Method for manufacturing chip metal interconnection lines and method for removing oxide layer

Abstract

The present invention relates to the field of semiconductor technology and discloses a method for fabricating chip metal interconnects and a method for removing an oxide layer. In actual use, the present invention completes the oxide layer removal and subsequent deposition process on the surface of a front-layer metal wire in a physical vapor deposition chamber, eliminating the need for an additional pre-cleaning etching chamber to etch away the oxide layer. This reduces the number of chambers required for fabricating chip metal interconnects and reduces maintenance costs. Furthermore, since the chip does not need to be transferred between chambers to remove the oxide layer on the surface of the front-layer metal wire, chip output is increased.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing chip metal interconnects and a method for removing oxide layers. Background Art

[0002] Integrated Circuits (ICs) are developing towards high density and low power consumption. The feature size of devices in ICs is decreasing. As the feature size becomes smaller and smaller, the interconnection lines are getting thinner, resulting in a decrease in the cross-section and line spacing of the interconnection leads. The parasitic effects caused by resistance, capacitance, and inductance are increasingly affecting the performance of the circuit.

[0003] In the selection of metal interconnects, aluminum has high conductivity (resistivity is only 2.65μΩ·cm) and low ohmic contact resistance with n-type, p-type silicon or polysilicon (can be as low as 10 -6 Ω / cm), excellent adhesion to silicon and phosphosilicate glass, and ease of deposition and etching. In traditional aluminum interconnect technology, the interconnection process involves first depositing a metal layer of aluminum on a dielectric layer, then etching using a photoresist as a mask to form the metal interconnect pattern. However, as integrated circuit manufacturing processes mature and feature sizes become smaller and smaller, aluminum interconnects have also exposed many fatal defects. For example, the high solubility of silicon in aluminum can cause the aluminum deposited on the silicon wafer to come into contact with the silicon, causing the silicon to dissolve in the aluminum and create cracks. The presence of these cracks can cause certain PN junctions to fail. Furthermore, with the rapid increase in the number of interconnect layers and lengths, and the decrease in interconnect width, the use of aluminum as the interconnect material is more susceptible to electromigration.

[0004] To ensure the conductivity of interconnects and improve their resistance to electromigration, copper is currently used in chips instead of aluminum as the interconnect material for integrated circuits. However, because copper is difficult to etch, the process used to make aluminum interconnects is difficult to apply to copper interconnects. To address this issue, the Damascene process is often used to fabricate metal interconnects on a substrate. During this process, metal interconnects are layered on the substrate. Before the subsequent metal layers are fabricated, the previous metal layers are exposed to the atmosphere for a long time, resulting in the formation of a metal oxide layer several nanometers thick on the surface of the previous metal layers. This metal oxide layer must be removed before the subsequent metal layers are fabricated, otherwise it will increase the resistance of the interconnects.

[0005] like Figure 1As shown, in the 55nm and 65nm process nodes, the existing technology for removing the metal oxide layer on the front metal wire is to place the corresponding chip structure in a pre-cleaning etching chamber of the AMAT ENDURA equipment to etch off the metal oxide layer. After the metal oxide layer etching is completed, the chip structure is transferred to the deposition chamber of the AMAT ENDURA equipment for deposition and subsequent process production. This manufacturing method will first occupy two cavities of the AMAT ENDURA equipment, increasing the cavity maintenance cost. In addition, since processing is carried out in two cavities, the chips need to be turned over, so the production efficiency is low. Summary of the Invention

[0006] In view of the shortcomings of the background technology, the present invention provides a method for manufacturing chip metal interconnect lines and a method for removing the oxide layer, which is suitable for 55nm and 65nm process nodes. By completing the removal of the metal oxide layer on the front-layer metal wire and the manufacture of the rear-layer metal wire in a physical vapor deposition chamber, the number of chambers required for manufacturing chip metal interconnect lines and the maintenance cost are reduced, thereby improving production efficiency.

[0007] To solve the above technical problems, in a first aspect, the present invention provides a method for removing an oxide layer of a chip metal interconnect line, comprising the following steps:

[0008] S1: Providing a physical vapor deposition chamber, wherein an electrostatic chuck, a target, a radio frequency magnetron device, and a direct current power supply device are arranged in the physical vapor deposition chamber, and the target is above the electrostatic chuck;

[0009] S2: Place the chip with the front-layer metal wires on the electrostatic chuck in the physical vapor deposition chamber;

[0010] S3: using ions to bombard the chip surface in a physical vapor deposition chamber to remove the oxide layer on the surface of the front metal wire.

[0011] In a certain embodiment of the first aspect, in step S3, an inert gas is introduced into the physical vapor deposition chamber, the radio frequency power of the radio frequency magnetron device is adjusted to generate ions from the inert gas, an AC power supply is input to the electrostatic chuck to generate a self-bias voltage, and the ions bombard the chip surface under the action of the self-bias voltage.

[0012] In a certain embodiment of the first aspect, in step S3, the RF power of the RF magnetron device is adjusted to between 300W and 600W, the power of the AC power supply is between 150W and 300W, and the duration of step S2 is between 2S and 5S.

[0013] In certain embodiments of the first aspect, the inert gas is argon.

[0014] In a second aspect, the present invention provides a method for manufacturing a chip metal interconnect line, applying the above-mentioned method for removing the oxide layer of the chip metal interconnect line, and performing step S4 after performing step S3. Step S4 is as follows:

[0015] S4: depositing a first metal layer on the chip surface;

[0016] S5: bombarding the surface of the first metal layer with ions to eliminate overhangs generated during the deposition of the first metal layer;

[0017] S6: Depositing a second metal layer on the surface of the first metal layer.

[0018] In a certain embodiment of the second aspect, in step S4, a DC power supply is supplied to the target material through the DC power supply device to generate a negative bias voltage, and the RF power of the RF magnetron device is adjusted to cause the inert gas to generate ions. The ions are bombarded toward the target material surface under the action of the negative bias voltage of the target material, and the target material atoms generated by the ion bombardment of the target material fall onto the surface of the chip to form a first metal layer.

[0019] In a certain embodiment of the second aspect, in step S5, the DC power supply to the target is stopped, and the AC power is input to the electrostatic chuck to generate a self-bias voltage for the electrostatic chuck. The RF power of the RF magnetron device is adjusted to cause the inert gas to generate ions. The ions generated by the inert gas are bombarded toward the surface of the first metal layer under the action of the self-bias voltage.

[0020] In a certain embodiment of the second aspect, in step S6, a DC power supply is supplied to the target material through the DC power supply device to generate a negative bias voltage, and the RF power of the RF magnetron device is adjusted to cause the inert gas to generate ions. The ions are bombarded toward the target material surface under the action of the negative bias voltage of the target material, and the target material atoms generated by the ion bombardment of the target material fall onto the surface of the chip to form a second metal layer.

[0021] In certain embodiments of the second aspect, the target material is a Ta target material.

[0022] The beneficial effects of the present invention compared with the prior art are: when the present invention is applied in a 55nm or 65nm process node, the present invention completes the removal of the oxide layer on the surface of the front metal wire and the subsequent deposition process in a physical vapor deposition chamber, without adding an additional pre-cleaning etching chamber to etch away the oxide layer on the surface of the front metal wire, thereby reducing the number of chambers and maintenance costs required for the production of chip metal interconnections, and because the chip does not need to be circulated between chambers due to the removal of the oxide layer on the surface of the front metal wire, the chip output is increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the structure of equipment used for making metal wires for existing chips;

[0024] Figure 2 is a flow chart of a method for removing an oxide layer from a chip metal interconnection line in an embodiment;

[0025] Figure 3 is a flow chart of a method for manufacturing a chip metal interconnection line in an embodiment;

[0026] Figure 4 It is a schematic diagram of the structure of preparing the first metal layer, eliminating the overhang on the first metal layer, and preparing the second metal layer in the embodiment. DETAILED DESCRIPTION

[0027] The illustrative embodiments of the present application include, but are not limited to, methods for fabricating chip metal interconnects and methods for removing oxide layers.

[0028] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0029] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a", "said" and "the" used in this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items. "Include" or "comprising" and similar words mean that the elements or objects appearing before "include" or "comprising" cover the elements or objects listed after "include" or "comprising" and their equivalents, and do not exclude other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect.

[0030] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are merely used to distinguish information of the same type from one another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of this application. Depending on the context, the term "if" as used herein may be interpreted as "when," "when," or "in response to determining."

[0031] When the metal interconnection lines of a chip are being manufactured, in order to prevent the oxide layer on the surface of the front-layer metal wires of the chip from affecting the overall working performance of the chip, the chip will be placed in a pre-cleaning etching chamber in advance to etch off the oxide layer on the surface of the front-layer metal wires when the back-layer metal wires are manufactured, and then the corresponding chip structure will be placed in a deposition chamber for deposition. Therefore, the existing chip metal interconnection lines require multiple cavities during manufacturing and require chip turnover, resulting in a higher overall manufacturing cost and lower manufacturing efficiency.

[0032] In order to solve the shortcomings of the existing chip metal interconnection process, such as Figure 2 As shown, this embodiment provides a method for removing the oxide layer of the metal interconnection line of a chip, comprising the following steps:

[0033] S1: Provide a physical vapor deposition chamber, which is equipped with an electrostatic chuck, a target material, a radio frequency magnetron device and a DC power supply device, and the target material is above the electrostatic chuck;

[0034] S2: Place the chip with the front-layer metal wires on the electrostatic chuck in the physical vapor deposition chamber;

[0035] S3: Use ions to bombard the chip surface in a physical vapor deposition chamber to remove the oxide layer on the surface of the front metal wire.

[0036] As a further technical solution, in this embodiment, in step S3, an inert gas is introduced into the physical vapor deposition chamber, the RF power of the RF magnetron device is adjusted to cause the inert gas to generate ions, and an AC power supply is input to the electrostatic chuck to generate a self-bias voltage. The ions bombard the wafer surface under the action of the self-bias voltage.

[0037] In actual use, a radio frequency magnetron device is used to generate an electric field in a physical vapor deposition chamber to generate ions from an inert gas, which is an existing technology.

[0038] Compared with using a single etching chamber to remove the front metal wires of the chip, the present invention uses ion sputtering in a physical vapor deposition chamber to bombard the oxide layer on the surface of the front metal wires of the chip, so an etching chamber can be saved in actual use.

[0039] Since ion sputtering is used to remove the oxide layer on the surface of the front metal wire of the chip, compared with depositing thin films by ion sputtering, when removing the oxide layer on the surface of the front metal wire, the voltage generated by the RF magnetron device and the self-bias voltage generated by the electrostatic chuck must be reduced.

[0040] Preferably, in step S3, the radio frequency power of the radio frequency magnetron device is adjusted to between 300W and 600W, the power of the AC power supply is between 150W and 300W, and the duration of step S3 is between 2S and 5S.

[0041] Specifically, in this embodiment, the inert gas is argon.

[0042] like Figure 3 As shown, this embodiment also provides a method for manufacturing chip metal interconnects, applying the above-mentioned method for removing the oxide layer of the chip metal interconnects, and performing step S4 after performing step S3. Step S4 is as follows:

[0043] S4: depositing a first metal layer 1 on the chip surface;

[0044] S5: using ions to bombard the surface of the first metal layer 1 to eliminate the overhang 2 generated when the first metal layer 1 is deposited;

[0045] S6 : Depositing a second metal layer 3 on the surface of the first metal layer 1 .

[0046] Specifically, in step S4, a DC power supply is supplied to the target material via a DC power supply device to generate a negative bias voltage. The RF power of the RF magnetron device is adjusted to generate ions from the inert gas. These ions, under the action of the negative bias voltage, bombard the target material surface. Target atoms generated by the ion bombardment fall onto the chip surface to form the first metal layer 1. In actual use, the AC power input to the electrostatic chuck in step S4 is between 150W and 400W.

[0047] In actual use, the target material is a Ta target material, and the first metal layer 1 is a Ta metal layer.

[0048] After executing step S4, ideally, the thickness of the first metal layer 1 on the chip surface is the same, but due to the presence of grooves on the chip surface, Figure 4 There is an overhang 2 at the corner of the first metal layer 1 in the trench. If the overhang 2 of the first metal layer 1 is not eliminated, the subsequent deposition process will be affected.

[0049] Specifically, in step S5, the DC power supply to the target is stopped, and an AC power supply is input to the electrostatic chuck to generate a self-bias voltage. The RF power of the RF magnetron device is adjusted to generate ions from the inert gas. The ions generated by the inert gas are bombarded toward the surface of the first metal layer 1 under the action of the self-bias voltage.

[0050] In actual use, in step S5, ion sputtering is used to eliminate overhangs generated during the deposition of the first metal layer 1. Furthermore, because the target of ion bombardment in step S5 is the surface of the first metal layer 1, i.e., the metal layer, rather than the surface of the oxide layer, the power input to the electrostatic chuck can be increased in step S5 to increase the energy of the ion bombardment of the first metal layer. The power of the AC power input to the electrostatic chuck in step S5 is between 500W and 1000W.

[0051] In step S6, a DC power supply is supplied to the target material through a DC power supply device to generate a negative bias voltage, and the RF power of the RF magnetron device is adjusted to generate ions in the inert gas. The ions are bombarded toward the target material surface under the action of the negative bias voltage of the target material, and the target material atoms generated by the ion bombardment fall onto the chip surface to form a second metal layer 3.

[0052] In actual use, step S6 is equivalent to secondary deposition, so the AC power input to the electrostatic chuck in step S6 is also between 150W and 400W.

[0053] In summary, when the present invention is applied in a 55nm or 65nm process node, the present invention completes the removal of the oxide layer on the surface of the front-layer metal wire and the subsequent deposition process in a physical vapor deposition chamber, without adding an additional pre-cleaning etching chamber to etch away the oxide layer, thereby reducing the number of chambers and maintenance costs required for chip metal interconnection production. In addition, since there is no need to transfer the chip between chambers due to the removal of the oxide layer on the surface of the front-layer metal wire, the chip output is increased.

[0054] The above description is for inspiration. Based on the above description, relevant personnel can make various changes and modifications without departing from the technical concept of this invention. The technical scope of this invention is not limited to the content of the specification, but must be determined according to the scope of the claims.

Claims

1. A method for manufacturing a chip metal interconnection line, characterized in that: The following steps are involved: S1: Providing a physical vapor deposition chamber, wherein an electrostatic chuck, a target, a radio frequency magnetron device, and a direct current power supply device are arranged in the physical vapor deposition chamber, and the target is above the electrostatic chuck; S2: Place the chip with the front-layer metal wires on the electrostatic chuck in the physical vapor deposition chamber; S3: Using ions to bombard the chip surface in a physical vapor deposition chamber to remove the oxide layer on the surface of the front metal wire; in step S3, an inert gas is introduced into the physical vapor deposition chamber, the radio frequency power of the radio frequency magnetron device is adjusted to generate ions from the inert gas, and an AC power supply is input to the electrostatic chuck to generate a self-bias voltage. The ions bombard the chip surface under the action of the self-bias voltage. S4: Depositing a first metal layer on the chip surface; in step S4, a DC power supply is supplied to the target material through the DC power supply device to generate a negative bias voltage, and the radio frequency power of the radio frequency magnetron device is adjusted to generate ions from the inert gas. The ions are bombarded toward the target material surface under the action of the negative bias voltage of the target material, and target material atoms generated by the target material bombardment by the ions fall onto the chip surface to form the first metal layer; S5: Bombarding the surface of the first metal layer with ions to eliminate overhangs generated during deposition of the first metal layer. In step S5, the DC power supply to the target is stopped, and an AC power supply is supplied to the electrostatic chuck to generate a self-bias voltage on the electrostatic chuck. The radio frequency power of the radio frequency magnetron device is adjusted to generate ions from the inert gas. The ions generated by the inert gas are bombarded toward the surface of the first metal layer under the action of the self-bias voltage. S6: Depositing a second metal layer on the surface of the first metal layer; in step S6, a DC power supply is supplied to the target material through the DC power supply device to generate a negative bias voltage, and the radio frequency power of the radio frequency magnetron device is adjusted to generate ions from the inert gas. The ions are bombarded toward the target material surface under the action of the negative bias voltage of the target material, and the target material atoms generated by the ion bombardment fall onto the chip surface to form the second metal layer; In step S3, the radio frequency power of the radio frequency magnetron device is adjusted to between 300W and 600W, the power of the AC power supply is between 150W and 300W, and the duration of step S3 is between 2S and 5S.

2. The method for manufacturing chip metal interconnection lines according to claim 1, characterized in that: The inert gas is argon.

3. The method for manufacturing chip metal interconnection lines according to claim 1, characterized in that: The target material is a Ta target material.

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