Manufacturing Method of High-Power Radio Frequency Devices

Abstract

The present invention provides a manufacturing method of a high-power radio frequency device, comprising: first, providing a high-power radio frequency semiconductor structure, including: a first region of a substrate and a first electrode, a second electrode and a third electrode; then, opening a first blind hole and a second blind hole in the substrate from the front, forming a fourth electrode in the first blind hole and a fifth electrode in the second blind hole; thereafter, forming a metal interconnection layer on the fourth electrode, the fifth electrode, a second region of the substrate and the high-power radio frequency semiconductor structure, including a ground electrode electrically connected to the second electrode, an input electrode electrically connected to the first electrode and the fourth electrode, and an output electrode electrically connected to the third electrode and the fifth electrode; then, forming a ground pad electrically connected to the ground electrode on the metal interconnection layer; thereafter, thinning the substrate from the back until the fourth electrode and the fifth electrode are exposed, forming an input pad electrically connected to the fourth electrode and an output pad electrically connected to the fifth electrode. Reducing the device thermal resistance, process cost and improving the yield rate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a manufacturing method of a high-power radio frequency device. Background Art

[0002] High-power radio frequency devices, such as radio frequency power amplifiers, are important components of various wireless transmitters. In a transmitting system, the output power of a radio frequency power amplifier can be as high as several hundred watts. Therefore, the heat dissipation effect of the radio frequency power amplifier determines the reliability and cost of the entire amplifier operation.

[0003] In related technologies, high-quality third-generation semiconductor gallium nitride materials are directly grown and deposited on a silicon substrate, which can significantly reduce the manufacturing cost of gallium nitride devices by leveraging large-size, low-cost silicon wafers and their automated process lines. However, due to the poor thermal conductivity of silicon, even if the gallium nitride wafer based on the silicon substrate is thinned as much as possible, its thermal resistance will still be relatively large, making it difficult to obtain excellent heat dissipation performance. In addition, due to the large lattice mismatch between the silicon substrate lattice and the gallium nitride lattice, the thinning degree of the gallium nitride wafer based on the silicon substrate is limited, which results in that the gallium nitride radio frequency power amplifier chip based on the silicon substrate is difficult to be used in radio frequency power amplifiers for a new generation of wireless communication base stations due to the poor heat dissipation problem. Summary of the Invention

[0004] The object of the present invention is to provide a manufacturing method of a high-power radio frequency device, which can obtain a lower device thermal resistance while ensuring the high-frequency performance of the device.

[0005] To achieve the above object, the present invention provides a manufacturing method of a high-power radio frequency device, including:

[0006] Providing a high-power radio frequency semiconductor structure, the high-power radio frequency semiconductor structure including: a first region of a substrate and a first electrode, a second electrode, and a third electrode located on the front surface of the first region, the second electrode and the third electrode being located on both sides of the first electrode;

[0007] Forming a first blind hole and a second blind hole in the substrate from the front surface of the substrate; forming a fourth electrode at least in the first blind hole and forming a fifth electrode at least in the second blind hole;

[0008] Forming a metal interconnection layer on the fourth electrode, the fifth electrode, a second region of the substrate, and the high-power radio frequency semiconductor structure; the metal interconnection layer including a ground electrode, an input electrode, and an output electrode; the ground electrode being electrically connected to the second electrode, the input electrode being electrically connected to the first electrode and the fourth electrode, and the output electrode being electrically connected to the third electrode and the fifth electrode;

[0009] A ground pad is formed on a side of the metal interconnect layer away from the substrate, and the ground pad is electrically connected to the ground electrode;

[0010] The substrate is thinned from the back side until the fourth electrode and the fifth electrode are exposed; an input pad and an output pad are formed on the back side of the substrate, the input pad is electrically connected to the fourth electrode, and the output pad is electrically connected to the fifth electrode.

[0011] Optionally, the high-power radio frequency semiconductor structure is an LDMOS structure or a HEMT structure, the first electrode is a gate electrode, the second electrode is a source electrode, and the third electrode is a drain electrode.

[0012] Optionally, the high-power radio frequency semiconductor structure is an HBT structure, the first electrode is a base electrode, the second electrode is a collector electrode, and the third electrode is an emitter electrode.

[0013] Optionally, the metal interconnect layer includes a second dielectric layer; before the step of forming the ground pad, a third dielectric layer is covered on a side of the metal interconnect layer away from the substrate, and the ground pad is formed on the third dielectric layer; the dielectric constant of the third dielectric layer is less than that of the second dielectric layer, and the thermal conductivity of the third dielectric layer is greater than that of the substrate.

[0014] Optionally, the dielectric constant of the third dielectric layer is less than that of the substrate.

[0015] Optionally, the substrate includes at least one of single-crystalline silicon, single-crystalline diamond, silicon carbide, gallium nitride, and sapphire; and / or the material of the second dielectric layer is at least one of silicon dioxide, silicon nitride, and silicon oxynitride; and / or the material of the third dielectric layer is at least one of polycrystalline diamond, amorphous diamond, polycrystalline silicon carbide, and amorphous silicon carbide.

[0016] Optionally, the thickness range of the third dielectric layer is 5 μm to 20 μm.

[0017] Optionally, the third dielectric layer is formed by at least one of microwave plasma chemical vapor deposition, inductively coupled plasma chemical vapor deposition, pulsed laser deposition, and electron cyclotron resonance chemical vapor deposition, and the deposition temperature is less than or equal to 400 °C.

[0018] Optionally, the substrate includes the first region and the second region, and the orthographic projections of the fourth electrode, the fifth electrode, the input electrode, and the output electrode on the plane where the substrate is located are located in the second region.

[0019] Optionally, the ground electrode is electrically connected to the second electrode through the metal interconnect layer, the input electrode is electrically connected to the first electrode and the fourth electrode through the metal interconnect layer, and the output electrode is electrically connected to the third electrode and the fifth electrode through the metal interconnect layer.

[0020] Optionally, the high-power radio frequency semiconductor structure includes: a first dielectric layer covering the front surface of the substrate, the first electrode, the second electrode, and the third electrode; the first blind hole and the second blind hole are formed in the substrate and the first dielectric layer.

[0021] Optionally, the steps of forming at least the fourth electrode in the first blind hole and at least the fifth electrode in the second blind hole include:

[0022] Form a metal layer on the side of the first dielectric layer away from the substrate and on the entire surface within the first blind hole and the second blind hole;

[0023] Polish the metal layer until the first dielectric layer is exposed, and the metal layer remaining in the first blind hole forms the fourth electrode, and the metal layer remaining in the second blind hole forms the fifth electrode.

[0024] Optionally, the metal layer fills the first blind hole and the second blind hole, or the metal layer is formed on the inner walls of the first blind hole and the second blind hole.

[0025] Optionally, between the step of covering the third dielectric layer and the step of forming the ground pad, the manufacturing method of the high-power radio frequency device further includes: covering a passivation layer on the third dielectric layer, and the thickness ratio of the passivation layer to the second dielectric layer ranges from 0.025 to 0.3.

[0026] Optionally, the passivation layer is a single-layer structure, and the material of the single-layer structure is silicon nitride; or the passivation layer is a laminated structure, and in the direction away from the second dielectric layer, the laminated structure sequentially includes a silicon dioxide layer and a silicon nitride layer.

[0027] Optionally, the manufacturing method of the high-power radio frequency device further includes:

[0028] Provide a package case;

[0029] Mount the ground pad on the package case, and lead out the input pad and the output pad to the outside of the package case through metal leads.

[0030] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0031] 1. Fabricate a ground pad on the front side of the substrate, and fabricate an input pad and an output pad on the back side of the substrate; during encapsulation, simply mount the ground pad on the encapsulation package and lead out the input pad and the output pad to the outside of the encapsulation package by wire bonding. The heat dissipation capacity of the multi-layer structure located on the front side of the substrate can be made greater than that of the substrate itself by controlling the layer settings, material types, and thicknesses of the multi-layer structure on the front side of the substrate. Therefore, the thermal resistance encountered during the conduction of the heat generated during the operation of the high-power RF device through the heat conduction path of "the multi-layer structure on the front side of the substrate → the package" is smaller than that encountered during the conduction through the heat conduction path of "the substrate → the package", thereby ensuring the high-frequency performance of the device.

[0032] 2. The electrical connection between the input pad on the back side of the substrate and the first electrode is achieved by: first, forming a first blind hole in the substrate from the front side, and forming at least a fourth electrode in the first blind hole; then, forming a metal interconnect layer on the front side of the substrate, where the metal interconnect layer includes an input electrode that electrically connects the first electrode and the fourth electrode; then, thinning the substrate from the back side until the fourth electrode is exposed, and forming an input pad on the back side of the substrate that electrically connects the fourth electrode. The electrical connection between the output pad on the back side of the substrate and the third electrode is achieved by: first, forming a second blind hole in the substrate from the front side, and forming at least a fifth electrode in the second blind hole; then, forming a metal interconnect layer on the front side of the substrate, where the metal interconnect layer includes an output electrode that electrically connects the third electrode and the fifth electrode; then, thinning the substrate from the back side until the fifth electrode is exposed, and forming an output pad on the back side of the substrate that electrically connects the fifth electrode. Compared with the process flow of first forming a metal interconnect layer on the front side of the substrate, where the metal interconnect layer includes an input electrode and an output electrode, the input electrode electrically connects the first electrode, and the output electrode electrically connects the third electrode; then, forming a first through hole and a second through hole in the substrate and the metal interconnect layer from the back side of the substrate, the first through hole exposes the input electrode, and the second through hole exposes the output electrode; then, forming an input pad that electrically connects the input electrode and an output pad that electrically connects the output electrode on the back side of the substrate, the advantages of this application are as follows:

[0033] 1) Double-sided alignment is not required, reducing equipment and process costs;

[0034] 2) The thermal budget of the back-side process of the substrate can be reduced. In the process of etching through holes on the back side, generally a high-power plasma etching process is required, which will generate a large amount of heat in the substrate; if the heat dissipation capacity is limited, it will cause the adhesive layer (the denaturation temperatures of different materials are different, generally <250 °C) that bonds the substrate and the carrier plate to denature, resulting in residual denatured organic matter on the surface of the substrate after the subsequent removal of the carrier plate, leading to device contamination and failure;

[0035] 3) The electrical connection reliability between the input electrode and the output electrode can be prevented from deteriorating. In the process of etching vias on the back surface, a high-power plasma etching process is generally required. Excessive etching with high power may cause the input electrode and the output electrode to be etched through, affecting the reliability.

[0036] Thirdly, setting a ground pad on one side of the front surface of the substrate for grounding can reduce the ground inductance of the RF device, improve the gain and cut-off frequency of the RF device, and thus enhance the high-frequency characteristics of the RF device. Description of the Drawings

[0037] Figure 1 is a flowchart of the manufacturing method of the high-power RF device according to the first embodiment of the present invention;

[0038] Figures 2 to 10 is Figure 1 the corresponding intermediate structure diagram of the manufacturing method;

[0039] Figures 11 to 13 is the corresponding intermediate structure diagram of the manufacturing method of the high-power RF device according to the second embodiment of the present invention;

[0040] Figures 14 to 15 is the corresponding intermediate structure diagram of the manufacturing method of the high-power RF device according to the third embodiment of the present invention;

[0041] Figure 16 is the corresponding intermediate structure diagram of the manufacturing method of the high-power RF device according to the fourth embodiment of the present invention;

[0042] Figure 17 is the corresponding intermediate structure diagram of the manufacturing method of the high-power RF device according to the fifth embodiment of the present invention.

[0043] For easy understanding of the present invention, all the reference numerals appearing in the present invention are listed below:

[0044] Substrate 10, First region 10a

[0045] Second region 10b, Front surface 10c

[0046] Back surface 10d, High-power RF semiconductor structure 101

[0047] First electrode, gate 101a, Second electrode, source 101b

[0048] Fourth electrode, drain 101c, Heterojunction structure 101d

[0049] P-type semiconductor layer 101e, First dielectric layer 1011

[0050] First blind hole 102, Second blind hole 103

[0051] Metal layer 11, fourth electrode 111

[0052] Fifth electrode 112, metal interconnection layer 12

[0053] Second dielectric layer 120, ground electrode 121

[0054] Input electrode 122, output electrode 123

[0055] Third dielectric layer 13, ground pad 141

[0056] Input pad 142, output pad 143

[0057] Passivation layer 15, package case 20 Detailed implementation manners

[0058] To make the above objects, features and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention is provided in conjunction with the accompanying drawings.

[0059] Figure 1 is a flowchart of a manufacturing method of a high-power radio frequency device according to the first embodiment of the present invention; Figures 2 to 10 is Figure 1 a corresponding intermediate structure schematic diagram of the manufacturing method.

[0060] First, referring to Figure 1 in step S1 and Figure 2 as shown, a high-power radio frequency semiconductor structure 101 is provided. The high-power radio frequency semiconductor structure 101 includes: a first region 10a of a substrate 10 and a first electrode 101a, a second electrode 101b, and a third electrode 101c located on the front surface 10c of the first region 10a. The second electrode 101b and the third electrode 101c are located on both sides of the first electrode 101a.

[0061] The material of the substrate 10 can be materials such as single-crystal silicon, single-crystal diamond, sapphire, silicon carbide, or gallium nitride.

[0062] Referring to Figure 1 as shown, the substrate 10 includes a first region 10a and a second region 10b, and the second region 10b can be disposed around the first region 10a.

[0063] The high-power radio frequency semiconductor structure 101 is formed in the first region 10a. In this embodiment, the high-power radio frequency semiconductor structure 101 is an LDMOS structure or an HEMT structure. Correspondingly, the first electrode 101a is a gate electrode, the second electrode 101b is a source electrode, and the third electrode 101c is a drain electrode.

[0064] Taking the HEMT semiconductor structure as an example, a heterojunction structure 101d can be formed on the first region 10a. The heterojunction structure 101d can include a channel layer close to the substrate 10 and a barrier layer far from the substrate 10. A two-dimensional electron gas can be formed at the interface between the channel layer and the barrier layer. The materials of both the channel layer and the barrier layer can be GaN-based materials, and the bandgap width of the barrier layer is greater than that of the channel layer. The material of the barrier layer can be AlGaN, and the material of the channel layer can be GaN.

[0065] The heterojunction structure 101d includes a gate region, and a source region and a drain region on both sides of the gate region. A P-type semiconductor layer 101e can be provided on the gate region to consume the excess two-dimensional electron gas in the channel and form an enhancement-mode HEMT device. A gate 101a can be provided on the side of the P-type semiconductor layer 101e far from the substrate 10 to control the turn-off or turn-on of the channel region.

[0066] The source 101b contacts the source region of the heterojunction structure, and the drain 101c contacts the drain region of the heterojunction structure. The source 101b and the drain 101c can contact the channel layer of the heterojunction structure.

[0067] In other embodiments, the high-power radio frequency semiconductor structure 101 can also be an HBT structure. Correspondingly, the first electrode 101a is the base, the second electrode 101b is the collector, and the third electrode 101c is the emitter. In addition, in some embodiments, the high-power radio frequency semiconductor structure 101 can also be two or more of an HEMT structure, an LDMOS structure, and an HBT structure.

[0068] In this embodiment, referring to Figure 1 as shown, the high-power radio frequency semiconductor structure 101 further includes: a first dielectric layer 1011, and the first dielectric layer 1011 covers the front surface 10c of the substrate 10, the source 101b, the drain 101c, and the gate 101a.

[0069] The surface of the first dielectric layer 1011 far from the substrate 10 is flat. The material of the first dielectric layer 1011 can be one or a combination of silicon dioxide, silicon nitride, and silicon oxynitride, or the first dielectric layer 1011 is a laminated structure composed of different material layers.

[0070] In other embodiments, the first dielectric layer 1011 can also be omitted.

[0071] Next, referring to Figure 1 the steps S2 in Figure 3 and as shown in Figure 5 a first blind hole 102 and a second blind hole 103 are formed in the substrate 10 from the front surface 10c of the substrate 10; referring to Figure 5 as shown, a fourth electrode 111 is formed in the first blind hole 102 and a fifth electrode 112 is formed in the second blind hole 103.

[0072] The first blind hole 102 and the second blind hole 103 can be formed by dry etching using a patterned photoresist as a mask.

[0073] The depth range of the first blind hole 102 and the second blind hole 103 can be 100μm to 300μm. The numerical range in this embodiment includes the endpoint values.

[0074] In this embodiment, the first blind hole 102 and the second blind hole 103 are located on one side of the high-power radio frequency semiconductor structure 101. In other embodiments, the first blind hole 102 and the second blind hole 103 can also be arranged to surround the high-power radio frequency semiconductor structure 101.

[0075] In this embodiment, the orthographic projection of the first blind hole 102 and the second blind hole 103 on the plane of the substrate 10 is located in the second region 10b. In other embodiments, on the premise of not affecting the performance of the high-power radio frequency semiconductor structure 101, the orthographic projection of the first blind hole 102 and the second blind hole 103 on the plane of the substrate 10 can also partially overlap with the first region 10a.

[0076] Forming the fourth electrode 111 and the fifth electrode 112 can specifically include steps S21 and S22.

[0077] Step S21: Refer to Figure 4 As shown, a metal layer 11 is formed entirely on the side of the first dielectric layer 1011 away from the substrate 10 and within the first blind hole 102 and the second blind hole 103.

[0078] In this embodiment, refer to Figure 4 As shown, the metal layer 11 fills the first blind hole 102 and the second blind hole 103. The material of the metal layer 11 can be at least one of aluminum, copper, and tungsten. Before the step of forming the metal layer 11, an adhesion layer can be formed entirely, and the material can be at least one of titanium, titanium nitride, and nickel. The metal layer 11 can be formed entirely by sputtering or chemical vapor deposition.

[0079] Step S22: Refer to Figure 5 As shown, the metal layer 11 is polished until the first dielectric layer 1011 is exposed, and the metal layer 11 remaining in the first blind hole 102 forms the fourth electrode 111, and the metal layer 11 remaining in the second blind hole 103 forms the fifth electrode 112.

[0080] The metal layer 11 can be polished by chemical mechanical polishing.

[0081] For the embodiment where the first metal dielectric layer 1011 is omitted, before forming the metal layer 11, a photoresist layer can be coated on the high-power radio frequency semiconductor structure 101. The metal layer 11 can be patterned to form the fourth electrode 111 and the fifth electrode 112. After that, the excess photoresist layer can be removed by ashing.

[0082] After that, referring to Figure 1 step S3 in Figure 6 as shown, a metal interconnect layer 12 is formed on the fourth electrode 111, the fifth electrode 112, the second region 10b, and the high-power radio frequency semiconductor structure 101; the metal interconnect layer 12 includes a ground electrode 121, an input electrode 122, and an output electrode 123; the ground electrode 121 is electrically connected to the second electrode 101b, the input electrode 122 is electrically connected to the first electrode 101a and the fourth electrode 111, and the output electrode 123 is electrically connected to the third electrode 101c and the fifth electrode 112.

[0083] In this embodiment, the metal interconnect layer 12 includes a second dielectric layer 120. The ground electrode 121 is electrically connected to the source electrode 101b through the metal interconnect layer 12, the input electrode 122 is electrically connected to the gate electrode 101a and the fourth electrode 111 through the metal interconnect layer 12, and the output electrode 123 is electrically connected to the drain electrode 101c and the fifth electrode 112 through the metal interconnect layer 12.

[0084] The second dielectric layer 120 can be an interlayer dielectric layer (ILD). The material of the interlayer dielectric layer can be silicon dioxide, silicon nitride, or silicon oxynitride, and is formed by physical vapor deposition or chemical vapor deposition correspondingly.

[0085] The materials of the ground electrode 121, the input electrode 122, and the output electrode 123 can be at least one of aluminum, gold, copper, and silver, and are formed by sputtering or chemical vapor deposition correspondingly.

[0086] In this embodiment, the ground electrode 121, the input electrode 122, and the output electrode 123 are located on one side of the high-power radio frequency semiconductor structure 101. In other embodiments, the ground electrode 121, the input electrode 122, and the output electrode 123 can also be arranged to surround the high-power radio frequency semiconductor structure 101.

[0087] In this embodiment, the orthographic projections of the ground electrode 121, the input electrode 122, and the output electrode 123 on the plane of the substrate 10 are located in the second region 10b. In other embodiments, on the premise of not affecting the performance of the high-power radio frequency semiconductor structure 101, the orthographic projections of the ground electrode 121, the input electrode 122, and the output electrode 123 on the plane of the substrate 10 can also partially overlap with the first region 10a.

[0088] Then, referring to Figure 1 step S4 inFigure 8 As shown, a ground pad 141 is formed on the side of the metal interconnect layer 12 away from the substrate 10, and the ground pad 141 is electrically connected to the ground electrode 121.

[0089] This step S4 specifically includes steps S41 and S42.

[0090] Step S41: Refer to Figure 7 As shown, a third dielectric layer 13 is covered on the side of the metal interconnect layer 12 away from the substrate 10.

[0091] In this embodiment, the dielectric constant of the third dielectric layer 13 is less than that of the second dielectric layer 120, and the thermal conductivity of the third dielectric layer 13 is greater than that of the substrate 10. Compared with the embodiment where the third dielectric layer 13 and the second dielectric layer 120 are made of the same material, this embodiment can further reduce the thermal resistance of the device while ensuring the high-frequency performance of the device. The reason is that: due to the large thermal resistance of the substrate 10, the heat dissipation performance of the heat dissipation path from the back of the substrate 10 is poor, so the heat dissipation path from the front of the substrate 10 is considered for heat dissipation; this requires the third dielectric layer 13 to be thinner to reduce the thermal resistance, but if the thickness is too thin, the parasitic capacitance will increase, restricting the high-frequency performance of the device; the third dielectric layer 13 is made of a material with a large thermal conductivity and a small dielectric constant. A large thermal conductivity can significantly improve the heat dissipation performance of the device, so the thickness can be thicker, and combined with a small dielectric constant, the parasitic capacitance can be reduced. It is especially suitable for high-frequency power semiconductor devices and radio frequency / millimeter-wave monolithic integrated circuits with strict requirements for heat dissipation ability and parasitic electrical parameters.

[0092] When the dielectric constant of the third dielectric layer 13 is less than that of the substrate 10, the parasitic capacitance can be further reduced.

[0093] The material of the third dielectric layer 13 that meets the above conditions can be at least one of polycrystalline diamond, amorphous diamond, polycrystalline silicon carbide, and amorphous silicon carbide, and is formed by using one or a combination of physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and inductively coupled plasma chemical vapor deposition (ICP-CVD). Preferably, it is formed by using one or a combination of microwave plasma chemical vapor deposition (MPCVD), inductively coupled plasma chemical vapor deposition (ICP-CVD), pulsed laser deposition (PLD), and electron cyclotron resonance chemical vapor deposition (ECR-CVD). The deposition temperature of the above processes can be relatively low, for example, less than or equal to 400 °C, without affecting the performance of the high-power radio frequency semiconductor structure 101.

[0094] The third dielectric layer 13 can also be a laminated structure composed of the following different material layers: polycrystalline diamond, amorphous diamond, polycrystalline silicon carbide, and amorphous silicon carbide.

[0095] The thickness of the third dielectric layer 13 ranges from 5 μm to 20 μm, preferably from 10 μm to 20 μm.

[0096] Step S42: Refer to Figure 8 As shown, a ground pad 141 is formed on the side of the third dielectric layer 13 away from the substrate 10, and the ground pad 141 is electrically connected to the ground electrode 121.

[0097] In this embodiment, forming the ground pad 141 may include: opening a through hole in the third dielectric layer 13 to expose the ground electrode 121; filling the through hole and forming the ground pad 141 on the side of the third dielectric layer 13 away from the substrate 10.

[0098] The through hole can be formed by dry etching. The ground pad 141 can be formed entirely by physical vapor deposition or electroplating, and the material can be a metal such as Au, Ag, Cu, or Al, and the thickness can be greater than or equal to 3 μm.

[0099] After that, refer to Figure 1 Steps S5 in Figure 9 As shown, the substrate 10 is thinned from the back surface 10d until the fourth electrode 111 and the fifth electrode 112 are exposed; refer to Figure 10 As shown, an input pad 142 and an output pad 143 are formed on the back surface 10d of the substrate 10, the input pad 142 is electrically connected to the fourth electrode 111, and the output pad 143 is electrically connected to the fifth electrode 112.

[0100] Before thinning the substrate 10, the ground pad 141 can be adhered to the carrier plate, and the material of the adhesive layer can be paraffin, thermosetting glue, or UV curable glue, etc.

[0101] The substrate 10 can be thinned by a grinding method, such as grinding with a grinding wheel.

[0102] The input pad 142 and the output pad 143 can be formed by physical vapor deposition or electroplating, and the material can be a metal such as Au, Ag, Cu, or Al, and the thickness can be greater than or equal to 3 μm.

[0103] When the substrate 10 is a non-insulating semiconductor material, such as doped single crystal silicon, non-insulating silicon carbide, or non-insulating gallium nitride and other materials, before forming the input pad 142 and the output pad 143, an insulating layer can be formed on the back surface 10d of the substrate 10. The material of the insulating layer can be silicon nitride or silicon dioxide, and the thickness can be greater than or equal to 0.5 μm. The input pad 142 and the output pad 143 are formed on the insulating layer.

[0104] When the substrate 10 is an insulating material, such as single-crystal diamond, sapphire, etc., the fabrication of the insulating layer can be omitted, and the input pad 142 and the output pad 143 are directly formed on the back surface 10d of the substrate 10.

[0105] The thinner the thickness of the substrate 10, the better the heat dissipation performance, but if the thickness is too thin, the substrate 10 will be broken during the thinning process.

[0106] In this embodiment, the high-power RF device can be used in high-power RF amplifiers, communication base stations, vehicle-mounted radars, etc.

[0107] Figures 11 to 13 It is a schematic diagram of an intermediate structure corresponding to the manufacturing method of the high-power RF device according to the second embodiment of the present invention.

[0108] Referring to Figures 11 to 13 As shown, the manufacturing method of the high-power RF device in the second embodiment is substantially the same as that of the high-power RF device in the first embodiment, and the only difference is that: referring to Figure 11 As shown, in step S21, the thickness of the metal layer 11 formed on the entire surface is relatively thin and does not fill the first blind hole 102 and the second blind hole 103, only covering the inner walls of the first blind hole 102 and the second blind hole 103; referring to Figure 12 As shown, after polishing the metal layer 11 until the first dielectric layer 1011 is exposed, the metal layer 11 on the inner wall of the first blind hole 102 forms the fourth electrode 111, and the metal layer 11 on the inner wall of the second blind hole 103 forms the fifth electrode 112.

[0109] In other words, the fourth electrode 111 and the fifth electrode 112 in this embodiment are annular on the surface of the first dielectric layer 1011 away from the substrate 10.

[0110] Referring to Figure 13 As shown, the first recessed area surrounded by the fourth electrode 111 and the second recessed area surrounded by the fifth electrode 112 can be filled with the second dielectric layer 120 when forming the metal interconnection layer 12 in step S3.

[0111] In other embodiments, referring to Figure 11 As shown, a fourth dielectric layer (not shown) can also be formed on the entire surface of the metal layer 11, and the fourth dielectric layer fills the first recessed area and the second recessed area surrounded by the metal layer 11. The position of the first recessed area corresponds to the first blind hole 102, and the position of the second recessed area corresponds to the second blind hole 103; then polish the fourth dielectric layer and the metal layer 11 until the first dielectric layer 1011 is exposed. Or referring to Figure 12As shown, a fourth dielectric layer (not shown) is formed over the entire surface of the fourth electrode 111, the fifth electrode 112, and the first dielectric layer 1011. The fourth dielectric layer fills the first recessed area surrounded by the fourth electrode 111 and the second recessed area surrounded by the fifth electrode 112; then the fourth dielectric layer is polished until the first dielectric layer 1011 is exposed. The metal interconnect layer 12 is formed on the first dielectric layer 1011, the fourth electrode 111, the fifth electrode 112, and the fourth dielectric layer.

[0112] The metal interconnect layer 12 can be connected to the entire circle of the fourth electrode 111 or to a certain annular section of the fourth electrode 111; and / or the metal interconnect layer 12 can be connected to the entire circle of the fifth electrode 112 or to a certain annular section of the fifth electrode 112.

[0113] Figures 14 to 15 It is a schematic diagram of an intermediate structure corresponding to the manufacturing method of the high-power radio frequency device according to the third embodiment of the present invention.

[0114] Refer to Figures 14 to 15 As shown, the manufacturing method of the high-power radio frequency device in the third embodiment is substantially the same as that of the high-power radio frequency device in the second embodiment, and the difference is only that: refer to Figure 14 As shown, in step S22, a patterning process replacement polishing method is used for the metal layer 11. After the metal layer 11 is patterned, the first section and the second section distributed in a partitioned manner are formed; the first section is located on the inner wall of the first blind hole 102 and the surface of the first dielectric layer 1011 away from the substrate 10, and the second section is located on the inner wall of the second blind hole 103 and the surface of the first dielectric layer 1011 away from the substrate 10.

[0115] The first section located on the surface of the first dielectric layer 1011 away from the substrate 10 forms the fourth electrode 111, and the second section located on the surface of the first dielectric layer 1011 away from the substrate 10 forms the fifth electrode 112.

[0116] The patterning process for the metal layer 11 can be achieved by dry etching using a patterned photoresist as a mask.

[0117] Refer to Figure 15 As shown, the metal interconnect layer 12 is connected to the fourth electrode 111 and the fifth electrode 112 respectively.

[0118] Figure 16 It is a schematic diagram of an intermediate structure corresponding to the manufacturing method of the high-power radio frequency device according to the fourth embodiment of the present invention.

[0119] Refer to Figure 16As shown, the manufacturing method of the high-power RF device in the fourth embodiment is substantially the same as that of the high-power RF devices in the first to third embodiments, with the only difference being that between step S41 and step S42, it further includes: covering a passivation layer 15 on the side of the third dielectric layer 13 away from the substrate 10.

[0120] The thickness ratio range of the passivation layer 15 to the third dielectric layer 13 can be 0.025 to 0.3. The numerical range in this embodiment includes the end values.

[0121] In this embodiment, the passivation layer 15 is a single-layer structure, and the material of the single-layer structure is silicon nitride. In other embodiments, the passivation layer 15 can also be a laminated structure, and in the direction away from the third dielectric layer 13, the laminated structure sequentially includes a silicon dioxide layer and a silicon nitride layer. The passivation layer 15 can prevent the invasion of chemical substances such as water vapor, salt spray, and metal ions that may cause chip failure.

[0122] In this embodiment, the ground pad 141 is electrically connected to the ground electrode 121 through a through hole opened in the passivation layer 15 and the third dielectric layer 13.

[0123] The passivation layer 15 is correspondingly formed by physical vapor deposition or chemical vapor deposition.

[0124] Figure 17 It is a schematic diagram of an intermediate structure corresponding to the manufacturing method of the high-power RF device in the fifth embodiment of the present invention.

[0125] Refer to Figure 17 As shown, the high-power RF device and its manufacturing method in the fifth embodiment are substantially the same as those of the high-power RF devices in the first to fourth embodiments, with the only difference being that it further includes:

[0126] Step S6: Provide a packaging case 20;

[0127] Step S7: Mount the ground pad 141 on the packaging case 20, and lead the input pad 142 and the output pad 143 out of the packaging case 20 through metal leads (not labeled).

[0128] The packaging of the high-power RF device can be in the form of ceramic packaging, metal packaging, plastic packaging, etc.

[0129] The ground pad 141 can be mounted on the packaging case 20 by a bonding method or a soldering method. The soldering material can be materials such as SnAu, SnAg, PbSnAg, or SnAgCu.

[0130] In the manufacturing method of the high-power radio frequency device of this embodiment, by controlling the settings of each layer, the types of materials, and the thickness of the multi-layer structure located on one side of the front surface 10c of the substrate, its heat dissipation capacity is made greater than that of the substrate 10 itself, thereby reducing the thermal resistance Tjc from the device junction area to the package case 20, significantly improving the heat dissipation capacity of the device / circuit, and thus enabling the device to have a higher output power level and higher reliability.

[0131] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A manufacturing method of a high-power radio frequency device, characterized in that Comprising: Providing a high-power radio frequency semiconductor structure, the high-power radio frequency semiconductor structure comprising: a first region of a substrate and a first electrode, a second electrode and a third electrode located on a front surface of the first region, the second electrode and the third electrode being located on both sides of the first electrode; Forming a first blind hole and a second blind hole in the substrate from the front surface of the substrate; forming a fourth electrode at least in the first blind hole and forming a fifth electrode at least in the second blind hole; Forming a metal interconnect layer on the fourth electrode, the fifth electrode, a second region of the substrate, and the high-power radio frequency semiconductor structure; the metal interconnect layer comprising a ground electrode, an input electrode, and an output electrode; the ground electrode being electrically connected to the second electrode, the input electrode being electrically connected to the first electrode and the fourth electrode, and the output electrode being electrically connected to the third electrode and the fifth electrode; Forming a ground pad on a side of the metal interconnect layer away from the substrate, the ground pad being electrically connected to the ground electrode; Thinning the substrate from the back surface until the fourth electrode and the fifth electrode are exposed; forming an input pad and an output pad on the back surface of the substrate, the input pad being electrically connected to the fourth electrode, and the output pad being electrically connected to the fifth electrode; wherein, The high-power radio frequency semiconductor structure is an LDMOS or HEMT structure, the first electrode is a gate electrode, the second electrode is a source electrode, and the third electrode is a drain electrode; or The high-power radio frequency semiconductor structure is an HBT structure, the first electrode is a base electrode, the second electrode is a collector electrode, and the third electrode is an emitter electrode.

2. The manufacturing method of the high-power radio frequency device according to claim 1, wherein The metal interconnect layer includes a second dielectric layer; before the step of forming the ground pad, a third dielectric layer is covered on a side of the metal interconnect layer away from the substrate, and the ground pad is formed on the third dielectric layer; the dielectric constant of the third dielectric layer is less than the dielectric constant of the second dielectric layer, and the thermal conductivity of the third dielectric layer is greater than the thermal conductivity of the substrate.

3. The manufacturing method of the high-power radio frequency device according to claim 2, wherein The dielectric constant of the third dielectric layer is less than the dielectric constant of the substrate.

4. The manufacturing method of the high-power radio frequency device according to claim 2 or 3, characterized in that The substrate includes at least one of single-crystalline silicon, single-crystalline diamond, silicon carbide, gallium nitride, and sapphire; and / or the material of the second dielectric layer is at least one of silicon dioxide, silicon nitride, and silicon oxynitride; and / or the material of the third dielectric layer is at least one of polycrystalline diamond, amorphous diamond, polycrystalline silicon carbide, and amorphous silicon carbide.

5. The manufacturing method of the high-power radio frequency device according to claim 2 or 3, characterized in that The thickness range of the third dielectric layer is 5 μm to 20 μm.

6. The manufacturing method of the high-power radio frequency device according to claim 2 or 3, characterized in that The third dielectric layer is formed by at least one of microwave plasma chemical vapor deposition, inductively coupled plasma chemical vapor deposition, pulsed laser deposition, and electron cyclotron resonance chemical vapor deposition, and the deposition temperature is less than or equal to 400 °C.

7. The manufacturing method of the high-power radio frequency device according to claim 1, characterized in that, The substrate includes the first region and the second region, and the positive projections of the fourth electrode, the fifth electrode, the input electrode, and the output electrode on the plane where the substrate is located are located in the second region.

8. The manufacturing method of the high-power radio frequency device according to claim 1, characterized in that The grounding electrode is electrically connected to the second electrode through the metal interconnection layer, the input electrode is electrically connected to the first electrode and the fourth electrode through the metal interconnection layer, and the output electrode is electrically connected to the third electrode and the fifth electrode through the metal interconnection layer.

9. The manufacturing method of the high-power radio frequency device according to claim 1, characterized in that, The high-power radio frequency semiconductor structure includes: a first dielectric layer covering the front surface of the substrate, the first electrode, the second electrode, and the third electrode; the first blind hole and the second blind hole are formed in the substrate and the first dielectric layer.

10. The manufacturing method of the high-power radio frequency device according to claim 9, characterized in that, The step of forming at least the fourth electrode in the first blind hole and at least the fifth electrode in the second blind hole includes: Forming a metal layer entirely on the side of the first dielectric layer away from the substrate and in the first blind hole and the second blind hole; Polishing the metal layer until the first dielectric layer is exposed, and the metal layer remaining in the first blind hole forms the fourth electrode, and the metal layer remaining in the second blind hole forms the fifth electrode.

11. The manufacturing method of the high-power radio frequency device according to claim 10, wherein, The metal layer fills the first blind hole and the second blind hole, or the metal layer is formed on the inner walls of the first blind hole and the second blind hole.

12. The manufacturing method of the high-power radio frequency device according to claim 2 or 3, characterized in that, Between the step of covering the third dielectric layer and the step of forming the ground pad, it further includes: covering a passivation layer on the third dielectric layer, and the thickness ratio range of the passivation layer to the third dielectric layer is 0.025 to 0.

3.

13. The manufacturing method of the high-power radio frequency device according to claim 1, characterized in that, It further includes: Providing a package case; Mounting the ground pad on the package case, and leading out the input pad and the output pad to the outside of the package case through metal leads.

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