Leakage protection circuit, integrated circuit, electronic device and method

Abstract

Embodiments of the present application provide a leakage protection circuit, an integrated circuit, an electronic device, and a method. The leakage protection circuit includes a leakage detection circuit, a compensation trigger circuit, and a leakage compensation circuit. The leakage detection circuit includes a detection capacitor and is configured to be connected to a circuit under test and charge the detection capacitor using the leakage current of the circuit under test. The compensation trigger circuit is connected to the leakage detection circuit and is configured to detect the magnitude of the leakage current during the charging of the detection capacitor and output a trigger signal when the leakage current is greater than or equal to a preset threshold. The leakage compensation circuit is connected to the compensation trigger circuit and is configured to provide a compensation current corresponding to the leakage current for the circuit under test according to the trigger signal. The leakage protection circuit provided in this embodiment can effectively eliminate the influence of system leakage and improve the detection range and accuracy of signals.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a leakage protection circuit, an integrated circuit, an electronic device, and a method. Background Art

[0002] The Internet of Things (IoT) is a highly integrated and comprehensive application of next-generation information technology. Its architecture is divided into the perception layer, the network layer, and the application layer. The perception layer of the IoT consists of sensors and gateways, which acquire information through sensors and receive control instructions through gateways.

[0003] Sensors, as the most fundamental component of the Internet of Things, can process various weak signals (such as pressure and gas signals) through processes such as acquisition, amplification, offset compensation, temperature compensation, and linearity compensation. However, during the processing of small signals, any leakage in the system can affect the quality of the processing, leading to signal distortion. Therefore, leakage protection is particularly important. Summary of the Invention

[0004] In view of the above problems, the embodiments of the present application provide a leakage protection circuit, an integrated circuit, an electronic device and a method to solve the above technical problems.

[0005] The embodiments of the present application are implemented using the following technical solutions:

[0006] A leakage protection circuit includes a leakage detection circuit, a compensation trigger circuit, and a leakage compensation circuit. The leakage detection circuit includes a detection capacitor and is used to connect to a circuit to be tested and use the leakage current of the circuit to be tested to charge the detection capacitor; the compensation trigger circuit is connected to the leakage detection circuit and is used to detect the magnitude of the leakage current during the charging period of the detection capacitor and output a trigger signal when the leakage current is greater than or equal to a preset threshold; the leakage compensation circuit is connected to the compensation trigger circuit and is used to provide a compensation current corresponding to the leakage current to the circuit to be tested according to the trigger signal.

[0007] In some embodiments, the compensation trigger circuit includes a comparison circuit, a clock control circuit, and a counter; the comparison circuit is connected to the leakage detection circuit and is preset with a reference voltage, and is used to output a comparison signal based on the voltage of the detection capacitor and the reference voltage; the clock control circuit is connected to the comparison circuit and the leakage detection circuit, and is used to output a clock signal based on the comparison signal, and control the leakage detection circuit to charge or discharge the detection capacitor through the clock signal; the counter is connected to the clock control circuit, and is used to detect the magnitude of the leakage current during the charging of the detection capacitor according to the clock signal, and output a trigger signal when the leakage current is greater than or equal to a preset threshold.

[0008] In some embodiments, the clock signal includes a first level signal and a second level signal, and the leakage current includes a first leakage current of the circuit under test leaking to the ground and a second leakage current between the circuit under test and the power supply; the clock control circuit is configured to output the first level signal according to the comparison signal and output the second level signal after a preset time delay, and the leakage detection circuit is configured to control the detection capacitor to discharge within the preset time according to the first level signal and charge the detection capacitor with the first leakage current according to the second level signal; or, the clock control circuit is configured to output the second level signal according to the comparison signal and output the first level signal after a preset time delay, and the leakage detection circuit is configured to control the detection capacitor to discharge within the preset time according to the second level signal and charge the detection capacitor with the second leakage current according to the first level signal.

[0009] In some embodiments, the counter is further configured to count according to a preset reference clock when the leakage detection circuit charges the detection capacitor with the first leakage current according to the second level signal, so as to detect the magnitude of the first leakage current; or, the counter is further configured to count according to a preset reference clock when the leakage detection circuit charges the detection capacitor with the second leakage current according to the first level signal, so as to detect the magnitude of the second leakage current.

[0010] In some embodiments, the clock control circuit includes a D flip-flop connected to a comparison circuit and an RS flip-flop connected to the D flip-flop.

[0011] In some embodiments, the leakage compensation circuit includes a compensation control circuit connected to a compensation trigger circuit and a current source unit connected to the compensation control circuit, and the compensation control circuit is configured to determine the magnitude of the leakage current according to the trigger signal and provide a compensation current corresponding to the magnitude of the leakage current for the circuit under test through the current source unit.

[0012] In some embodiments, the current source unit is a current source array, and the compensation control current is configured to select a current source corresponding to the magnitude of the leakage current in the current source array according to the magnitude of the leakage current to provide the compensation current.

[0013] In some embodiments, the leakage detection circuit includes a first leakage detection circuit and a second leakage detection circuit, and the detection capacitor includes a first detection capacitor and a second detection capacitor; the first leakage detection circuit is configured to connect to the circuit under test and charge the first detection capacitor with the first leakage current when the circuit under test leaks to the ground; the second leakage detection circuit is configured to connect to the circuit under test and charge the second detection capacitor with the second leakage current between the circuit under test and the power supply.

[0014] In some embodiments, the first leakage detection circuit includes a first switch, a second switch, and a first detection capacitor; one end of the first detection capacitor is connected to the power supply, and the other end is connected to the first switch; the second switch is connected in parallel across the two ends of the first detection capacitor; the connection node between the first detection capacitor and the first switch is connected to the compensation trigger circuit; the second leakage detection circuit includes a third switch, a fourth switch, and a second detection capacitor; one end of the second detection capacitor is grounded, and the other end is connected to the third switch, and the other end of the third switch is connected to the other end of the first switch; the fourth switch is connected in parallel across the two ends of the second detection capacitor; the connection node between the second detection capacitor and the third switch is connected to the compensation trigger circuit; the connection node between the first switch and the third switch is used to connect to the circuit under test; the first switch, the second switch, the third switch, and the fourth switch are controlled by a clock signal.

[0015] In some embodiments, the comparison circuit includes a first comparator and a second comparator, and the reference voltage includes a first reference voltage and a second reference voltage; the first input terminal of the first comparator is preset with the first reference voltage, the second input terminal is connected to the connection node between the first detection capacitor and the first switch, and the output terminal is connected to the clock control circuit; the first input terminal of the second comparator is connected to the connection node between the second detection capacitor and the third switch, the second input terminal is preset with the second reference voltage, and the output terminal is connected to the clock control circuit.

[0016] In some embodiments, the compensation trigger circuit further includes a gating circuit, the gating circuit is connected between the comparison circuit and the clock control circuit, and is used to selectively connect one of the first comparator and the second comparator to the clock control circuit.

[0017] In some embodiments, the current source unit includes a first current source unit and a second current source unit, the compensation control circuit is used to determine the magnitude of the leakage current when the circuit under test leaks to the ground according to the trigger signal, and provide a compensation current corresponding to the magnitude of the leakage current for the circuit under test through the first current source unit; the compensation control circuit is further used to determine the magnitude of the leakage current between the circuit under test and the power supply according to the trigger signal, and provide a compensation current corresponding to the leakage current for the circuit under test through the second current source unit.

[0018] The embodiment of the present application also provides an integrated circuit, including the leakage protection circuit according to any one of the above.

[0019] The embodiment of the present application also provides an electronic device, including a device main body and the integrated circuit as described above provided in the device main body.

[0020] The embodiments of the present application further provide a leakage protection method, which is applied to the leakage protection circuit of any one of the above. The method includes charging a detection capacitor with the leakage current of a circuit under test; detecting the magnitude of the leakage current during the charging of the detection capacitor, and outputting a trigger signal when the leakage current is greater than or equal to a preset threshold; and providing a compensation current corresponding to the leakage current for the circuit under test according to the trigger signal.

[0021] In the leakage protection circuit, integrated circuit, electronic device and method provided by the embodiments of the present application, the leakage protection circuit is provided with a leakage detection circuit, a compensation trigger circuit and a leakage compensation circuit. The leakage detection circuit includes a detection capacitor; the detection capacitor is charged with the leakage current of the circuit under test through the leakage detection circuit; then the magnitude of the leakage current is detected by the compensation trigger circuit during the charging of the detection capacitor, and a trigger signal is output when the leakage current is greater than or equal to a preset threshold; finally, the leakage compensation circuit provides a compensation current corresponding to the leakage current for the circuit under test according to the trigger signal, thereby effectively eliminating the influence of system leakage and improving the detection range and accuracy of signals.

[0022] These aspects or other aspects of the present application will be more clearly understood in the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 Shows a block diagram of a leakage protection circuit provided by an embodiment of the present application.

[0025] Figure 2 Shows another block diagram of a leakage protection circuit provided by an embodiment of the present application.

[0026] Figure 3 Shows yet another block diagram of a leakage protection circuit provided by an embodiment of the present application.

[0027] Figure 4 Shows a schematic circuit diagram of a leakage protection circuit provided by an embodiment of the present application.

[0028] Figure 5 Shows a schematic diagram of the structure of a reference voltage generation circuit provided by an embodiment of the present application.

[0029] Figure 6 Shows a circuit schematic diagram of negative leakage protection provided by an embodiment of the present application.

[0030] Figure 7 The circuit schematic diagram of the forward leakage protection provided by the embodiment of the present application is shown.

[0031] Figure 8 The schematic flow chart of the leakage protection method provided by the embodiment of the present application is shown. Specific embodiments

[0032] The following describes in detail the embodiments of the present application. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary only for explaining the present application and should not be construed as limiting the present application.

[0033] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0034] As Figure 1 shown, Figure 1 The block diagram of the leakage protection circuit 100 provided by the embodiment of the present application is schematically shown. The leakage protection circuit 100 can be connected to the circuit under test 10 and perform leakage protection on the circuit under test 10. In the field of measurement applications, the circuit under test 10 can be a sensor, and the sensor can be a pressure sensor, a temperature sensor, a humidity sensor, etc. Taking the pressure sensor as an example, the leakage protection circuit 100 can perform leakage protection on the pressure detection system composed of a Wheatstone bridge in the pressure sensor. Of course, the embodiment of the present application can also be applied to other fields, and the circuit under test 10 can also be any other circuit with a risk of leakage.

[0035] The leakage protection circuit 100 includes a leakage detection circuit 110, a compensation trigger circuit 120, and a leakage compensation circuit 130. Among them, the leakage detection circuit 110 includes a detection capacitor. The leakage detection circuit 110 is used to connect to the circuit under test 10 and charge the detection capacitor with the leakage current of the circuit under test 10; the compensation trigger circuit 120 is connected to the leakage detection circuit 110 and is used to detect the magnitude of the leakage current during the charging of the detection capacitor and output a trigger signal when the leakage current is greater than or equal to a preset threshold; the leakage compensation circuit 130 is connected to the compensation trigger circuit 120 and is used to provide a compensation current corresponding to the leakage current for the circuit under test 10 according to the trigger signal.

[0036] When the circuit 10 to be measured has a leakage, the detection capacitor is charged by the leakage current. During the charging time window of the detection capacitor, since the charging current of the detection capacitor is related to the leakage current, the magnitude of the leakage current can be detected. When the leakage current is greater than or equal to the preset threshold, it indicates that the leakage of the circuit 10 to be measured exceeds the given leakage threshold, which will affect the signal detection. At this time, a compensation current is provided to the circuit 10 to be measured. This compensation current is a current with a direction opposite to the leakage current, which can completely compensate for the leakage current, or partially compensate for the leakage current to reduce the leakage current within the given threshold, thereby eliminating the influence of the leakage current on the signal detection and improving the accuracy of signal detection.

[0037] The leakage protection circuit provided by the embodiment of the present application is provided with a leakage detection circuit, a compensation trigger circuit, and a leakage compensation circuit. The leakage detection circuit includes a detection capacitor; the detection capacitor is charged by the leakage current of the circuit to be measured through the leakage detection circuit; then, the magnitude of the leakage current is detected by the compensation trigger circuit during the charging of the detection capacitor, and a trigger signal is output when the leakage current is greater than or equal to the preset threshold; finally, the leakage compensation circuit provides a compensation current corresponding to the leakage current for the circuit to be measured according to the trigger signal, thereby effectively eliminating the influence of system leakage and improving the detection range and accuracy of the signal.

[0038] As Figure 2 shown, the embodiment of the present application further provides a leakage protection circuit 200. The leakage protection circuit 200 has the same leakage detection circuit 210, compensation trigger circuit 220, and leakage compensation circuit 230 as the above-mentioned leakage protection circuit 100. On this basis, the compensation trigger circuit 220 includes a comparison circuit 221, a clock control circuit 222, and a counter 223.

[0039] Among them, the comparison circuit 221 is connected to the leakage detection circuit 210, and a reference voltage is preset, and it is used to output a comparison signal according to the voltage of the detection capacitor and the reference voltage; the clock control circuit 222 is connected to the comparison circuit 221 and the leakage detection circuit 210, and is used to output a clock signal according to the comparison signal, and control the leakage detection circuit 210 to charge or discharge the detection capacitor through the clock signal; the counter 223 is connected to the clock control circuit 222, and is used to detect the magnitude of the leakage current during the charging of the detection capacitor according to the clock signal, and output a trigger signal when the leakage current is greater than or equal to the preset threshold.

[0040] In this embodiment, the leakage current includes at least one of a first leakage current of the circuit under test 10 leaking to the ground and a second leakage current between the circuit under test 10 and the power supply. The clock signal includes a first level signal and a second level signal. The clock control circuit 222 is further configured to output the first level signal according to the comparison signal and output the second level signal after a preset time delay. The leakage detection circuit 210 is configured to control the detection capacitor to discharge within the preset time according to the first level signal and charge the detection capacitor using the first leakage current according to the second level signal; or, the clock control circuit 222 is configured to output the second level signal according to the comparison signal and output the first level signal after a preset time delay. The leakage detection circuit 210 is configured to control the detection capacitor to discharge within the preset time according to the second level signal and charge the detection capacitor using the second leakage current according to the first level signal.

[0041] Specifically, the comparison circuit 221 and the clock control circuit 222 in this embodiment are connected to form an oscillation circuit, so that the clock control circuit 222 alternately outputs the first level signal and the second level signal at a certain frequency, thereby controlling the detection capacitor to alternately discharge and charge at a certain frequency. When the circuit under test 10 has a leakage and the leakage current is the first leakage current, within the time period when the clock control circuit 222 outputs the second level signal, the second level signal can control the leakage detection circuit 210 to charge the detection capacitor using the first leakage current. When the voltage across the detection capacitor is charged to a value that can cause a change in the output of the comparison circuit 221, the comparison circuit 221 outputs a comparison signal to the clock control circuit 222. After receiving this comparison signal, the clock control circuit 222 outputs the first level signal to the leakage detection circuit 210 to control the leakage detection circuit 210 to discharge the detection capacitor, that is, no longer charge the detection capacitor using the first leakage current. At the same time, the clock control circuit 222 starts to perform a time delay. The time delay period is also the discharge time of the detection capacitor. After a preset time delay, the clock control circuit 222 outputs the second level signal to the leakage detection circuit 210 again, so that the leakage detection circuit 210 performs a new round of detection on the first leakage current. In this embodiment, the clock control circuit 222 may include a D flip-flop and an RS flip-flop. Through the above process, continuous detection of the first leakage current of the circuit under test leaking to the ground can be achieved, and thus the leakage of the circuit under test 10 can be quickly responded to.

[0042] When the circuit 10 to be measured has a leakage, and the leakage current is the second leakage current, during the time period when the clock control circuit 222 outputs a first level signal, the first level signal can control the leakage detection circuit 210 to charge the detection capacitor with the second leakage current. When the voltage across the detection capacitor is charged to a level that can cause a change in the output of the comparison circuit 221, the comparison circuit 221 outputs a comparison signal to the clock control circuit 222. After receiving this comparison signal, the clock control circuit 222 outputs a second level signal to the leakage detection circuit 210 to control the leakage detection circuit 210 to discharge the detection capacitor, that is, to stop charging the detection capacitor with the second leakage current. At the same time, the clock control circuit 222 starts to perform a delay. The delay period is also the discharge time of the detection capacitor. After the preset delay time, the clock control circuit 222 outputs the first level signal to the leakage detection circuit 210 again, enabling the leakage detection circuit 210 to perform a new round of detection of the second leakage current. In this embodiment, the clock control circuit 222 may include a D flip-flop and an RS flip-flop. Through the above process, continuous detection of the second leakage current of the circuit to be measured leaking to the power supply can be achieved, and thus a rapid response to the leakage of the circuit 10 to be measured can be obtained.

[0043] Optionally, the detection of the first leakage current and the second leakage current can be alternately performed by a leakage detection circuit 210 and a comparison circuit 221 at different times; or the detection of the first leakage current and the second leakage current can be respectively performed by two leakage detection circuits 210 and two comparison circuits 221.

[0044] Further, the counter is further configured to count according to a preset reference clock when the leakage detection circuit charges the detection capacitor with the first leakage current according to the second level signal, so as to detect the magnitude of the first leakage current; or the counter is further configured to count according to a preset reference clock when the leakage detection circuit charges the detection capacitor with the second leakage current according to the first level signal, so as to detect the magnitude of the second leakage current.

[0045] During the charging of the detection capacitor, the counter 223 starts to work and count. In this embodiment, when the leakage current is the first leakage current, within the pulse width window of the second level signal, the counter 223 counts using the high-frequency reference clock to detect the magnitude of the first leakage current. Among them, the high-frequency reference clock is the input clock of the counter 223. The pulse width window of the second level signal is also the high-level time window of the second level signal. Within this high-level time window, the detection capacitor is charging. And within the charging time window of the detection capacitor, if the high-frequency count is less than or equal to the given count threshold, it indicates that the first leakage current is greater than or equal to the preset threshold, and the leakage of the circuit under test 10 to the ground exceeds the given range. At this time, the counter 223 outputs a trigger signal to the leakage compensation circuit 230 to trigger the leakage compensation circuit 230 to compensate for the first leakage current.

[0046] When the leakage current is the second leakage current, within the pulse width window of the first level signal, the counter 223 counts using the high-frequency reference clock to detect the magnitude of the second leakage current. Among them, the high-frequency reference clock is the input clock of the counter 223. The pulse width window of the first level signal is also the high-level time window of the first level signal. Within this high-level time window, the detection capacitor is charging. And within the charging time window of the detection capacitor, if the high-frequency count is less than or equal to the given count threshold, it indicates that the second leakage current is greater than or equal to the preset threshold, and the leakage of the circuit under test 10 to the power supply exceeds the given range. At this time, the counter 223 outputs a trigger signal to the leakage compensation circuit 230 to trigger the leakage compensation circuit 230 to compensate for the second leakage current.

[0047] It should be noted that the fewer the high-frequency counts of the counter 223, the less time it takes for the detection capacitor to charge to the reference voltage, and the greater the leakage current. Through the above process of the counter 223, the magnitudes of the first leakage current and the second leakage current can be accurately detected, and the leakage compensation can be triggered accordingly.

[0048] Further, the leakage compensation circuit 230 provided in this embodiment includes a compensation control circuit 231 connected to the compensation trigger circuit 220 and a current source unit 232 connected to the compensation control circuit 231. The current source unit 232 is also connected to the circuit under test 10. The compensation control circuit 231 is configured to determine the magnitude of the leakage current according to the trigger signal, and provide a compensation current corresponding to the magnitude of the leakage current to the circuit under test 10 through the current source unit 232. When the compensation control circuit 231 receives the trigger signal output by the counter 223, the compensation control circuit 231 can determine the magnitude of the leakage current, and then control the current source unit 232 to generate a reverse current opposite to the direction of the leakage current, and input the reverse current into the circuit under test 10 to offset the influence of the leakage current. In this embodiment, the magnitude of the reverse current can be equal to the magnitude of the leakage current, so as to completely offset the leakage current and eliminate the influence of the leakage current. In some embodiments, the magnitude of the reverse current can be greater than the difference between the leakage current and a preset threshold, so as to partially offset the leakage current and reduce the influence of the leakage current to within a given threshold.

[0049] In this embodiment, the current source unit 232 can be a current source array. The compensation control circuit 231 is configured to select a current source corresponding to the magnitude of the leakage current in the current source array according to the magnitude of the leakage current to provide a compensation current. Through the current source array, a current corresponding to the magnitude of the leakage current can be matched, and thus the leakage current can be dynamically compensated.

[0050] Further, when the circuit under test 10 has a negative leakage to the ground, that is, the first leakage current flows to the ground, and the first leakage current is a negative leakage current; when the circuit under test 10 has a positive leakage to the power supply, that is, the second leakage current leaks from the power supply, and the second leakage current is a positive leakage current. As Figure 3 shown in Figure 4 this embodiment, the leakage detection circuit 210 includes a first leakage detection circuit 211 and a second leakage detection circuit 212. The first leakage detection circuit 211 includes a first detection capacitor C1, and the second leakage detection circuit 212 includes a second detection capacitor C2. The first leakage detection circuit 211 is configured to connect to the circuit under test 10 and charge the first detection capacitor C1 with the leakage current when the circuit under test 10 has a leakage to the ground. That is, the first leakage detection circuit 211 is configured to detect the negative leakage current. The second leakage detection circuit 212 is configured to connect to the circuit under test 10 and charge the second detection capacitor C2 with the leakage current between the circuit under test 10 and the power supply. That is, the second leakage detection circuit 212 is configured to detect the positive leakage current. Through the detection of positive and negative bidirectional leakage by the leakage detection circuit 210, the leakage protection circuit 200 can compensate for positive and negative bidirectional leakage, and thus eliminate the influence of positive and negative bidirectional leakage on signal detection.

[0051] Specifically, if Figure 3 and Figure 4 As shown, the first leakage detection circuit 211 includes a first switch S1, a second switch S2 and a first detection capacitor C1; one end of the first detection capacitor C1 is connected to the power supply VDD and the other end is connected to the first switch S1; the second switch S2 is connected in parallel to both ends of the first detection capacitor C1; the connection node between the first detection capacitor C1 and the first switch S1 is connected to the compensation trigger circuit; the second leakage detection circuit 212 includes a third switch S3, a fourth switch S4 and a second detection capacitor C2; one end of the second detection capacitor C2 is grounded and the other end is connected to one end of the third switch S3, and the other end of the third switch S3 is connected to the other end of the first switch S1; the fourth switch S4 is connected in parallel to both ends of the second detection capacitor C2; the connection node between the second detection capacitor C2 and the third switch S3 is connected to the compensation trigger circuit; the connection node between the first switch S1 and the third switch S3 is used to connect to the circuit to be tested 10; the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are controlled by a clock signal.

[0052] The comparison circuit 221 includes a first comparator CMP1 and a second comparator CMP2. The reference voltage includes a first reference voltage Vpos and a second reference voltage Vneg, and the first reference voltage Vpos and the second reference voltage Vneg are equal in magnitude. The first comparator CMP1 has a first input terminal for receiving the first reference voltage Vpos, a second input terminal connected to the connection node between the first detection capacitor C1 and the first switch S1, and an output terminal connected to the clock control circuit 222. The second comparator CMP2 has a first input terminal connected to the connection node between the second detection capacitor C2 and the third switch S3, a second input terminal for receiving the second reference voltage Vneg, and an output terminal connected to the clock control circuit 222. In this embodiment, the first input terminal of the first comparator CMP1 is a non-inverting input terminal, and the second input terminal is an inverting input terminal; the first input terminal of the second comparator CMP2 is a non-inverting input terminal, and the second input terminal is an inverting input terminal.

[0053] The first reference voltage Vpos and the second reference voltage Vneg can be generated by an external reference voltage generating circuit. Figure 5As shown, the reference voltage generation circuit may include a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. Among them, taking the first MOS transistor Q1 and the third MOS transistor Q3 as N-MOS transistors, and the second MOS transistor Q2 and the fourth MOS transistor Q4 as P-MOS transistors as an example, the drain of the first MOS transistor Q1 is connected to the power supply VDD through the first resistor R1, the source is connected to the source of the second MOS transistor Q2, and the gate is connected to the gate of the third MOS transistor Q3; the drain of the first MOS transistor Q1 is connected to the gate; the drain of the second MOS transistor Q2 is grounded through the second resistor R2, and the gate is connected to the gate of the fourth MOS transistor Q4; the drain of the second MOS transistor Q2 is connected to the gate; the drain of the third MOS transistor Q3 is connected to the power supply VDD through the third resistor R3, and the source is connected to the source of the fourth MOS transistor Q4; the drain of the fourth MOS transistor Q4 is grounded through the fourth resistor R4. The connection node between the third MOS transistor Q3 and the third resistor R3 is connected to the first input terminal of the first comparator CMP1 to provide a first reference voltage Vpos to the first comparator CMP1; the connection node between the fourth MOS transistor Q4 and the fourth resistor R4 is connected to the second input terminal of the second comparator CMP2 to provide a second reference voltage Vneg to the second comparator CMP2. Among them, the current Ithreshold is the threshold current, the first reference voltage Vpos is (VDD - Ithreshold * R), the second reference voltage Vneg is (Ithreshold * R), and the resistance values of the first resistor R1 to the fourth resistor R4 are all R.

[0054] As Figure 4As shown, in this embodiment, the leakage protection circuit further includes a gating circuit 240. The gating circuit 240 is connected between the comparison circuit 221 and the clock control circuit 222, and is used to select one of the first comparator CMP1 and the second comparator CMP2 to be connected to the clock control circuit 222. The gating circuit 240 includes switches Smux1, Smux2, Smux3, Smux4, Smux5, and Smux6. The clock control circuit 222 includes a D flip-flop and an RS flip-flop. A series connection of switches Smux1 and Smux2 is connected between the output terminals of the first comparator CMP1 and the second comparator CMP2. The input terminal D of the D flip-flop is connected to the connection node of switches Smux1 and Smux2. The output terminal Q0 of the D flip-flop and a preset RST signal are connected to the reset terminal R0 of the D flip-flop through an OR gate, and the RST signal is the initial reset signal of the circuit. A series connection of switches Smux3 and Smux4 is connected between the output terminal of the first comparator CMP1 and the output terminal Q0 of the D flip-flop; a series connection of switches Smux5 and Smux6 is connected between the output terminal of the second comparator CMP2 and the output terminal Q0 of the D flip-flop. The set terminal S of the RS flip-flop is connected to the connection node of switches Smux3 and Smux4; the reset terminal R1 of the RS flip-flop is connected to the connection node of switches Smux5 and Smux6.

[0055] As Figure 3 with Figure 4 shown, the counter 223 includes a first counter and a second counter. The RS flip-flop includes a first output terminal Q1 and a second output terminal QB, where the first output terminal Q1 and the second output terminal QB are two complementary output terminals, that is, when the first output terminal Q1 outputs a high level, the second output terminal QB outputs a low level; when the first output terminal Q1 outputs a low level, the second output terminal QB outputs a high level. The enable terminal EN1 of the first counter is connected to the first output terminal Q of the RS flip-flop, and the enable terminal EN2 of the second counter is connected to the second output terminal QB of the RS flip-flop. The clock input terminals CLK1 of the first counter and CLK2 of the second counter are both connected to a high-frequency reference clock, and the output terminals of the first counter and the second counter are both connected to the leakage compensation circuit 230.

[0056] The leakage current compensation circuit 230 includes a compensation control circuit 231 and a current source unit 232. The compensation control circuit 231 is an Auto-Current Compensation circuit, and the current source unit 232 is a current source array. The input terminal of the compensation control circuit 231 is connected to the output terminals of the first counter and the second counter, and the output terminal of the compensation control circuit 231 is connected to the current source array. The current source array includes a positive current source array and a negative current source array connected to the positive current source array. One end of each positive current source in the positive current source array is connected to the circuit under test 10, and the other end is connected to the power supply VDD through a switch; one end of each positive current source in the negative current source array is connected to the circuit under test 10, and the other end is grounded through a switch.

[0057] The following will describe Figures 6 to 7 the principle of the leakage protection circuit provided in this embodiment.

[0058] The switches Smux1, Smux2, Smux3, Smux4, Smux5, and Smux6 can be controlled by an external timing signal. By controlling the timing of the above switches, it is possible to switch between positive leakage protection and negative leakage protection.

[0059] As Figure 6As shown, when switch Smux1, switch Smux3, and switch Smux5 are closed and switch Smux2, switch Smux4, and switch Smux6 are open, the leakage detection system performs negative leakage protection, and the current Ileakage is the negative leakage current flowing from the circuit under test 10 to the ground. At this time, the output terminal of the first comparator CMP1 is connected to the input terminal D of the D flip-flop and the set terminal S of the RS flip-flop. The reset terminal R0 of the D flip-flop is connected to the output terminal Q0 of the D flip-flop, and the reset terminal R1 of the RS flip-flop is connected between the output terminal Q0 of the D flip-flop and the reset terminal R0 of the D flip-flop. The clock input terminal CLK0 of the D flip-flop is connected to the high-frequency reference clock. The first output terminal Q1 of the RS flip-flop outputs the first clock signal CK1 to the leakage detection circuit 210 to control the on / off of the second switch S2 and the third switch S3; the second output terminal QB of the RS flip-flop outputs the second clock signal CK2 to the leakage detection circuit 210 to control the on / off of the first switch S1 and the fourth switch S4. And the first output terminal Q1 of the RS flip-flop outputs the first clock signal CK1 to the first counter; the second output terminal QB of the RS flip-flop outputs the second clock signal CK2 to the second counter. In this embodiment, the first level signal is the first clock signal CK1 = 1 and the second clock signal CK2 = 0, that is, the first clock signal is a high-level signal and the second clock signal is a low-level signal; the second level signal is the first clock signal CK1 = 0 and the second clock signal CK2 = 1, that is, the first clock signal is a low-level signal and the second clock signal is a high-level signal. It should be noted that the first clock signal and the second clock signal are a set of non-overlapping clock signals.

[0060] When the RS flip-flop outputs a second-level signal, that is, when the first clock signal CK1 = 0 and the second clock signal CK2 = 1, the first switch S1 and the fourth switch S4 are respectively controlled by the second clock signal CK2 to conduct, and the second switch S2 and the third switch S3 are respectively controlled by the first clock signal CK1 to disconnect. At this time, the leakage of the power supply VDD and the conducting first switch S1 provide a charging path for the detection capacitor C1, and the detection capacitor C1 starts to charge, and the charging current is the leakage current Ileakage. During the charging process of the detection capacitor C1, the node voltage Va starts to decrease from the power supply voltage. The node voltage Va is the input voltage of the inverting input terminal of the first comparator CMP1. When the detection capacitor C1 is charged until the node voltage Va is less than the first reference voltage Vpos, the first comparator CMP1 outputs a high-level signal. When the output of the first comparator CMP1 changes from a low-level signal to a high-level signal, this high-level signal is input to the set terminal S of the RS flip-flop, so that the first clock signal CK1 output by the first output terminal Q1 of the RS flip-flop flips from 0 to 1, and the second clock signal CK2 output by the second output terminal QB of the RS flip-flop flips from 1 to 0. At the same time, when the output of the first comparator CMP1 changes from a low-level signal to a high-level signal, after the high-frequency reference clock of the D flip-flop triggers an edge, the output terminal Q0 of the D flip-flop outputs a high-level signal. The high-level signal output by the D flip-flop and the RST signal are ORed and then immediately reset the D flip-flop, so that the output terminal Q0 of the D flip-flop is converted to a low-level signal.

[0061] At this time, the RS flip-flop outputs a first-level signal, that is, the first clock signal CK1 = 1 and the second clock signal CK2 = 0, so that the first switch S1 disconnects, the second switch S2 conducts, the third switch S3 conducts, and the fourth switch S4 disconnects. The detection capacitor C1 starts to discharge through the conducting second switch S2, causing the node voltage Va to gradually rise to the power supply voltage. At the same time, the D flip-flop starts to delay. After delaying for a preset time Tdelay, the D flip-flop outputs a high pulse signal to the reset terminal R1 of the RS flip-flop, causing the RS flip-flop to reset, and then causing the first clock signal to flip to CK1 = 0 and the second clock signal to flip to CK2 = 1, and the detection capacitor starts a new round of charging. During this process, the discharge time of the detection capacitor C1 is the preset time Tdelay, and the charging time is (Ithreshold * R * C1 / Ileakage). The low-frequency oscillation period T is (Tdelay + Ithreshold * R * C1 / Ileakage).

[0062] During the charging process of the detection capacitor C1, since the first clock signal CK1 = 0 and the second clock signal CK2 = 1, the enable terminal EN2 of the second counter becomes high level and the second counter starts to work. The input clock of the second counter is the high-frequency reference clock. During the charging time window of the detection capacitor C1 (Ithreshold * R * C1 / Ileakage), since the charging current of the detection capacitor C1 is the leakage current Ileakage, the high-frequency counting result of the second counter can directly reflect the magnitude of the leakage current Ileakage. Further, if the high-frequency count is less than the given count threshold Nthreshold, that is, Ithreshold * R * C1 / Ileakage

[0063] *Fclk < Nthreshold, it can be deduced that Ileakage > Ithreshold * R * C1 / (Fclk * Nthreshold), that is, the leakage current Ileakage exceeds the preset leakage threshold, Ithreshold * R * C1 /

[0064] (Fclk * Nthreshold), which is the preset leakage threshold.

[0065] When the leakage current Ileakage exceeds the preset leakage threshold, the compensation control circuit 231 controls the switches in the positive current source array to select a positive current corresponding to the magnitude of the leakage current Ileakage and input it to the circuit under test 10, thereby performing dynamic compensation on the circuit under test 10. Optionally, the output currents of each current source in the positive current source array can be the same or different. The compensation control circuit 231 can choose to connect the current source with appropriate output current to the circuit under test to compensate for the leakage current Ileakage, or can choose to connect multiple current sources to the circuit under test 10 at the same time to superimpose sufficient output current to compensate for the leakage current Ileakage. In other words, compensation can be performed by switching the connected current sources, or by controlling the number of connected current sources.

[0066] Such as Figure 7As shown, when switch Smux2, switch Smux4, and switch Smux6 are closed and switch Smux1, switch Smux3, and switch Smux5 are open, the leakage detection system performs forward leakage protection, and the current Ileakage is the forward leakage current flowing from power supply VDD to the circuit under test 10. At this time, the output terminal of the second comparator CMP2 is connected to the input terminal D of the D flip-flop and the reset terminal R1 of the RS flip-flop. The reset terminal R0 of the D flip-flop is connected to the output terminal Q0 of the D flip-flop, and the reset terminal R1 of the RS flip-flop is connected between the output terminal Q0 of the D flip-flop and the reset terminal R0 of the D flip-flop. The clock input terminal CLK0 of the D flip-flop is connected to the high-frequency reference clock. The first output terminal Q1 of the RS flip-flop outputs the first clock signal CK1 to the leakage detection circuit 210 to control the on / off of the second switch S2 and the third switch S3; the second output terminal QB of the RS flip-flop outputs the second clock signal CK2 to the leakage detection circuit 210 to control the on / off of the first switch S1 and the fourth switch S4. And the first output terminal Q1 of the RS flip-flop outputs the first clock signal CK1 to the first counter; the second output terminal QB of the RS flip-flop outputs the second clock signal CK2 to the second counter. In this embodiment, the first level signal is that the first clock signal CK1 = 1 and the second clock signal CK2 = 0, that is, the first clock signal is a high-level signal and the second clock signal is a low-level signal; the second level signal is that the first clock signal CK1 = 0 and the second clock signal CK2 = 1, that is, the first clock signal is a low-level signal and the second clock signal is a high-level signal. It should be noted that the first clock signal and the second clock signal are a set of non-overlapping clock signals.

[0067] When the RS flip-flop outputs a first level signal, that is, when the first clock signal CK1 = 1 and the second clock signal CK2 = 0, the first switch S1 and the fourth switch S4 are respectively controlled by the second clock signal CK2 and turned off, and the second switch S2 and the third switch S3 are respectively controlled by the first clock signal CK1 and turned on. At this time, the power supply VDD and the turned-on third switch S3 provide a charging circuit for the detection capacitor C2, and the detection capacitor C2 starts to charge, and the charging current is the leakage current Ileakage. During the charging process of the detection capacitor C2, the node voltage Vb increases from zero. The node voltage Vb is the input voltage of the non-inverting input terminal of the second comparator. When the detection capacitor C2 is charged to the node voltage Va greater than the second reference voltage Vneg, the second comparator CMP2 outputs a high level signal. When the output of the second comparator CMP2 changes from a low level signal to a high level signal, after the high-frequency reference clock edge of the D flip-flop is triggered, the output terminal Q0 of the D flip-flop outputs a high level signal to the set terminal S of the RS flip-flop, so that the first clock signal CK1 = 0 output by the first output terminal Q1 of the RS flip-flop, and the second clock signal CK2 = 1 output by the second output terminal QB of the RS flip-flop. When the output terminal Q0 of the D flip-flop becomes high, the high level signal output by the D flip-flop is ORed with the RST signal and then immediately resets the D flip-flop, so that the output terminal Q0 of the D flip-flop is converted to a low level signal.

[0068] At this time, the RS flip-flop outputs a second level signal, that is, when the first clock signal CK1 = 0 and the second clock signal CK2 = 1, the first switch S1 is turned on, the second switch S2 is turned off, the third switch S3 is turned off, and the fourth switch S4 is turned on. The detection capacitor C2 starts to discharge through the turned-on fourth switch S3, and the node voltage VB gradually drops to zero. At the same time, the D flip-flop starts to delay. After delaying for a preset time Tdelay, the D flip-flop outputs a high pulse signal to the set terminal S of the RS flip-flop, thereby making the first clock signal CK1 = 1 and the second clock signal CK2 = 0, and the detection capacitor C2 starts a new round of charging. During this process, the discharge time of the detection capacitor C2 is also the preset time Tdelay, the charging time is (Ithreshold * R * C2 / Ileakage), and the low-frequency oscillation period T is (Tdelay + Ithreshold * R * C1 / Ileakage).

[0069] During the charging process of the detection capacitor C2, since the first clock signal CK1 = 1 and the second clock signal CK2 = 0, the enable terminal EN1 of the first counter becomes high level and the first counter starts to work. The input clock of the first counter is the high-frequency reference clock. Within the charging time window (Ithreshold * R * C2 / Ileakage) of the detection capacitor C2, since the charging current of the detection capacitor C2 is the leakage current Ileakage, the high-frequency counting result of the first counter can directly reflect the magnitude of the leakage current Ileakage. Further, if the high-frequency count is less than the given count threshold Nthreshold, that is, Ithreshold * R * C2 / Ileakage

[0070] *Fclk < Nthreshold, it can be deduced that Ileakage > Ithreshold * R * C2 / (Fclk * Nthreshold), that is, the leakage current Ileakage exceeds the preset leakage threshold, Ithreshold * R * C1 /

[0071] (Fclk * Nthreshold), which is the preset leakage threshold.

[0072] When the leakage current Ileakage exceeds the preset leakage threshold, the compensation control circuit 231 controls the switches in the negative current source array at this time, selects a negative current corresponding to the magnitude of the leakage current Ileakage and inputs it to the circuit under test 10, and then performs dynamic compensation on the circuit under test 10. Optionally, the output currents of each current source in the negative current source array can be the same or different. The compensation control circuit 231 can choose to connect the current source with appropriate output current to the circuit under test to compensate for the leakage current Ileakage, or can also choose to connect multiple current sources to the circuit under test 10 at the same time to superimpose sufficient output current to compensate for the leakage current Ileakage. In other words, compensation can be performed by switching the connected current sources, or by controlling the number of connected current sources.

[0073] In some embodiments, a smaller leakage threshold can be set for identifying leakage. For example, when the high-frequency count of the counter 223 is less than a count threshold larger than the count threshold Nthreshold, it indicates that the circuit under test 10 has a leakage; when the high-frequency count of the counter 223 is less than the count threshold Nthreshold, it indicates that the leakage of the circuit under test 10 exceeds the preset leakage threshold.

[0074] Such as Figures 3 - 4 、 Figures 6 - 7As shown, the first branch formed by the first leakage detection circuit 211 and the first comparator CMP1 and the second branch formed by the second leakage detection circuit 212 and the second comparator CMP2 are symmetrical to each other, and the working clock levels are opposite. Therefore, in the leakage protection circuit of this embodiment, both the first branch and the second branch can be set at the same time, and the forward leakage detection and the negative leakage detection are respectively performed through two different branches; or only the first branch or the second branch can be set, and under the action of the clock signal, the forward leakage detection and the negative leakage detection are alternately performed through a single branch in a time-sharing manner.

[0075] The leakage protection circuit provided in this embodiment can achieve different types of leakage detection through the first detection capacitor or the second detection capacitor (i.e., a single detection capacitor). When there are positive and negative leaks in the circuit under test 10, a closed-loop feedback is formed through the charge and discharge of the detection capacitor, the comparator, the D flip-flop, and the RS flip-flop, etc., to form a low-frequency oscillator. The oscillation period T of this low-frequency oscillator is (Tdelay + Ithreshold * R * C1 / Ileakage). By adjusting the preset time Tdelay, a low-frequency clock signal with a high low-level duty cycle can be formed. The low-level time window of this low-frequency clock signal represents the charging time window of the detection capacitor, and the high-level time window represents the discharging time window of the detection capacitor. Then, through the counter 223, the high-frequency reference clock is accumulated and counted within the low-level time window of the low-frequency oscillator. When the positive and negative leaks exceed a certain range, the system outputs relevant identification bits (NegSideLeak, PosSideLeak) for leakage identification. At the same time, when the positive and negative leaks exceed the given range, the leakage compensation circuit 230 can be activated to cancel the reverse current, thereby effectively eliminating the influence of the leakage current and improving the detection range and accuracy of the signal.

[0076] The embodiment of the present application also provides an integrated circuit, which includes the above-mentioned leakage protection circuit 100 or leakage protection circuit 200. In this embodiment, the integrated circuit can be a leakage protection chip.

[0077] The integrated circuit provided in this embodiment is provided with a leakage detection circuit, a compensation trigger circuit, and a leakage compensation circuit. The leakage detection circuit includes a detection capacitor; the leakage current of the circuit under test is used to charge the detection capacitor through the leakage detection circuit; then, the magnitude of the leakage current is detected during the charging of the detection capacitor through the compensation trigger circuit, and a trigger signal is output when the leakage current is greater than or equal to the preset threshold; finally, the leakage compensation circuit provides a compensation current corresponding to the leakage current for the circuit under test according to the trigger signal, thereby effectively eliminating the influence of system leakage and improving the detection range and accuracy of the signal.

[0078] The embodiment of the present application further provides an electronic device, which includes a main body of the electronic device and the integrated circuit as described above disposed in the device main body. In this embodiment, the electronic device includes at least one sensor among, but not limited to, a temperature sensor, a pressure sensor, an infrared sensor, an ultrasonic sensor, a humidity sensor, a light sensor, and a gravity sensor.

[0079] The electronic device provided in this embodiment is provided with a leakage detection circuit, a compensation trigger circuit, and a leakage compensation circuit. The leakage detection circuit includes a detection capacitor; the leakage detection circuit charges the detection capacitor by using the leakage current of the circuit to be measured; then, the compensation trigger circuit detects the magnitude of the leakage current during the charging of the detection capacitor and outputs a trigger signal when the leakage current is greater than or equal to a preset threshold; finally, the leakage compensation circuit provides a compensation current corresponding to the leakage current for the circuit to be measured according to the trigger signal, thereby effectively eliminating the influence of system leakage and improving the detection range and accuracy of signals.

[0080] As Figure 8 shown, the embodiment of the present application further provides a leakage protection method 300, which is applied to the above-mentioned leakage protection circuit 100 or leakage protection circuit 200. The leakage protection method 300 includes the following steps S1 to S3.

[0081] S1: Charge the detection capacitor by using the leakage current of the circuit to be measured.

[0082] When the circuit to be measured leaks, charge the detection capacitor by using the leakage current of the circuit to be measured. At this time, the charging current of the detection capacitor is also the leakage current of the circuit to be measured.

[0083] During the charging process of the detection capacitor, change the charge and discharge state of the detection capacitor according to the voltage across the detection capacitor and the reference voltage. Specifically, when the voltage across the detection capacitor rises to the reference voltage or drops to the reference voltage, change the detection capacitor to the discharge state. After the detection capacitor changes to the discharge state, delay for a preset time to change the detection capacitor from the discharge state back to the charging state.

[0084] In one embodiment, the voltage of the detection capacitor can be input to a comparator. When the output state of the comparator changes (that is, the output signal of the comparator changes from a high-level signal to a low-level signal or from a low-level signal to a high-level signal), a comparison signal is generated to an oscillation circuit composed of a D flip-flop and an RS flip-flop, so that the oscillation circuit outputs a first clock signal to the control switch of the detection capacitor, thereby changing the detection capacitor from the charging state to the discharge state. After the detection capacitor changes to the discharge state, the oscillation circuit delays for a preset time and outputs a second clock signal to the control switch of the detection capacitor, thereby changing the detection capacitor from the discharge state back to the charging state.

[0085] Furthermore, the leakage current includes a first leakage current of the circuit under test to the ground and a second leakage current between the circuit under test and the power supply. The oscillation circuit alternately outputs a first clock signal and a second clock signal at a certain frequency, so as to control the detection capacitor to alternately discharge and charge at a certain frequency. When the leakage current is the first leakage current, during the period when the oscillation circuit outputs the second clock signal, the first leakage current can be used to charge the detection capacitor. When the voltage across the detection capacitor is charged to a value that can change the output of the comparator, the comparator outputs a comparison signal to the oscillation circuit. After receiving this comparison signal, the oscillation circuit outputs the first clock signal to the control switch of the detection capacitor to control the detection capacitor to discharge, that is, no longer use the first leakage current to charge the detection capacitor. At the same time, the oscillation circuit starts to perform a delay. The delay period is also the discharge time of the detection capacitor. After the preset delay time, the oscillation circuit outputs the second clock signal to the control switch of the detection capacitor again, and then performs a new round of detection of the first leakage current.

[0086] When the leakage current is the second leakage current, during the period when the oscillation circuit outputs the first clock signal, the second leakage current can be used to charge the detection capacitor. When the voltage across the detection capacitor is charged to a value that can change the output of the comparator, the comparator outputs a comparison signal to the oscillation circuit. After receiving this comparison signal, the oscillation circuit outputs the second clock signal to the control switch of the detection capacitor to control the detection capacitor to discharge, that is, no longer use the second leakage current to charge the detection capacitor. At the same time, the oscillation circuit starts to perform a delay. The delay period is also the discharge time of the detection capacitor. After the preset delay time, the oscillation circuit outputs the first clock signal to the control switch of the detection capacitor again, and then performs a new round of detection of the second leakage current.

[0087] S2: Detect the magnitude of the leakage current during the charging of the detection capacitor, and output a trigger signal when the leakage current is greater than or equal to a preset threshold.

[0088] Since the leakage current is the charging current of the detection capacitor, the magnitude of the leakage current can be detected within the charging time window of the detection capacitor. When the leakage current is greater than or equal to the preset threshold, it indicates that the leakage of the circuit under test has reached the given leakage threshold, and at this time, a trigger signal is output.

[0089] In one embodiment, when it is detected that the capacitance changes from the discharge state to the charging state, an oscillation circuit composed of a D flip-flop and an RS flip-flop outputs a clock pulse to the enable terminal of the counter. Then, the counter counts the high-frequency reference clock within the charging time window of the detection capacitance, and the count value of the counter can reflect the magnitude of the leakage current. It is worth noting that the smaller the count value of the counter, the shorter the charging time of the detection capacitance, and the larger the leakage current. When the count value of the counter is less than the counting threshold, it indicates that the leakage current of the circuit under test has reached the given leakage threshold. At this time, the counting signal of the counter is equivalent to a trigger signal.

[0090] Further, when the leakage current is the first leakage current, within the pulse width window of the second clock signal, the counter counts using the high-frequency reference clock to detect the magnitude of the first leakage current. Herein, the high-frequency reference clock is the input clock of the counter. The pulse width window of the second clock signal is also the high-level time window of the second clock signal. Within this high-level time window, the detection capacitance is charging. And within the charging time window of the detection capacitance, if the high-frequency count is less than or equal to the given counting threshold, it indicates that the first leakage current is greater than or equal to the preset threshold, and the leakage of the circuit under test to the ground exceeds the given range. At this time, the counter outputs a trigger signal to trigger the compensation for the first leakage current.

[0091] When the leakage current is the second leakage current, within the pulse width window of the first clock signal, the counter counts using the high-frequency reference clock to detect the magnitude of the second leakage current. Herein, the high-frequency reference clock is the input clock of the counter. The pulse width window of the first clock signal is also the high-level time window of the first clock signal. Within this high-level time window, the detection capacitance is charging. And within the charging time window of the detection capacitance, if the high-frequency count is less than or equal to the given counting threshold, it indicates that the second leakage current is greater than or equal to the preset threshold, and the leakage of the circuit under test to the power supply exceeds the given range. At this time, the counter outputs a trigger signal to trigger the compensation for the second leakage current.

[0092] S3: Provide a compensation current corresponding to the leakage current for the circuit under test according to the trigger signal.

[0093] According to this trigger signal, a compensation current corresponding to the leakage current can be provided for the circuit under test. The compensation current is a reverse current opposite to the direction of the leakage current. It can completely compensate for the leakage current or partially compensate for the leakage current to reduce the leakage current to within the given threshold, thereby eliminating the influence of the leakage current on signal detection and improving the accuracy of signal detection.

[0094] In one embodiment, an automatic current compensation control circuit can control a current source to generate a reverse current corresponding to the leakage current, and input the reverse current into the circuit under test to provide current compensation for the circuit under test. The automatic current compensation control circuit can select to connect a current source with appropriate output current to the circuit under test to compensate for the leakage current, or can also select to connect multiple current sources to the circuit under test simultaneously to superimpose sufficient output current to compensate for the leakage current. In other words, compensation can be achieved by switching the connected current sources, or by controlling the number of connected current sources.

[0095] The leakage protection method provided by the embodiments of the present application charges a detection capacitor using the leakage current of the circuit under test; then detects the magnitude of the leakage current during the charging of the detection capacitor, and outputs a trigger signal when the leakage current is greater than or equal to a preset threshold; finally, provides a compensation current corresponding to the leakage current for the circuit under test according to the trigger signal, thereby effectively eliminating the influence of system leakage and improving the detection range and accuracy of signals.

[0096] The above are only the preferred embodiments of the present application, and do not impose any form of limitation on the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to form equivalent embodiments with equivalent changes, but as long as the technical content of the present application is not departed from, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A leakage protection circuit, characterized in that, Comprising: A leakage detection circuit including a detection capacitor. The leakage detection circuit is used to connect to a circuit under test and charge the detection capacitor using the leakage current of the circuit under test. The leakage current includes a first leakage current that leaks to the ground, and the first leakage current is a negative leakage current. A compensation trigger circuit connected to the leakage detection circuit, configured to detect the magnitude of the leakage current during the charging of the detection capacitor and output a trigger signal when the leakage current is greater than or equal to a preset threshold. And A leakage compensation circuit connected to the compensation trigger circuit, configured to provide a compensation current corresponding to the leakage current for the circuit under test according to the trigger signal. The compensation current includes a positive current for fully or partially compensating the first leakage current.

2. The leakage protection circuit according to claim 1, characterized in that, The compensation trigger circuit includes: A comparison circuit connected to the leakage detection circuit. The comparison circuit has a preset reference voltage and is configured to output a comparison signal according to the voltage of the detection capacitor and the reference voltage. A clock control circuit connected to the comparison circuit and the leakage detection circuit, configured to output a clock signal according to the comparison signal and control the leakage detection circuit to charge or discharge the detection capacitor through the clock signal; and A counter connected to the clock control circuit, configured to detect the magnitude of the leakage current during the charging of the detection capacitor according to the clock signal and output a trigger signal when the leakage current is greater than or equal to the preset threshold.

3. The leakage protection circuit according to claim 2, characterized in that, The clock signal includes a first level signal and a second level signal; the clock control circuit is configured to output the first level signal according to the comparison signal and output the second level signal after a preset time delay. The leakage detection circuit is configured to control the detection capacitor to discharge within the preset time according to the first level signal and charge the detection capacitor using the first leakage current according to the second level signal.

4. The leakage protection circuit according to claim 3, characterized in that, The counter is further configured to count according to a preset reference clock when the leakage detection circuit charges the detection capacitor using the first leakage current according to the second level signal to detect the magnitude of the first leakage current.

5. The leakage protection circuit according to claim 3, characterized in that, The clock control circuit includes a D flip-flop connected to the comparison circuit and an RS flip-flop connected to the D flip-flop.

6. The leakage protection circuit according to claim 3, wherein, The leakage compensation circuit includes a compensation control circuit connected to the compensation trigger circuit and a current source unit connected to the compensation control circuit. The compensation control circuit is configured to determine the magnitude of the leakage current according to the trigger signal and provide a compensation current corresponding to the magnitude of the leakage current for the circuit under test through the current source unit.

7. The leakage protection circuit according to claim 6, characterized in that The current source unit is a current source array, and the compensation control circuit is configured to select a current source corresponding to the magnitude of the leakage current in the current source array to provide the compensation current according to the magnitude of the leakage current.

8. The leakage protection circuit according to claim 6, characterized in that The leakage detection circuit includes a first leakage detection circuit, and the detection capacitor includes a first detection capacitor. The first leakage detection circuit is used to connect to the circuit under test and charge the first detection capacitor with the first leakage current when the circuit under test has a ground leakage.

9. The leakage protection circuit according to claim 8, wherein The first leakage detection circuit includes a first switch, a second switch, and the first detection capacitor; one end of the first detection capacitor is connected to the power supply, and the other end is connected to one end of the first switch; the second switch is connected in parallel across the first detection capacitor; the connection node of the first detection capacitor and the first switch is connected to the compensation trigger circuit; The other end of the first switch is used to connect to the circuit under test; The first switch and the second switch are controlled by the clock signal.

10. The leakage protection circuit according to claim 9, characterized in that, The comparison circuit includes a first comparator, and the reference voltage includes a first reference voltage and a second reference voltage; A first reference voltage is preset at a first input terminal of the first comparator, a second input terminal is connected to the connection node of the first detection capacitor and the first switch, and an output terminal is connected to the clock control circuit.

11. The leakage protection circuit according to claim 10, characterized in that, The compensation trigger circuit further includes a gating circuit, the gating circuit is connected between the comparison circuit and the clock control circuit, and is used to selectively connect the first comparator to the clock control circuit.

12. The leakage protection circuit according to claim 10, characterized in that, The current source unit includes a first current source unit, and the compensation control circuit is used to determine the magnitude of the leakage current when the circuit under test has a ground leakage according to the trigger signal, and provide a compensation current corresponding to the magnitude of the leakage current for the circuit under test through the first current source unit.

13. An integrated circuit, characterized in that, Including the leakage protection circuit according to any one of the above claims 1 to 12.

14. An electronic device, characterized in that, Including a device body and an integrated circuit as described in claim 13 above provided in the device body.

15. A leakage protection method is applied to the leakage protection circuit described in any one of claims 1 to 12 above, characterized in that, Including: Charging a detection capacitor with the leakage current of the circuit under test; Detecting the magnitude of the leakage current during the charging of the detection capacitor, and outputting a trigger signal when the leakage current is greater than or equal to a preset threshold; And Providing a compensation current corresponding to the leakage current for the circuit under test according to the trigger signal.

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