Method for manufacturing aluminum nitride substrate, aluminum nitride substrate, and method for suppressing generation of cracks in aluminum nitride layer

Abstract

The present invention is a method for manufacturing an AlN substrate, comprising: a brittle processing step (S10) for reducing the strength of a SiC base substrate (10); and a crystal growth step (S20) for forming an AlN layer (20) on the SiC base substrate (10). Further, the present invention is a method for suppressing generation of cracks in an AlN layer (20), comprising: a brittle processing step (S10) for reducing the strength of a SiC base substrate (10) before forming the AlN layer (20) on the SiC base substrate (10).

Description

Technical Field

[0001] This invention relates to a method for manufacturing an aluminum nitride substrate, an aluminum nitride substrate, and a method for suppressing crack formation in an aluminum nitride layer. Background Technology

[0002] Ultraviolet (UV) light-emitting elements are expected to be used in a wide range of applications, including high-brightness white light sources, high-density information recording light sources, and resin-curing light sources, when combined with germicidal or phosphoric light sources. Aluminum nitride (AlN) is a promising semiconductor material for such UV light-emitting elements.

[0003] Previously, as a method for manufacturing AlN substrates, AlN crystals were grown on substrates with different compositions whose chemical composition differed from that of AlN crystals.

[0004] Patent Document 1 states that, from the viewpoint of having durability in the high-temperature atmosphere of the sublimation process and having a small lattice constant mismatch with AlN crystals, it is preferable to use a silicon carbide (SiC) substrate as the substrate for AlN crystal growth.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2008-13390 Summary of the Invention

[0008] The problem the invention aims to solve

[0009] However, in Patent Document 1, the problem is that cracks are easily generated in the AlN crystal grown on the SiC substrate due to the difference between the thermal expansion coefficient of the SiC substrate on which the AlN crystal is grown and the thermal expansion coefficient of the AlN crystal.

[0010] The problem to be solved by the present invention is to provide a novel technique that can suppress the generation of cracks in AlN layers.

[0011] Problem-solving methods

[0012] The present invention, which solves the above problems, is a method for manufacturing an aluminum nitride substrate, comprising: a brittle processing step to reduce the strength of a silicon carbide substrate; and a crystal growth step to form an aluminum nitride layer on the silicon carbide substrate.

[0013] In this way, by including brittle processing steps that reduce the strength of the SiC substrate, the stress generated in the AlN layer can be released to the SiC substrate, and the generation of cracks in the AlN layer can be suppressed.

[0014] In a preferred embodiment of the invention, the brittle processing step includes: a through-hole forming step for forming through-holes on the silicon carbide substrate; and a strain layer removal step for removing the strain layer introduced by the through-hole forming step.

[0015] In a preferred embodiment of the present invention, the through-hole forming step is performed by irradiating the silicon carbide substrate with a laser to form the through-hole.

[0016] In a preferred embodiment of the invention, the strain layer removal step involves etching the silicon carbide substrate by performing a heat treatment.

[0017] In a preferred embodiment of the invention, the strain layer removal step involves etching the silicon carbide substrate in a silicon atmosphere.

[0018] In a preferred embodiment of the present invention, the crystal growth step is performed using a physical vapor transport method.

[0019] Furthermore, the present invention also relates to a method for suppressing crack formation in an AlN layer. Specifically, the present invention, which solves the above-mentioned problems, is a method for suppressing crack formation in an aluminum nitride layer, comprising: a brittle processing step that reduces the strength of the silicon carbide substrate before forming the aluminum nitride layer on the silicon carbide substrate.

[0020] In a preferred embodiment of the invention, the brittle processing step includes: a through-hole forming step for forming through-holes on the silicon carbide substrate; and a strain layer removal step for removing the strain layer introduced by the through-hole forming step.

[0021] In a preferred embodiment of the invention, the strain layer removal step removes the strain layer of the silicon carbide substrate by performing heat treatment.

[0022] In a preferred embodiment of the present invention, the silicon carbide substrate is silicon carbide; the strain layer removal step involves etching the silicon carbide substrate in a silicon atmosphere.

[0023] The effects of the invention

[0024] Based on the disclosed technology, a novel technique can be provided that can suppress the generation of cracks in AlN layers.

[0025] Other issues, features, and advantages will become apparent from reading the embodiments of the invention described below, in conjunction with the accompanying drawings and claims. Attached Figure Description

[0026] Figure 1 This is an explanatory diagram illustrating the steps of a method for manufacturing an AlN substrate according to an embodiment.

[0027] Figure 2 This is an explanatory diagram illustrating the steps of a method for manufacturing an AlN substrate according to an embodiment.

[0028] Figure 3 This is an explanatory diagram of the through-hole formation steps according to the embodiment.

[0029] Figure 4 This is an explanatory diagram illustrating the crystal growth steps according to the embodiment.

[0030] Figure 5 This is an explanatory diagram of the through-hole formation steps according to Example 1.

[0031] Figure 6 This is an explanatory diagram of the strain layer removal steps according to Example 1.

[0032] Figure 7 This is an explanatory diagram of the crystal growth steps according to Example 1.

[0033] Figure 8 This is an explanatory diagram of the cooling steps according to Example 1. Detailed Implementation

[0034] The preferred embodiments of the method for manufacturing an AlN substrate according to the present invention will be described in detail below with reference to the accompanying drawings. The scope of the present invention is not limited to the embodiments shown in the drawings, and can be appropriately modified within the scope of the claims. Furthermore, the drawings are conceptual diagrams, and the relative dimensions of the components do not constitute a limitation on the present invention. In addition, in this specification, for the purpose of explaining the present invention, the terms "up" and "down" may be used based on the drawings, but are not limited in relation to the use of the AlN substrate of the present invention. Furthermore, in the following description of the embodiments and the accompanying drawings, the same reference numerals are used for the same structures, and repeated descriptions are omitted.

[0035] Fabrication methods for AlN substrates

[0036] Figure 1 and Figure 2 The steps of a method for manufacturing an AlN substrate according to an embodiment of the present invention are shown.

[0037] The method for manufacturing an AlN substrate according to the embodiments may include: a brittle processing step S10 to reduce the strength of a SiC substrate 10; a crystal growth step S20 to form an AlN layer 20 on the SiC substrate 10; and a cooling step S30 to cool the SiC substrate 10 and the AlN layer 20 after the crystal growth step S20.

[0038] Furthermore, this embodiment can be understood as a method for suppressing crack generation in the growth layer 20 by including a brittle processing step S10 that reduces the strength of the SiC substrate 10 before forming the AlN layer 20 on the SiC substrate 10.

[0039] The following is a detailed description of each step of the implementation method.

[0040] <Crispy Processing Steps>

[0041] The brittle processing step is a step that reduces the strength of the SiC substrate 10. In other words, the brittle processing step S10 is a process that makes the SiC substrate 10 more susceptible to deformation or damage by external forces. Furthermore, the brittle processing step S10 increases the fragility of the SiC substrate 10. Additionally, the term "strength" in this specification refers to the durability against physical forces such as compression and tension, and includes the concept of mechanical strength.

[0042] According to the embodiment, the brittle processing step S10 reduces the strength of the SiC substrate 10 by forming through holes 11 on the SiC substrate 10. That is, by reducing the volume of the SiC substrate 10, a processing is applied that makes it easily deformable or damaged by external forces.

[0043] More specifically, the brittle processing step S10 includes: a through-hole forming step S11 for forming a through-hole 11 on the SiC substrate 10; and a strain layer removal step S12 for removing the strain layer 12 introduced through the through-hole forming step S11.

[0044] The SiC substrate 10 can be a wafer or substrate processed from bulk crystals, or a substrate having a buffer layer made of the aforementioned semiconductor material.

[0045] The through-hole forming step S11 reduces the strength of the SiC substrate 10 by forming a through-hole 11 on the SiC substrate 10. This through-hole forming step S11 can be any method that can form a through-hole 11 on the SiC substrate 10.

[0046] The through-hole 11 can be formed by, for example, plasma etching such as laser processing, focused ion beam system (FIB), or reactive ion etching (RIE). Furthermore, in the embodiment shown... Figure 2 The illustration shows a method for forming a through hole 11 by irradiating a SiC substrate 10 with a laser L.

[0047] The through-hole 11 can be shaped to reduce the strength of the SiC substrate 10, and can be formed as a single or multiple through-holes 11. Alternatively, a through-hole group (pattern) formed by arranging multiple through-holes 11 can also be used.

[0048] The following is a detailed description of an example of a pattern for growing a hexagonal semiconductor material.

[0049] Figure 3 This is an explanatory diagram illustrating pattern 100 according to an embodiment. The line segments represented by pattern 100 are SiC substrate 10. Pattern 100 preferably presents a three-dimensionally symmetrical regular hexagonal displacement shape. (Refer to the following...) Figure 3 The term "regular hexagonal displacement shape" as used in this specification will be described in detail. A regular hexagonal displacement shape is a dodecagon. Furthermore, the regular hexagonal displacement shape is composed of 12 line segments of equal length and in a straight line configuration. The pattern 100 presenting the regular hexagonal displacement shape includes a reference figure 101, which is an equilateral triangle with an area and includes three vertices 104. Each of these three vertices 104 is included in the vertex of the pattern 100. Here, the three vertices 104 can be understood as being located on the line segments constituting the pattern 100. The pattern 100 includes: a line segment 102 extending from and including the vertex 104 (equivalent to a first line segment), and a line segment 103 adjacent to the line segment 102 that does not extend from and does not include the vertex 104 (equivalent to a second line segment). Here, the angle θ between two adjacent line segments 102 in the pattern 100 is constant and equal to the angle θ between two adjacent line segments 103 in the pattern 100. In addition, the term "displaced regular hexagon" in this specification can be understood as a dodecagon formed by displacing (deforming) a regular hexagon based on an angle θ representing the degree of concavity or convexity while maintaining the area of ​​the regular hexagon.

[0050] The angle θ is preferably greater than 60°, more preferably 66° or more, more preferably 80° or more, more preferably 83° or more, more preferably 120° or more, more preferably 150° or more, and more preferably 155° or more. Furthermore, the angle θ is preferably less than 180°, more preferably less than 155°, more preferably less than 150°, more preferably less than 120°, more preferably less than 83°, more preferably less than 80°, and more preferably less than 66°.

[0051] The pattern 100 according to the embodiment can also be a six-fold symmetric regular dodecagonal displacement shape, instead of a three-fold symmetric regular hexagonal displacement shape. The regular dodecagonal displacement shape is a 24-sided polygon. Furthermore, the regular dodecagonal displacement shape is composed of 24 line segments of equal length and straight lines. The pattern 100 presenting the regular dodecagonal displacement shape includes a reference shape 101 as a regular hexagon with an area and including 6 vertices 104. Each of the 6 vertices 104 is included in the vertex of the pattern 100. In addition, as with the regular hexagonal displacement shape, the angle θ between two adjacent line segments 102 in the pattern 100 is constant and equal to the angle θ between two adjacent line segments 103 in the pattern 100. That is to say, the "regular dodecagonal displacement shape" in the description of this specification can be understood as a 24-sided polygon formed by displacement (deformation) of the regular dodecagon based on the angle θ representing the degree of concavity and convexity while maintaining the area of ​​the regular dodecagon. Alternatively, pattern 100 can also be a 4n-gon, or 2n-gon displacement shape, formed by shifting (deforming) a regular 2n-gon based on an angle θ representing the degree of concavity or convexity while maintaining the area of ​​the regular 2n-gon. In this case, the 2n-gon displacement shape can be understood as containing a regular n-gon (equivalent to the reference figure 101). Here, the reference figure 101 can be understood as including n vertices.

[0052] The pattern 100 according to the embodiment may also be a structure including a regular 2n-gon displacement shape (including a regular hexagonal displacement shape and a regular 12-gon displacement shape). Furthermore, the pattern 100 may also be a structure that, in addition to the line segments constituting the regular 2n-gon displacement shape, includes at least one line segment (equivalent to a third line segment) connecting the intersection point of two adjacent line segments 103 in the regular 2n-gon displacement shape to the centroid of the reference shape 101. Furthermore, the pattern 100 may also be a structure that, in addition to the line segments constituting the regular 2n-gon displacement shape, includes at least one line segment connecting the intersection point of two adjacent line segments 103 in the regular 2n-gon displacement shape to the vertex 104 constituting the reference shape 101. Furthermore, the pattern 100 may also be a structure that, in addition to the line segments constituting the regular 2n-gon displacement shape, includes at least one line segment constituting the reference shape 101 included in the regular 2n-gon displacement shape.

[0053] Furthermore, the through-hole forming step S11 is preferably a step of removing more than 50% of the effective area of ​​the SiC substrate 10. More preferably, it is a step of removing more than 60% of the effective area, even more preferably, it is a step of removing more than 70% of the effective area, and even more preferably, it is a step of removing more than 80% of the effective area.

[0054] Furthermore, the effective area in this specification refers to the surface of the SiC substrate 10 to which the raw material is attached during the crystal growth step S20. In other words, it refers to the remaining area on the growth surface of the SiC substrate 10 excluding the area removed by the through-hole 11.

[0055] The strain layer removal step S12 is a step of removing the strain layer 12 formed on the SiC substrate 10 through the through-hole forming step S11. This strain layer removal step S12 can be performed by any means that can remove the strain layer 12 introduced into the SiC substrate 10.

[0056] The method for removing the strain layer 12 may include, for example, hydrogen etching using hydrogen as the etching gas, Si vapor etching (SiVE) performed under Si atmosphere, and the etching method described in Example 1 below.

[0057] <Crystal Growth Steps>

[0058] The crystal growth step S20 is the step of forming an AlN layer 20 on the SiC substrate 10 after the brittle processing step S10.

[0059] As for the growth method of AlN layer 20, the crystal growth step S20 can employ known vapor phase growth methods (equivalent to vapor phase epitaxy), such as Physical Vapor Transport (PVT), sublimation recrystallization, modified Rayleigh method, Chemical Vapor Transport (CVT), Molecular-Organic Vapor Phase Epitaxy (MOVPE), and Hydride Vapor Phase Epitaxy (HVPE). Alternatively, the crystal growth step S20 can be replaced by Physical Vapor Deposition (PVD) instead of PVT. Furthermore, the crystal growth step S20 can be replaced by Chemical Vapor Deposition (CVD) instead of CVT.

[0060] Figure 4 This is an explanatory diagram illustrating the crystal growth step S20 according to the embodiment.

[0061] According to the embodiment, the crystal growth step S20 involves placing the SiC substrate 10 and the semiconductor material 40, which forms the raw material for the AlN layer 20, face to face within a crucible 30 having a quasi-enclosed space and heating them. Furthermore, in this specification, "quasi-enclosed space" refers to a space that, while capable of being evacuated, can also contain at least a portion of the vapor generated within the container.

[0062] Furthermore, the crystal growth step S20 is a step of heating to form a temperature gradient along the vertical direction of the SiC substrate 10. By heating the crucible 30 (SiC substrate 10 and semiconductor material 40) in this temperature gradient, the raw material is transported from the semiconductor material 40 to the substrate 10 through the raw material transport space 31.

[0063] The temperature gradient described above can be used as the driving force for conveying raw materials.

[0064] Specifically, within the quasi-enclosed space, vapor composed of elements sublimated from the semiconductor material 40 is transported by diffusion in the raw material transport space 31, and reaches supersaturation and condenses on the SiC substrate 10, where the temperature is set below that of the semiconductor material 40. As a result, an AlN layer 20 is formed on the SiC substrate 10.

[0065] Additionally, in the crystal growth step S20, an inert gas or a dopant gas can be introduced into the raw material transport space 31 to control the doping concentration or growth environment of the AlN layer 20. Furthermore, in the crystal growth step S20, it is desirable to introduce nitrogen gas to create a nitrogen atmosphere inside the raw material transport space 31 for growth.

[0066] This embodiment illustrates an implementation of forming an AlN layer 20 using the PVT method; however, any method capable of forming an AlN layer 20 can certainly be used.

[0067] <Cooling Steps>

[0068] The cooling step S30 is a step to cool down the SiC substrate 10 and AlN layer 20 that were heated in the crystal growth step S20.

[0069] In the cooling step S30, the SiC substrate 10 and the AlN layer 20 shrink according to their respective coefficients of thermal expansion due to the decrease in temperature. At this time, a difference in shrinkage rate occurs between the SiC substrate 10 and the AlN layer 20.

[0070] According to this embodiment, since the strength of the SiC substrate 10 is reduced in the brittle processing step S10, the SiC substrate 10 deforms or forms cracks 13 even when a shrinkage difference occurs between the SiC substrate 10 and the AlN layer 20 (see reference). Figure 2 and Figure 8 ).

[0071] According to the present invention, by including a brittle processing step S10 that reduces the strength of the SiC substrate 10, the stress generated between the SiC substrate 10 and the AlN layer 20 can be released to the SiC substrate 10 and the generation of cracks in the AlN layer 20 can be suppressed.

[0072] Example

[0073] The present invention will be described in more detail by way of Example 1 and Comparative Example 1.

[0074] The lattice mismatch between AlN and SiC is approximately 1%, and the difference in their coefficients of thermal expansion is approximately 23%. In Example 1, crack formation in the AlN layer 20 can be suppressed by releasing the stress caused by this lattice mismatch and the difference in their coefficients of thermal expansion to the SiC substrate 10.

[0075] Example 1

[0076] <Step S11 for forming a through hole>

[0077] Under the following conditions, a laser is irradiated onto a SiC substrate 10 to form a through-hole 11.

[0078] (SiC substrate 10)

[0079] Semiconductor material: 4H-SiC

[0080] Substrate dimensions: 11mm wide × 11mm long × 524μm thick

[0081] Growth surface: Si surface

[0082] Offset angle: coaxial

[0083] (Laser processing conditions)

[0084] Type: Green laser

[0085] Wavelength: 532nm

[0086] Spot diameter: 40μm

[0087] Average output: 4W (at 30kHz)

[0088] (Details of the pattern)

[0089] Figure 5 This is an explanatory diagram illustrating the pattern of the through hole 11 formed in step S11 of the through hole formation according to Embodiment 1. Figure 5 (a) is an explanatory diagram showing the arrangement of the plurality of through holes 11. Figure 5In (a), the black area represents part of the through hole 11, and the white area is reserved as the SiC substrate 10.

[0090] Figure 5 (b) is shown Figure 5 An explanatory diagram showing the enlarged view of the through hole 11 in (a). Figure 5 In (b), the white area represents part of the through hole 11, and the black area is reserved as the SiC substrate 10.

[0091] In addition, Figure 5 In the pattern, more than 80% of the effective area of ​​the SiC substrate 10 is removed, thereby reducing the strength of the SiC substrate 10.

[0092] (Strain layer removal step S12)

[0093] Figure 6 This is an explanatory diagram illustrating step S12 of strain layer removal according to Example 1.

[0094] The SiC substrate 10, which has formed a through-hole 11 through the through-hole forming step S11, is housed in a SiC container 50, and the SiC container 50 is further housed in a TaC container 60, and then heated under the following conditions.

[0095] (Heating conditions)

[0096] Heating temperature: 1800℃

[0097] Heating time: 2 hours

[0098] Etching depth: 8μm

[0099] (SiC container 50)

[0100] Material: Polycrystalline SiC

[0101] Container dimensions: 60mm in diameter × 4mm in height

[0102] Distance between the bottom surfaces of the SiC substrate 10 and the SiC container 50: 2mm

[0103] (Details of SiC container 50)

[0104] like Figure 6 As shown, the SiC container 50 is a fitted container including an upper container 51 and a lower container 52 that can be fitted together. A small gap 53 is formed at the fitting part of the upper container 51 and the lower container 52, which is configured to allow venting (vacuuming) of the SiC container 50 through the gap 53.

[0105] The SiC container 50 has an etching space 54 formed by positioning a portion of the SiC container 50 on the low-temperature side of a temperature gradient relative to the SiC substrate 10. This etching space 54 is used to transport Si and C atoms from the SiC substrate 10 to the SiC container 50 and etch them, driven by the temperature difference between the bottom surfaces of the SiC substrate 10 and the SiC container 50.

[0106] Furthermore, the SiC container 50 has a substrate holder 55 that holds the SiC substrate 10 in mid-air and forms an etching space 54. Alternatively, the substrate holder 55 may be omitted depending on the direction of the temperature gradient in the furnace. For example, if the furnace forms a temperature gradient so that the temperature drops from the lower container 52 to the upper container 51, the SiC substrate 10 may be disposed on the bottom surface of the lower container 52 without the substrate holder 55.

[0107] (TaC container 60)

[0108] Materials: TaC

[0109] Container dimensions: 160mm in diameter × 60mm in height

[0110] Si vapor supply source 64 (Si compound): TaSi2

[0111] (Details of TaC container 60)

[0112] Similar to the SiC container 50, the TaC container 60 is a fitted container comprising an upper container 61 and a lower container 62 that can fit together, and is configured to house the SiC container 50. A small gap 63 is formed at the fitting portion of the upper container 61 and the lower container 62, which allows for venting (vacuuming) of the TaC container 60 through the gap 63.

[0113] The TaC container 60 has a Si vapor supply source 64 capable of supplying a vapor pressure of gaseous species containing Si within the TaC container 60. The Si vapor supply source 64 is simply a structure that generates a vapor pressure of gaseous species containing Si within the TaC container 60 during heat treatment.

[0114] <Crystal growth step S20>

[0115] Figure 7 This is an explanatory diagram illustrating the crystal growth step S20 according to Example 1.

[0116] The SiC substrate 10, after the strain layer 12 has been removed in the strain layer removal step S12, is placed in the crucible 30 in a manner opposite to the semiconductor material 40, and is heated under the following conditions.

[0117] (Heating conditions)

[0118] Heating temperature: 2040℃

[0119] Heating time: 70 hours

[0120] Growth thickness: 500 μm

[0121] N2 gas pressure: 10 kPa

[0122] (Crucible 30)

[0123] Materials: Tantalum carbide (TaC) and / or tungsten (W)

[0124] Container dimensions: 10mm × 10mm × 1.5mm

[0125] Distance between SiC substrate 10 and semiconductor material 40: 1mm

[0126] (Details of crucible 30)

[0127] The crucible 30 has a material transport space 31 between the SiC substrate 10 and the semiconductor material 40. The material is transported from the semiconductor material 40 to the SiC substrate 10 through the material transport space 31.

[0128] Figure 7 (a) is an example of the crucible 30 used in the crystal growth step S20. Like the SiC container 50 and the TaC container 60, the crucible 30 is a fitted container comprising an upper container 32 and a lower container 33 that can be fitted together. A small gap 34 is formed at the fitting portion of the upper container 32 and the lower container 33, which is configured to allow venting (vacuuming) of the crucible 30 through the gap 34.

[0129] Additionally, the crucible 30 has a substrate holder 35 for forming the raw material delivery space 31. The substrate holder 35 is disposed between the SiC substrate 10 and the semiconductor material 40, and the semiconductor material 40 is positioned on the high-temperature side and the SiC substrate 10 is positioned on the low-temperature side to form the raw material delivery space 31.

[0130] Figure 7 (a) and Figure 7 (c) is another example of the crucible 30 used in the crystal growth step S20. Figure 7 (b) and Figure 7 The temperature gradient of (c) is set to be similar to... Figure 7The temperature gradient is opposite to that of (a), and the SiC substrate 10 is disposed on the upper side. That is, with Figure 7 Similar to (a), a material transport space 31 is formed by placing semiconductor material 40 on the high-temperature side and SiC substrate 10 on the low-temperature side.

[0131] Figure 7 (b) shows an example of forming a material delivery space 31 between the SiC substrate 10 and the semiconductor material 40 by fixing the SiC substrate 10 to the side of the upper container 32.

[0132] Figure 7 (c) illustrates an example of forming a material delivery space 31 between the semiconductor material 40 and a through window at the upper container 32, and configuring the SiC substrate 10 thereon. Furthermore, as shown in the diagram... Figure 7 As shown in (c), the raw material conveying space 31 can also be formed by setting an intermediate component 36 between the upper container 32 and the lower container 33.

[0133] (Semiconductor Materials 40)

[0134] Material: AlN sintered body

[0135] Dimensions: 20mm wide x 20mm long x 5mm thick

[0136] (Details of semiconductor material 40)

[0137] The AlN sintered body of semiconductor material 40 is sintered in the following sequence.

[0138] AlN powder was placed inside a TaC block and compacted with moderate force. The compacted AlN powder and TaC block were then placed in a thermally decomposed carbon crucible and heated under the following conditions.

[0139] Heating temperature: 1850℃

[0140] N2 gas pressure: 10 kPa

[0141] Heating time: 3 hours

[0142] <Cooling Steps>

[0143] Finally, the SiC substrate 10 and AlN layer 20 after crystal growth step S20 are cooled under the following conditions.

[0144] (Cooling conditions)

[0145] Substrate temperature before cooling: 2040℃

[0146] Substrate temperature after cooling: room temperature

[0147] Cooling rate: 128℃ / min

[0148] Figure 8 The image is a SEM image obtained from the SiC substrate 10 side after cooling under the above conditions. It can be seen that crack 13 is formed at the SiC substrate 10.

[0149] Multiple cracks 13 were observed in the SiC substrate 10 with AlN substrate manufactured in Example 1. On the other hand, no cracks were observed in AlN layer 20. That is, it was confirmed that there were no cracks in the entire 10 mm × 10 mm region of the AlN crystal growth surface (0001).

[0150] Comparative Example 1

[0151] For the same SiC substrate 10 as in Example 1, the crystal growth step S20 and the cooling step S30 were performed under the same conditions as in Example 1. That is, Comparative Example 1 performed the crystal growth step S20 but did not perform the brittle processing step S10.

[0152] No crack 13 was observed in the SiC substrate 10 with the AlN substrate manufactured in Comparative Example 1. On the other hand, a 1.0 mm crack was observed in the AlN layer 20. -1 The crack line density is defined as follows: The crack line density in this specification refers to the value obtained by summing the lengths of all cracks observed in the measured area and dividing by the measured area (total crack length (mm) / measured area (mm)). 2 Crack linear density (mm²) -1 )).

[0153] The results from Example 1 and Comparative Example 1 can be understood that by using the brittle processing step S10 to reduce the strength of the SiC substrate 10, the stress generated in the AlN layer 20 can be released to the SiC substrate 10, and the generation of cracks in the AlN layer 20 can be suppressed.

[0154] Explanation of reference numerals in the attached figures

[0155] 10 SiC substrate

[0156] 11 Through Holes

[0157] 12 Strain Layer

[0158] 13 Cracks

[0159] 20 AlN layers

[0160] 30 crucibles

[0161] 31 Raw material conveying space

[0162] 40 Semiconductor Materials

[0163] 50 SiC container

[0164] 60 TaC containers

[0165] S10 Brittle Processing Steps

[0166] S11 Through Hole Formation Steps

[0167] S12 Strain Layer Removal Steps

[0168] S20 crystal growth steps

[0169] S30 Cooling Procedure

Claims

1. A method for manufacturing an aluminum nitride substrate, comprising: Brittle processing steps that reduce the strength of silicon carbide substrates; and The crystal growth step of forming an aluminum nitride layer on the silicon carbide substrate; The brittle processing step includes a through-hole forming step, which forms through-holes on the silicon carbide substrate. The through-hole forming step is a step that removes more than 50% of the effective area, where the effective area is the area of ​​the surface of the silicon carbide substrate to which the raw material of the aluminum nitride layer is attached during the crystal growth step.

2. The method for manufacturing an aluminum nitride substrate according to claim 1, wherein, The brittle processing step also includes: The strain layer removal step removes the strain layer introduced by the through-hole forming step.

3. The method for manufacturing an aluminum nitride substrate according to claim 2, wherein, The through-hole forming step is achieved by irradiating the silicon carbide substrate with a laser to form the through-hole.

4. The method for manufacturing an aluminum nitride substrate according to claim 2 or 3, wherein, The strain layer removal step removes the strain layer from the silicon carbide substrate by performing heat treatment.

5. The method for manufacturing an aluminum nitride substrate according to claim 2 or 3, wherein, The strain layer removal step involves etching the silicon carbide substrate in a silicon atmosphere.

6. The method for manufacturing an aluminum nitride substrate according to claim 1 or 2, wherein, The crystal growth step utilizes a physical vapor transport method.

7. An aluminum nitride substrate manufactured by the manufacturing method according to any one of claims 1 to 6.

8. A method for suppressing crack formation in an aluminum nitride layer, comprising: A brittle processing step that reduces the strength of the silicon carbide substrate before forming an aluminum nitride layer on the silicon carbide substrate. The brittle processing step includes a through-hole forming step, which forms through-holes on the silicon carbide substrate. The through-hole forming step is a step of removing more than 50% of the area of ​​the growth surface in the silicon carbide substrate where the aluminum nitride layer is formed.

9. The method according to claim 8, wherein, The brittle processing step also includes: The strain layer removal step removes the strain layer introduced by the through-hole forming step.

10. The method according to claim 9, wherein, The strain layer removal step involves etching the silicon carbide substrate by performing a heat treatment.

11. The method according to claim 9 or 10, wherein, The strain layer removal step involves etching the silicon carbide substrate in a silicon atmosphere.

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