Digital frequency synthesizer, signal compensation method, SOC chip and electronic device

Abstract

The application relates to a digital frequency synthesizer, a signal compensation method, an SOC chip and electronic equipment, and belongs to the integrated circuit field.The digital frequency synthesizer comprises a digital frequency synthesis unit, a phase compensation unit and a phase adjustment unit; the digital frequency synthesis unit is used for generating a first clock signal with a first specified duty cycle according to an externally input first digital phase enable binary code and a multi-path initial phase clock signal; the phase compensation unit is used for generating a target compensation clock signal with a corresponding phase width according to required phase accuracy; and the phase adjustment unit is used for generating an output clock signal with a second specified duty cycle according to the target compensation clock signal and the first clock signal. The first clock signal is compensated by generating the target compensation clock signal with the required phase width, so that a clock signal with an arbitrary duty cycle can be output, and the problem that the existing digital frequency synthesizer can only output a clock signal with a specific frequency is effectively improved.

Description

Technical Field

[0001] This application belongs to the field of integrated circuits, specifically relating to a digital frequency synthesizer, a signal compensation method, a SOC chip, and electronic equipment. Background Technology

[0002] In System-on-Chip (SoC) chips, combinational logic and synchronous sequential logic are commonly used to implement complex chip functions. Synchronous sequential logic requires a clock to control timing. Different functional modules within an SoC chip require different clock frequencies. Taking CPU (Central Processing Unit) design as an example, depending on the functional modules, more than ten different clock frequencies are needed. For instance, the clock frequencies of the high-speed Arithmetic Logic Unit (ALU), the cache, and the analog module are all different.

[0003] Currently, there are two main solutions for providing the clock signal required by a System-on-a-Chip (SoC): The first is to use a PLL (Phase Locked Loop) to provide the clock signal. Although a PLL can output a stable and high-frequency clock signal, it can only provide a single clock output. However, different functional modules of an SoC require different clock frequencies, and each clock requires a separate PLL. This occupies a large area, compresses the area of ​​other functional modules, and consumes a lot of power.

[0004] The second method typically uses a 4-phase input Digital Frequency Synthesizer (DFS) to generate a specific frequency clock. The DFS generates a specific frequency clock based on the externally input Digital Phase Enable Code (DPEC) and the multiple phase clock signals (Clk0, Clk90, Clk180, Clk270) of the same frequency output by the PLL. Specifically, when the DFS receives a DPEC, it internally assigns the received DPEC bit-by-bit to the phase enable signals (En0, En90, En180, En270), thereby generating the corresponding phase enable signals (En0, En90, En180, En270). Then, it uses its own generated phase enable signals (En0, En90, En180, En270) and the received multiple phase clock signals (Clk0, Clk90, Clk180, Clk270) to generate the specific frequency clock. A schematic diagram of the digital frequency synthesizer is shown below. Figure 1 As shown.

[0005] Taking the divide-by-two DFS as an example, the corresponding DPEC binary code has a bit width of 8. Assuming the binary code is 1110_0000, the DFS will cyclically assign values ​​to the phase enable signal bit by bit. For example, in the first clock cycle, the 1110 in the binary code is sequentially assigned to En0, En90, En180, and En270. In the second clock cycle, the 0000 in the binary code is sequentially assigned to En0, En90, En180, and En270, and so on. A schematic diagram is shown below. Figure 2 As shown.

[0006] The output frequency of the digital frequency synthesizer can be adjusted by changing the value of DPEC. In other words, different binary codes correspond to different output frequencies. For example, the binary code 1000_0000 corresponds to a 25% duty cycle of the output clock, the binary code 1100_0000 corresponds to a 37.5% duty cycle of the output clock, the binary code 1110_0000 corresponds to a 50% duty cycle of the output clock, and the binary code 1111_0000 corresponds to a 62.5% duty cycle of the output clock, and so on.

[0007] Although digital frequency synthesizers can output clock signals of different specific frequencies, current 4-phase input digital frequency synthesizers cannot provide duty cycle adjustment with higher accuracy than 1 / 4 phase. This means that the generated clock signals of specific frequencies cannot cover arbitrary duty cycles. In practical high-frequency circuits, especially those with high requirements for clock duty cycles, the application of current DFS is greatly limited, or even unsuitable. For example, since the maximum phase accuracy of existing DFS is 1 / 4, a DFS with a division ratio of 2.25 cannot output a clock signal with a 50% duty cycle, which greatly limits the application of this digital frequency synthesizer. Summary of the Invention

[0008] Therefore, the purpose of this application is to provide a digital frequency synthesizer, a signal compensation method, a SOC chip, and an electronic device to improve the problem that existing digital frequency synthesizers can only output clock signals of a specific frequency, which limits their application and makes them unsuitable for circuits with high clock duty cycle requirements.

[0009] The embodiments of this application are implemented as follows:

[0010] In a first aspect, embodiments of this application provide a digital frequency synthesizer, including: a digital frequency synthesis unit, a phase compensation unit, and a phase adjustment unit; the digital frequency synthesis unit is used to generate a first clock signal with a first specified duty cycle based on an externally input first digital phase enable binary code and multiple initial phase clock signals; the phase compensation unit is used to generate a target compensation clock signal with a corresponding phase width based on the required phase accuracy; the phase adjustment unit is used to generate an output clock signal with a second specified duty cycle based on the target compensation clock signal and the first clock signal.

[0011] In this embodiment, a phase compensation unit is used to generate a target compensation clock signal with a corresponding phase width according to the required phase accuracy, and the target compensation clock signal is used to perform phase compensation on the first clock signal to generate an output clock signal with an arbitrary high precision clock duty cycle. This effectively improves the problem that existing digital frequency synthesizers can only output clock signals of specific frequencies, so as to meet the needs of circuits with high clock duty cycle requirements.

[0012] In one possible implementation of the first aspect embodiment, the phase compensation unit includes: a multi-channel phase compensation generator and a selector; the phase of the compensation clock signal generated by the multi-channel phase compensation generator corresponds one-to-one with the phase of the multi-channel initial phase clock signal; each phase compensation generator is used to generate a compensation clock signal with a corresponding phase width according to the required phase accuracy, wherein the phase of the compensation clock signal generated by different phase compensation generators is different; the selector is connected to each phase compensation generator respectively, and the selector is used to selectively output the target compensation clock signal generated by each phase compensation generator.

[0013] In this embodiment, a multi-channel phase compensation generator is used to generate compensation clock signals with corresponding phase widths but different phases. A selector is used to select the desired target compensation clock signal to adapt to the different phase requirements of the compensation clock signals in different cycles. Since the compensation clock signals generated by different phase compensation generators have the same phase width, the duty cycle of the output clock signal is ensured to be consistent in each cycle.

[0014] In one possible implementation of the first aspect embodiment, the multi-channel phase compensation generator includes a 0-degree phase compensation generator, a 90-degree phase compensation generator, a 180-degree phase compensation generator, and a 270-degree phase compensation generator; the 0-degree phase compensation generator is used to generate a compensation clock signal with a corresponding phase width and a phase delay of 0 degrees according to the required phase accuracy; the 90-degree phase compensation generator is used to generate a compensation clock signal with a corresponding phase width and a phase delay of 90 degrees according to the required phase accuracy; the 180-degree phase compensation generator is used to generate a compensation clock signal with a corresponding phase width and a phase delay of 180 degrees according to the required phase accuracy; and the 270-degree phase compensation generator is used to generate a compensation clock signal with a corresponding phase width and a phase delay of 270 degrees according to the required phase accuracy.

[0015] In this embodiment, a 0-degree phase compensation generator, a 90-degree phase compensation generator, a 180-degree phase compensation generator, and a 270-degree phase compensation generator are used to generate compensation clock signals with phase delays of 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively, to meet the requirements of existing 4-phase input digital frequency synthesizers.

[0016] In one possible implementation of the first aspect embodiment, the digital frequency synthesizer further includes: a phase indication unit, configured to generate a corresponding phase indication signal based on a target initial phase clock signal, wherein the rising edge of the target initial phase clock signal is aligned with the rising edge of the first clock signal; wherein the phase indication signal is configured to select a compensation clock signal generated by a target phase compensation generator as the output of the selector, wherein the phase of the target phase compensation generator is the same as the phase of the target initial phase clock signal.

[0017] In this embodiment, a phase indicator unit is used to generate a phase indicator signal required for selecting a target compensation clock signal, so as to accurately select the required compensation clock signal and avoid logic confusion.

[0018] In one possible implementation of the first aspect embodiment, the digital frequency synthesis unit is further configured to generate a second clock signal with a third specified duty cycle based on the externally input second digital phase enable binary code and the multi-channel initial phase clock signal, wherein the high-level phase width of the second clock signal differs from the high-level phase width of the first clock signal by 1 / 4 clock cycle; correspondingly, the phase adjustment unit is configured to generate the output clock signal based on the target compensation clock signal, the second clock signal and the first clock signal.

[0019] In this embodiment, a second clock signal with a high-level phase width that differs from the high-level phase width of the first clock signal by 1 / 4 clock cycle is generated to achieve precise control of the time window for phase compensation of the first clock signal. This allows for precise selection of the target compensation clock signal to perform phase compensation on the first clock signal, thereby achieving precise control of the duty cycle of the output clock signal.

[0020] In one possible implementation of the first aspect embodiment, the phase adjustment unit includes: an XOR gate, an AND gate, and a logic device; the XOR gate is used to perform an XOR operation on the second clock signal and the first clock signal; the AND gate is used to perform an AND operation on the target compensation clock signal and the clock signal obtained by the XOR operation; the logic device is used to perform a specified logic operation on the first clock signal and the clock signal obtained by the AND operation to generate the output clock signal.

[0021] In the embodiments of this application, the required functions are implemented by employing logic devices such as XOR gates, AND gates, and logic devices, which is easy to implement.

[0022] Secondly, embodiments of this application also provide a signal compensation method, which generates a first clock signal with a first specified duty cycle based on an externally input first digital phase enable binary code and multiple initial phase clock signals; generates a target compensation clock signal with a corresponding phase width based on the required phase accuracy; and generates an output clock signal with a second specified duty cycle based on the target compensation clock signal and the first clock signal.

[0023] In one possible implementation of the second aspect embodiment, generating a target compensation clock signal with a corresponding phase width according to the required phase accuracy includes: generating a compensation clock signal with a corresponding phase width and a phase delay of 0 degrees according to the required phase accuracy; generating a compensation clock signal with a corresponding phase width and a phase delay of 90 degrees according to the required phase accuracy; generating a compensation clock signal with a corresponding phase width and a phase delay of 180 degrees according to the required phase accuracy; generating a compensation clock signal with a corresponding phase width and a phase delay of 270 degrees according to the required phase accuracy; selecting a compensation clock signal with the same phase as the target initial phase clock signal as the target compensation clock signal, wherein the rising edge of the target initial phase clock signal is aligned with the rising edge of the first clock signal.

[0024] In a possible implementation of the second aspect embodiment, the method further includes: generating a second clock signal with a third specified duty cycle based on an externally input second digital phase enable binary code and the multiple initial phase clock signals; wherein the high-level phase width of the second clock signal differs from the high-level phase width of the first clock signal by 1 / 4 clock cycle; correspondingly, generating an output clock signal with a second specified duty cycle based on the target compensation clock signal and the first clock signal, including: generating the output clock signal based on the target compensation clock signal, the second clock signal, and the first clock signal.

[0025] Thirdly, embodiments of this application also provide a SOC chip, including a digital frequency synthesizer provided as described in the first aspect embodiments and / or any possible implementation in conjunction with the first aspect embodiments.

[0026] Fourthly, embodiments of this application also provide an electronic device, including the SOC chip provided in the third aspect of the embodiments described above.

[0027] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing embodiments of this application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The above and other objects, features, and advantages of this application will become clearer through the drawings. The same reference numerals indicate the same parts in all the drawings. The drawings are not intentionally drawn to scale to actual size; the focus is on illustrating the main points of this application.

[0029] Figure 1 This is a schematic diagram of the principle of a digital frequency synthesizer in the prior art.

[0030] Figure 2 This is a schematic diagram illustrating the principle of assigning a phase enable signal to a digital frequency synthesizer based on DPEC in the prior art.

[0031] Figure 3 This is a schematic diagram of the structure of a digital frequency synthesizer provided in an embodiment of this application.

[0032] Figure 4This is a waveform diagram of a target compensation clock signal, a first clock signal, and an output clock signal provided in an embodiment of this application.

[0033] Figure 5 This is a schematic diagram of another digital frequency synthesizer provided in an embodiment of this application.

[0034] Figure 6 This is a schematic diagram of another digital frequency synthesizer provided in an embodiment of this application.

[0035] Figure 7 This is a schematic diagram of another digital frequency synthesizer provided in an embodiment of this application.

[0036] Figure 8 This is a schematic diagram of another digital frequency synthesizer provided in an embodiment of this application.

[0037] Figure 9 This is a waveform diagram of a digital frequency synthesizer provided in an embodiment of this application.

[0038] Figure 10 This is a schematic diagram illustrating the principle of a signal compensation method provided in an embodiment of this application. Detailed Implementation

[0039] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0040] It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one…" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0041] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can also refer to an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0042] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0043] Existing 4-phase input digital frequency synthesizers cannot provide duty cycle adjustment with higher accuracy than 1 / 4 phase, which greatly limits their application in circuits with high clock duty cycle requirements, and even makes them unsuitable for high-frequency circuits. This application provides a digital frequency synthesizer that supports outputting clock signals with arbitrary duty cycles, supporting arbitrary high-precision clock duty cycles, for example, supporting all division ratios and outputting clock signals with a 50% duty cycle.

[0044] To facilitate understanding, the following will be combined with... Figure 3 The digital frequency synthesizer shown is explained below. Figure 3 As shown, the digital frequency synthesizer includes: a digital frequency synthesis unit, a phase compensation unit, and a phase adjustment unit. Both the digital frequency synthesis unit and the phase compensation unit are connected to the phase adjustment unit.

[0045] It should be noted that the digital frequency synthesis unit shown in this application supports multi-phase inputs, including 4-phase input (with a frequency division accuracy of 1 / 4 phase), 6-phase input (with a frequency division accuracy of 1 / 6 phase), and 8-phase input (with a frequency division accuracy of 1 / 8 phase). The principles of digital frequency synthesis units with different inputs are similar; the following description focuses on the 4-phase input digital frequency synthesis unit.

[0046] A digital frequency synthesis unit is used to generate a first clock signal (represented by ClkRaw) with a first specified duty cycle based on an externally input first digital phase enable binary code (DPEC) and multiple initial phase clock signals (such as Clk0, Clk90, Clk180, Clk270). Specifically, the digital frequency synthesis unit first assigns the received DPEC bit-by-bit to the phase enable signals (En0, En90, En180, En270) to generate phase enable signals (En0, En90, En180, En270), and then generates the first clock signal with the first specified duty cycle based on its own generated phase enable signals (En0, En90, En180, En270) and the received multiple initial phase clock signals (such as Clk0, Clk90, Clk180, Clk270). The digital frequency synthesis unit in this embodiment has all the functions of a prior art digital frequency synthesizer, and its schematic diagram can be found in [reference needed]. Figure 1 As shown. It can be understood that if it is a 6-phase input, the 6 initial phase clock signals are Clk0, Clk60, Clk120, Clk180, Clk240, and Clk300 respectively. Similarly, if it is an 8-phase input, the 8 initial phase clock signals are Clk0, Clk45, Clk90, Clk135, Clk180, Clk225, and Clk270 respectively. The other input cases are similar.

[0047] Wherein, En0 is the phase enable signal for Clk0, En90 is the phase enable signal for Clk90, En180 is the phase enable signal for Clk180, and En270 is the phase enable signal for Clk270. It can be understood that if there are 6-phase inputs, the corresponding phase enable signals are En0, En60, En120, En180, En240, and En300, respectively. Similarly, if there are 8-phase inputs, the corresponding phase enable signals are En0, En45, En90, En135, En180, En225, and En270, respectively. The same applies to other inputs.

[0048] Wherein, Clk0 represents the 0-degree phase clock signal output by the PLL, Clk90 represents the clock signal output by the PLL with a phase offset of 1 / 4 phase relative to Clk0 (i.e., 90 degrees phase), Clk180 represents the clock signal output by the PLL with a phase offset of 180 degrees relative to Clk0 and a phase offset of 1 / 4 phase relative to Clk90, and Clk270 represents the clock signal output by the PLL with a phase offset of 270 degrees relative to Clk0 and a phase offset of 1 / 4 phase relative to Clk180. These four initial phase clock signals can originate from the same PLL, thus saving area and power consumption.

[0049] The principle behind how the digital frequency synthesis unit cyclically assigns the received DPEC signals bit by bit to the phase enable signals (En0, En90, En180, En270) can be found in [reference needed]. Figure 2 As shown. It should be noted that different DPECs correspond to different frequencies or duty cycles of the first clock signal. By adjusting the value of the DPEC, the output frequency and output duty cycle of the digital frequency synthesizer can be adjusted.

[0050] In this example, assuming the number of 1s in the DPEC binary code is M and the number of 0s is N, the high-level width of the clock signal output by the digital frequency synthesizer is (M+1) quarter-phase widths, and the low-level width is (N-1) quarter-phase widths. N must be greater than 1; otherwise, a low level cannot be obtained. It should be noted that this explanation uses a 4-phase input digital frequency synthesizer (i.e., a division precision of 1 / 4 phase, or 90 degrees). The principle for the high-level and low-level widths is similar for different division precisions. For example, for an 8-phase input digital frequency synthesizer with a division precision of 1 / 8 phase, or 45 degrees, the high-level width of the clock signal output by the digital frequency synthesizer is (M+1) quarter-phase widths, and the low-level width is (N-1) quarter-phase widths. For example, for a digital frequency synthesizer with 12-phase input, its frequency division accuracy is 1 / 12 phase, which is 30 degrees. Then, the high-level width of the clock signal output by the digital frequency synthesizer is (M+1) 1 / 12 phase widths, and the low-level width is (N-1) 1 / 12 phase widths.

[0051] For example, with a frequency division accuracy of 1 / 4 phase (i.e., a phase of 90°) and DPEC = 1110_0000, the high-level width is (3+1)*90 = 360°, and the low-level width is (5-1)*90 = 360°. Different DPEC combinations can output clocks with different duty cycles, as shown in Tables 1 and 2.

[0052] Table 1

[0053]

[0054]

[0055] Table 2

[0056]

[0057] Table 1 provides an example with a frequency division accuracy of 1 / 4 phase accuracy and an output clock divided by 2. Table 2 provides an example with a frequency division accuracy of 1 / 4 phase accuracy and an output clock divided by 2.25. The bit width of the DPEC binary code = frequency division ratio / frequency division accuracy. For example, for Table 1, the bit width of the DPEC binary code = 2 / 0.25 = 8; for Table 2, the bit width of the DPEC binary code = 2.25 / 0.25 = 9. The duty cycle = high-level width / (high-level width + low-level width).

[0058] It should be noted that the first specified duty cycle of the aforementioned first clock signal depends on the DPEC binary code. For example, taking Table 1 as an example, if the DPEC binary code is 1000_0000, the first specified duty cycle is 25%; if the DPEC binary code is 1100_0000, the first specified duty cycle is 37.5%; if the DPEC binary code is 1110_0000, the first specified duty cycle is 50%; if the DPEC binary code is 1111_0000, the first specified duty cycle is 62.5%; if the DPEC binary code is 1111_1000, the first specified duty cycle is 75%; and if the DPEC binary code is 1111_1100, the first specified duty cycle is 82.5%. Different division ratios correspond to different DPEC binary codes, and the corresponding first specified duty cycles are also different. For example, taking a 2.25 division ratio as an example, the correspondence between the DPEC binary code and the duty cycle can be seen in Table 2.

[0059] The phase compensation unit generates a target compensation clock signal (represented by PhExt) with a corresponding phase width based on the required phase accuracy (supporting arbitrary phase accuracy, such as 1 / 4, 1 / 6, 1 / 8, 1 / 9, 1 / 10, 1 / 16, 1 / 32 phase accuracy, etc.). By generating any desired phase width using the phase compensation unit, the duty cycle of the output clock can be adjusted. For example, generating a target compensation clock signal with a 22.5-degree phase width achieves an adjustment of 1 / 16 phase accuracy. Another example is generating a target compensation clock signal with a 45-degree phase width, achieving an adjustment of 1 / 8 phase accuracy. Yet another example is generating a target compensation clock signal with a 36-degree phase width, achieving an adjustment of 1 / 10 phase accuracy. Yet another example is generating a target compensation clock signal with a 30-degree phase width, achieving an adjustment of 1 / 12 phase accuracy. And yet another example is generating a target compensation clock signal with a 60-degree phase width, achieving an adjustment of 1 / 6 phase accuracy.

[0060] The required phase precision is determined by the desired clock duty cycle and the current clock duty cycle. Taking a 2.25 divider as an example, assuming the current clock duty cycle is 44.4% (high-level width 360 degrees, low-level width 450 degrees), and the required clock duty cycle is 50% (high-level width 405 degrees, low-level width 405 degrees), then the required phase precision is 1 / 8 phase, thus generating a compensated clock signal with a 45-degree phase width. As another example, taking a 2 divider as an example, assuming the current clock duty cycle is 50% (high-level width 360 degrees, low-level width 360 degrees), and the required clock duty cycle is 40% (high-level width 288 degrees, low-level width 432 degrees), then the required phase precision is 1 / 5 phase, thus generating a compensated clock signal with a 72-degree phase width.

[0061] In this design, the rising edge of the target compensation clock signal needs to be aligned with the falling edge of the first clock signal, or vice versa. This allows for the generation of a second specified duty cycle output clock signal by performing a specified logical operation (such as an AND or OR operation) on the target compensation clock signal and the first clock signal. After obtaining the target compensation clock signal and the first clock signal, the phase adjustment unit can generate the second specified duty cycle output clock signal based on them. For example, performing a specified logical operation (such as an AND operation, an OR operation, or other similar operations like addition, subtraction, or XOR) on the target compensation clock signal and the first clock signal will generate the second specified duty cycle output clock signal. To better understand this, let's consider the example above. Assuming the duty cycle of the first clock signal is 44.4%, a target compensation clock signal with a 45-degree phase width needs to be generated. By performing a logical OR operation between the target compensation clock signal and the first clock signal, an output clock signal with a 50% duty cycle can be obtained, as illustrated in the diagram above. Figure 4 As shown. Figure 4 In this context, ClkOut represents the output clock signal with the second specified duty cycle (50% in this case), ClkRaw represents the first clock signal with the first specified duty cycle (44.4% in this case), and PhExt represents the target compensation clock signal with a 45-degree phase width.

[0062] It should be noted that, Figure 4 An example is the case where the rising edge of the target compensation clock signal is aligned with the falling edge of the first clock signal. Alternatively, another target compensation clock signal (where the falling edge of the target compensation clock signal is aligned with the rising edge of the first clock signal) can be used to compensate the first clock signal, which will also yield the desired duty cycle for the output clock signal. Therefore, it is not possible to... Figure 4The target compensation clock signal is understood as a limitation of this application. Specifically, when performing a specified logical operation (such as AND, OR, addition, or subtraction) on the target compensation clock signal and the first clock signal to generate an output clock signal with a second specified duty cycle, if the second specified duty cycle is greater than the first specified duty cycle, then the target compensation clock signal and the first clock signal can be logically ORed or added; if the second specified duty cycle is less than the first specified duty cycle, then the target compensation clock signal and the first clock signal can be logically ANDed, subtracted, or XORed.

[0063] In one optional implementation, the phase compensation unit may include a PLL for generating a target compensation clock signal with a corresponding phase width according to the required phase accuracy. For example, it may generate a target compensation clock signal with a rising edge aligned with the falling edge of the first clock signal, or it may generate a target compensation clock signal with a falling edge aligned with the rising edge of the first clock signal.

[0064] In another implementation, such as Figure 5 As shown, the phase compensation unit includes a multi-channel phase compensation generator and a selector. The phase of the compensation clock signal generated by the multi-channel phase compensation generator corresponds one-to-one with the phase of the multiple initial phase clock signals. Each phase compensation generator is used to generate a compensation clock signal with a corresponding phase width according to the required phase accuracy; different phase compensation generators generate compensation clock signals with different phases. The selector is connected to each phase compensation generator and is used to selectively output the target compensation clock signal generated by each phase compensation generator. Assuming that the multiple initial phase clock signals are Clk0, Clk90, Clk180, and Clk270, the multi-channel phase compensation generator can correspondingly include a 0-degree phase compensation generator, a 90-degree phase compensation generator, a 180-degree phase compensation generator, and a 270-degree phase compensation generator. It can be understood that if the multiple initial phase clock signals are Clk0, Clk45, Clk90, Clk135, Clk180, Clk225, and Clk270... A multi-channel phase compensation generator can include a 0-degree phase compensation generator, a 45-degree phase compensation generator, a 90-degree phase compensation generator, a 135-degree phase compensation generator, a 180-degree phase compensation generator, a 225-degree phase compensation generator, and a 270-degree phase compensation generator. The same applies to other input initial phase clock signals.

[0065] A 0-degree phase compensation generator generates a compensation clock signal with a corresponding phase width and a phase delay of 0 degrees, based on the required phase accuracy. A 90-degree phase compensation generator generates a compensation clock signal with a corresponding phase width and a phase delay of 90 degrees, based on the required phase accuracy. A 180-degree phase compensation generator generates a compensation clock signal with a corresponding phase width and a phase delay of 180 degrees, based on the required phase accuracy. A 270-degree phase compensation generator generates a compensation clock signal with a corresponding phase width and a phase delay of 270 degrees, based on the required phase accuracy.

[0066] It should be noted that the phase width of the compensation clock signal generated by different phase compensation generators can be the same or different.

[0067] In one implementation, each phase compensation generator may include a PLL for generating a compensation clock signal with a corresponding phase width and a phase delay of a specified degree.

[0068] This phase compensation generator can generate a compensated clock signal with the required phase width and a phase delay of a specified degree based on an externally input clock signal. For example... Figure 6 As shown, the 0-degree phase compensation generator generates a compensation clock signal with a corresponding phase width and a phase delay of 0 degrees based on the inputs Clk0 and Clk0dlt; the 90-degree phase compensation generator generates a compensation clock signal with a corresponding phase width and a phase delay of 90 degrees based on the inputs Clk90 and Clk90dlt; the 180-degree phase compensation generator generates a compensation clock signal with a corresponding phase width and a phase delay of 180 degrees based on the inputs Clk180 and Clk180dlt; and the 270-degree phase compensation generator generates a compensation clock signal with a corresponding phase width and a phase delay of 270 degrees based on the inputs Clk270 and Clk270dlt.

[0069] The Clk0dlt, Clk90dlt, Clk180dlt, and Clk270dlt signals are clock signals generated according to the required phase accuracy. Taking a required phase accuracy of 1 / 8 phase as an example, then Clk0dlt = Clk180dlt = Clk45, and Clk270dlt = Clk90dlt = Clk135(90+45). If the required phase accuracy is 1 / 16 of the phase, then Clk0dlt = Clk180dlt = Clk22.5, Clk90dlt = Clk270dlt = Clk112.5 (90 + 22.5). If the required phase accuracy is 1 / 6 of the phase, then Clk0dlt = Clk180dlt = Clk60, Clk270dlt = Clk90dlt = Clk150 (90 + 60). If the phase accuracy is 1 / 12 of the phase, then Clk0dlt = Clk180dlt = Clk30, Clk270dlt = Clk90dlt = Clk120 (90 + 30). And so on. If the phase accuracy is 1 / 10 of the phase, then Clk0dlt = Clk180dlt = Clk36, Clk90dlt = Clk270dlt = Clk126 (90 + 36). Among them, the Clk0dlt, Clk90dlt, Clk180dlt, and Clk270dlt signals mentioned above can be provided by the PLL.

[0070] In one optional implementation, the principle by which the 0-degree phase compensation generator, 90-degree phase compensation generator, 180-degree phase compensation generator, and 270-degree phase compensation generator generate the corresponding compensation clock signals is as follows: Figure 6 As shown. The Clk0dlt signal is inverted (by an inverter) and then ANDed with the Clk0 signal to obtain the Ph0_Ext signal; the Clk90dlt signal is inverted (by an inverter) and then ANDed with the Clk90 signal to obtain the Ph90_Ext signal; the Clk180dlt signal is ANDed with the Clk180 signal to obtain the Ph180_Ext signal; the Clk270dlt signal is ANDed with the Clk270 signal to obtain the Ph270_Ext signal.

[0071] The selector is used to select one of the following signals as the output from Ph0_Ext, Ph90_Ext, Ph180_Ext, and Ph270_Ext. The selector can choose the compensation clock signal generated by the target phase compensation generator as the output based on the phase indication signal, where the phase of the target phase compensation generator is the same as the phase of the target initial phase clock signal. For example, assuming the phase of the target initial phase clock signal is 90 degrees, i.e., the target initial phase clock signal is Clk90, then the target phase compensation generator is a 90-degree phase compensation generator.

[0072] In one optional implementation, the digital frequency synthesizer further includes: a phase indicator unit, such as... Figure 7 As shown. It should be noted that, in one embodiment, the phase indicator unit can be integrated inside the phase compensation unit as an internal component of the phase compensation unit; in another embodiment, it can be separated from the phase compensation unit and arranged in parallel.

[0073] The phase indication unit is used to generate a corresponding phase indication signal (PH0, PH90, PH180, or PH270) based on the target initial phase clock signal, wherein the rising edge of the target initial phase clock signal is aligned with the rising edge of the first clock signal. The phase indication signal is used to select the compensation clock signal generated by the target phase compensation generator as the output of the selector.

[0074] If the first "1" in the first digital phase enable binary code (DPEC) is assigned to En0, then the rising edge of Clk0 is aligned with the rising edge of the first clock signal, and Clk0 is the target initial phase clock signal, with the corresponding phase indicator signal PH0 being high; if the first "1" in the first digital phase enable binary code (DPEC) is assigned to En90, then the rising edge of Clk90 is aligned with the rising edge of the first clock signal, and Clk90 is the target initial phase clock signal, with the corresponding phase indicator signal PH90 being high; if the first digital If the first "1" in the Phase Enable Binary Code (DPEC) is assigned to En180, then the rising edge of Clk180 is aligned with the rising edge of the first clock signal, and Clk180 is the target initial phase clock signal, with the corresponding phase indicator signal PH180 being high. If the first "1" in the first Digital Phase Enable Binary Code (DPEC) is assigned to En270, then the rising edge of Clk270 is aligned with the rising edge of the first clock signal, and Clk270 is the target initial phase clock signal, with the corresponding phase indicator signal PH270 being high.

[0075] Specifically, when PH0 is high (PH0=1), Ph0_Ext is selected for output; when PH90 is high (PH90=1), Ph90_Ext is selected for output; when PH180 is high (PH180=1), Ph180_Ext is selected for output; and when PH270 is high (PH270=1), Ph270_Ext is selected for output.

[0076] To facilitate precise control of the time window for phase compensation of the first clock signal, i.e., when to perform phase compensation on the first clock signal, one optional implementation is as follows: Figure 8As shown, the digital frequency synthesis unit is also used to generate a second clock signal with a specified duty cycle (e.g., denoted by ClkRawEx) based on the externally input second digital phase enable binary code and multiple initial phase clock signals. The high-level phase width of the second clock signal differs from the high-level phase width of the first clock signal by 1 / 4 clock cycle; that is, the high-level phase width of the second clock signal can be 1 / 4 clock cycle more or less than the high-level phase width of the first clock signal. The principle of the digital frequency synthesis unit generating the second clock signal is the same as that of generating the first clock signal (e.g., denoted by ClkRaw), the difference being the DPEC binary code. For the principle of generating the second clock signal, please refer to the above explanation of the principle of generating the first clock signal.

[0077] Accordingly, the phase adjustment unit is used to generate a second specified duty cycle output clock signal based on the target compensation clock signal (e.g., PhExt), the second clock signal (ClkRawEx), and the first clock signal (ClkRaw). For example, the phase adjustment unit performs an XOR operation on the second clock signal and the first clock signal, and then performs an AND operation on the target compensation clock signal and the clock signal obtained by the XOR operation (e.g., represented by PhExtEn). Then, it performs a specified logic operation (e.g., performing an AND operation, or an OR operation, or other similar operations, such as performing addition, subtraction, XOR operation, etc.) on the first clock signal (ClkRaw) and the clock signal obtained by the AND operation (e.g., represented by PhEn) to generate an output clock signal with the required duty cycle. If the second specified duty cycle is greater than the first specified duty cycle, then the clock signal obtained from the AND operation and the first clock signal can be logically ORed or added. If the second specified duty cycle is less than the first specified duty cycle, then the clock signal obtained from the AND operation and the first clock signal can be logically ANDed, subtracted, or XORed.

[0078] The second clock signal is XORed with the first clock signal to obtain the difference part PhExtEn signal. The falling edge of ClkRaw triggers the rising edge of PhExtEn, and the falling edge of ClkRawEx triggers the falling edge of PhExtEn. Alternatively, the falling edge of ClkRawEx triggers the rising edge of PhExtEn, and the falling edge of ClkRaw triggers the falling edge of PhExtEn.

[0079] During the period when the PhExtEn signal is high, the PhEn signal is equal to the PhExt signal. During this period, the PhExt signal and ClkRaw are then subjected to specified logic operations (such as AND operation, OR operation, or other similar operations, such as addition, subtraction, XOR operation, etc.) to generate the output clock signal with the required duty cycle.

[0080] The phase adjustment unit can use software to perform phase compensation on the first clock signal to generate an output clock signal with a second specified duty cycle. For example, when generating an output clock signal with a second specified duty cycle based on the target compensation clock signal, the second clock signal, and the first clock signal, software can be used to XOR the second clock signal with the first clock signal, then perform an AND operation on the target compensation clock signal and the clock signal obtained from the XOR operation (e.g., represented by PhExtEn); then, the first clock signal (ClkRaw) and the clock signal obtained from the AND operation (e.g., represented by PhEn) are subjected to specified logic operations (e.g., performing an AND operation, OR operation, or other similar operations, such as addition, subtraction, XOR operation, etc.) to generate an output clock signal with the required duty cycle.

[0081] In one optional implementation, the phase adjustment unit may perform phase compensation on the first clock signal using purely hardware to generate an output clock signal with a second specified duty cycle. For example, in one implementation, such as... Figure 8 As shown, the phase adjustment unit includes an XOR gate, an AND gate, and logic devices. The XOR gate performs an XOR operation on the second clock signal and the first clock signal; the AND gate performs an AND operation on the target compensation clock signal and the clock signal obtained from the XOR operation; and the logic devices perform specified logic operations (such as performing an AND operation, OR operation, or other similar operations, such as addition, subtraction, XOR operation, etc.) on the first clock signal and the clock signal obtained from the AND operation to generate an output clock signal with the required duty cycle.

[0082] It should be noted that the structure of a logic device depends on the specific logical operation it needs to perform. For example, if the specified logical operation is OR, the logic device can be an OR gate or an adder; if the specified logical operation is AND, the logic device can be an AND gate; and if the specified logical operation is XOR, the logic device can be an XOR gate or a subtractor. Therefore, one cannot simply... Figure 8 The case where the logic device shown is an OR gate is to be understood as a limitation of this application.

[0083] It is understandable that, in addition to directly inputting the second digital phase enable binary code into the digital frequency synthesis unit, in an alternative implementation, the required second digital phase enable binary code can also be generated based on the externally input first digital phase enable binary code. For example, assuming the first digital phase enable binary code is 1_1100_0000 and the second digital phase enable binary code is 1_1110_0000, then simply replacing or updating the first "0" after a consecutive "1" in 1_1110_0000 (the first digital phase enable binary code) with a "1" will yield 1_1110_0000 (the second digital phase enable binary code). Conversely, assuming the first digital phase enable binary code is 1_1110_0000 and the second digital phase enable binary code is 1_1100_0000, then we only need to replace or update the last "1" in 1_1110_0000 (the first digital phase enable binary code) with "0" to obtain 1_1100_0000 (the second digital phase enable binary code).

[0084] To better understand, the following will be combined with... Figure 9 The waveform diagram shown is used for illustration. It should be noted that... Figure 9 This example uses a 2.25 frequency divider and phase compensation to generate a ClkOut signal with a 50% duty cycle from the ClkRaw signal (44.4% duty cycle). The duty cycle of ClkRawEx is 55.6%. By monitoring the values ​​of En0, En90, En180, and En270, the first "0" after a consecutive "1" in DPEC is updated to "1". Then, a new phase enable signal is used to generate another clock signal, ClkRawEx, in the same way as ClkRaw. In this example, the high-level phase width of ClkRawEx is 1 / 4 clock cycle longer than that of ClkRaw.

[0085] Different phase compensation generators can produce compensation clock signals with the same or different phase widths. Therefore, one cannot simply... Figure 9 The fact that the phase widths of the compensation clock signals generated by the different phase compensation generators shown are the same is to be understood as a limitation of this application.

[0086] The XOR operation between ClkRawEx and ClkRaw yields the PhExtEn signal. During Cycle 1 (period 1), the phase indicator signal PH0 is high, and the selector outputs the Ph0_Ext signal. At this time, a AND operation is performed between PhExtEn and Ph0_Ext, and the result is the same as Ph0_Ext. Then, the result of this AND operation is ORed with ClkRaw to obtain a 50% duty cycle. During Cycle 2 (period 2), the phase indicator signal PH90 is high, and the selector outputs the Ph90_Ext signal. At this time, a AND operation is performed between PhExtEn and Ph90_Ext, and the result is the same as Ph90_Ext. Then, the result of this AND operation is ORed with ClkRaw. Alternatively, a 50% duty cycle can be obtained. In Cycle 3, the phase indicator signal PH180 is high, and the selector outputs the Ph180_Ext signal. At this time, the PhExtEn and Ph180_Ext are ANDed, and the result of the AND operation is consistent with Ph180_Ext. Then, the result of the AND operation is ORed with ClkRaw to obtain a 50% duty cycle. In Cycle 4, the phase indicator signal PH270 is high, and the selector outputs the Ph270_Ext signal. At this time, the PhExtEn and Ph270_Ext are ANDed, and the result of the AND operation is consistent with Ph270_Ext. Then, the result of the AND operation is ORed with ClkRaw to obtain a 50% duty cycle.

[0087] Since Ph0_Ext, Ph90_Ext, Ph180_Ext, and Ph270_Ext are generated periodically, the time window for phase compensation of the first clock signal can be precisely controlled through PhExtEn. For example, when performing phase compensation on the first clock signal, Ph0_Ext, Ph90_Ext, Ph180_Ext, or Ph270_Ext is ORed with ClkRaw only during the period when PhExtEn is high, thereby obtaining a clock signal with a duty cycle of 50%.

[0088] Based on the same inventive concept, this application also provides a SOC chip, which includes the aforementioned digital frequency synthesizer. This SOC chip can be any SOC chip requiring multiple different frequency clock signals. For example, it can be various common processors and memories.

[0089] The processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices.

[0090] The memory can be, but is not limited to, Random Access Memory (RAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash memory, etc.

[0091] The digital frequency synthesizer provided in the SOC chip embodiment has the same implementation principle and technical effect as the aforementioned digital frequency synthesizer embodiment. For the sake of brevity, any parts not mentioned in the SOC chip embodiment can be referred to the corresponding content in the aforementioned digital frequency synthesizer embodiment.

[0092] Based on the same inventive concept, this application also provides an electronic device including the above-mentioned SOC chip, the electronic device including the above-mentioned digital frequency synthesizer SOC chip.

[0093] The electronic device can be any electronic device that contains a SOC chip, such as a mobile phone, tablet, computer, server, etc.

[0094] The SOC chip provided in the electronic device embodiment has the same implementation principle and technical effect as the aforementioned SOC chip embodiment. For the sake of brevity, any parts not mentioned in the electronic device embodiment can be referred to the corresponding content in the aforementioned SOC chip embodiment.

[0095] Based on the same inventive concept, embodiments of this application also provide a signal compensation method, such as... Figure 10 As shown. This method can be applied to the aforementioned digital frequency synthesizer. The following will combine... Figure 10 The signal compensation method provided in the embodiments of this application will be described.

[0096] S1: Generate a first clock signal with a first specified duty cycle based on the first digital phase enable binary code input from the outside and the multiple initial phase clock signals.

[0097] Optionally, the aforementioned digital frequency synthesis unit can be used to generate a first clock signal with a first specified duty cycle based on the externally input first digital phase enable binary code and multiple initial phase clock signals.

[0098] S2: Generate a target compensation clock signal with the corresponding phase width according to the required phase accuracy.

[0099] Alternatively, the aforementioned phase compensation unit can be used to generate a target compensation clock signal with a corresponding phase width based on the required phase accuracy.

[0100] S3: Generate an output clock signal with a second specified duty cycle based on the target compensation clock signal and the first clock signal.

[0101] The phase adjustment unit described above can be used to generate a second specified duty cycle output clock signal based on the target compensation clock signal and the first clock signal.

[0102] Optionally, when generating a target compensation clock signal with a corresponding phase width according to the required phase accuracy, the compensation clock signal with a corresponding phase width and a phase delay of 0 degrees can be generated according to the required phase accuracy; the compensation clock signal with a corresponding phase width and a phase delay of 90 degrees can be generated according to the required phase accuracy; the compensation clock signal with a corresponding phase width and a phase delay of 180 degrees can be generated according to the required phase accuracy; the compensation clock signal with a corresponding phase width and a phase delay of 270 degrees can be generated according to the required phase accuracy; and the compensation clock signal with the same phase as the target initial phase clock signal is selected as the target compensation clock signal, wherein the rising edge of the target initial phase clock signal is aligned with the rising edge of the first clock signal. In this embodiment, a multi-channel phase compensation generator in the phase compensation unit can be used to generate compensation clock signals with different phases, and then a selector can be used to select the compensation clock signal with the same phase as the target initial phase clock signal as the target compensation clock signal.

[0103] In one optional implementation, the method further includes: generating a second clock signal with a third specified duty cycle based on an externally input second digital phase enable binary code and multiple initial phase clock signals; wherein the high-level phase width of the second clock signal differs from the high-level phase width of the first clock signal by 1 / 4 clock cycle; correspondingly, generating an output clock signal with a second specified duty cycle based on a target compensation clock signal and a first clock signal, including: generating an output clock signal based on the target compensation clock signal, the second clock signal, and the first clock signal.

[0104] A digital frequency synthesis unit can be used to generate a second clock signal with a specified duty cycle based on an externally input second digital phase enable binary code and multiple initial phase clock signals. Correspondingly, the phase adjustment unit is specifically used to generate an output clock signal based on the target compensation clock signal, the second clock signal, and the first clock signal.

[0105] The implementation principle and technical effects of the method embodiment are the same as those of the aforementioned digital frequency synthesizer embodiment. For the sake of brevity, any parts not mentioned in the method embodiment can be referred to the corresponding content in the aforementioned digital frequency synthesizer embodiment.

[0106] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0107] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A digital frequency synthesizer, characterized in that, include: The digital frequency synthesis unit is used to generate a first clock signal with a first specified duty cycle based on the first digital phase enable binary code input externally and multiple initial phase clock signals. The phase compensation unit is used to generate a target compensation clock signal with a corresponding phase width according to the required phase accuracy. The phase compensation unit includes: a multi-channel phase compensation generator, wherein the phase of the compensation clock signal generated by the multi-channel phase compensation generator corresponds one-to-one with the phase of the multi-channel initial phase clock signal; each phase compensation generator is used to generate a compensation clock signal with a corresponding phase width according to the required phase accuracy; wherein the phases of the compensation clock signals generated by different phase compensation generators are different, the target compensation clock signal is the compensation clock signal generated by the target phase compensation generator among the multi-channel phase compensation generators, the phase of the target phase compensation generator is the same as the phase of the target initial phase clock signal among the multi-channel initial phase clock signals, and the rising edge of the target initial phase clock signal is aligned with the rising edge of the first clock signal; wherein the phase accuracy is determined according to a second specified duty cycle and a first specified duty cycle, and the rising edge of the target compensation clock signal is aligned with the falling edge of the first clock signal, or the falling edge of the target compensation clock signal is aligned with the rising edge of the first clock signal; The phase adjustment unit is used to generate an output clock signal with the second specified duty cycle based on the target compensation clock signal and the first clock signal.

2. The digital frequency synthesizer according to claim 1, characterized in that, The phase compensation unit further includes: The selector is connected to each phase compensation generator and is used to selectively output the target compensation clock signal generated by the target phase compensation generator based on the phase indication signal generated by the target initial phase clock signal.

3. The digital frequency synthesizer according to claim 2, characterized in that, The multi-channel phase compensation generator includes a 0-degree phase compensation generator, a 90-degree phase compensation generator, a 180-degree phase compensation generator, and a 270-degree phase compensation generator. The 0-degree phase compensation generator is used to generate a compensation clock signal with a corresponding phase width and a phase delay of 0 degrees according to the required phase accuracy. The 90-degree phase compensation generator is used to generate a compensation clock signal with a corresponding phase width and a phase delay of 90 degrees according to the required phase accuracy. The 180-degree phase compensation generator is used to generate a compensation clock signal with a corresponding phase width and a phase delay of 180 degrees according to the required phase accuracy. The 270-degree phase compensation generator is used to generate a compensation clock signal with a corresponding phase width and a phase delay of 270 degrees according to the required phase accuracy.

4. The digital frequency synthesizer according to claim 2, characterized in that, The digital frequency synthesizer also includes: A phase indication unit is used to generate a corresponding phase indication signal based on the target initial phase clock signal.

5. The digital frequency synthesizer according to claim 1, characterized in that, The digital frequency synthesis unit is further configured to generate a second clock signal with a third specified duty cycle based on the externally input second digital phase enable binary code and the multi-channel initial phase clock signals, wherein the high-level phase width of the second clock signal differs from the high-level phase width of the first clock signal by 1 / 4 clock cycle; correspondingly, A phase adjustment unit is used to generate the output clock signal based on the target compensation clock signal, the second clock signal, and the first clock signal.

6. The digital frequency synthesizer according to claim 5, characterized in that, The phase adjustment unit includes: An XOR gate is used to perform an XOR operation between the second clock signal and the first clock signal. The AND gate is used to perform an AND operation on the target compensation clock signal and the clock signal obtained by the XOR process; A logic device is used to perform a specified logic operation on the first clock signal and the clock signal obtained by the AND operation to generate the output clock signal.

7. A signal compensation method, characterized in that, Applied to the digital frequency synthesizer as described in claim 1, the method includes: Based on the externally input first digital phase enable binary code and multiple initial phase clock signals, generate a first clock signal with a first specified duty cycle; A target compensation clock signal with a corresponding phase width is generated according to the required phase accuracy; wherein, the phase accuracy is determined according to the second specified duty cycle and the first specified duty cycle, and the rising edge of the target compensation clock signal is aligned with the falling edge of the first clock signal, or the falling edge of the target compensation clock signal is aligned with the rising edge of the first clock signal. Based on the target compensation clock signal and the first clock signal, an output clock signal with the second specified duty cycle is generated.

8. The method according to claim 7, characterized in that, Generate a target compensated clock signal with a corresponding phase width based on the required phase accuracy, including: Generate a compensated clock signal with a corresponding phase width and a phase delay of 0 degrees according to the required phase accuracy; A compensated clock signal with a corresponding phase width and a phase delay of 90 degrees is generated according to the required phase accuracy. A compensated clock signal with a phase width corresponding to the required phase accuracy and a phase delay of 180 degrees is generated. A compensated clock signal with a phase width corresponding to the required phase accuracy and a phase delay of 270 degrees is generated. The target compensation clock signal is selected as the compensation clock signal whose phase is the same as that of the target initial phase clock signal, wherein the rising edge of the target initial phase clock signal is aligned with the rising edge of the first clock signal.

9. The method according to claim 7, characterized in that, The method further includes: Based on the externally input second digital phase enable binary code and the multi-channel initial phase clock signals, a second clock signal with a third specified duty cycle is generated; wherein, the high-level phase width of the second clock signal differs from the high-level phase width of the first clock signal by 1 / 4 clock cycle; correspondingly, Based on the target compensation clock signal and the first clock signal, a second specified duty cycle output clock signal is generated, including: The output clock signal is generated based on the target compensation clock signal, the second clock signal, and the first clock signal.

10. A SOC chip, characterized in that, Includes a digital frequency synthesizer as described in any one of claims 1-6.

11. An electronic device, characterized in that, Including the SOC chip as described in claim 10.

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