A method and system for predicting parasitic parameters in the pre-simulation process of integrated circuits

Abstract

This application relates to the field of analog integrated circuit design technology, and provides a method and system for predicting parasitic parameters in the pre-simulation process of analog integrated circuits. The method includes acquiring a schematic file to be predicted; extracting device parameters and device relationships from the schematic file to obtain a set of device abstract logic; inputting the set of device abstract logic into a pre-established graph neural network model to output a set of pseudo-parasitic parameters; reading the manufacturing process used in the analog integrated circuit; and obtaining the actual set of parasitic parameters of the analog integrated circuit based on the manufacturing process and the set of pseudo-parasitic parameters. The embodiments of this application, based on deep learning neural networks, effectively integrate schematic reading, parasitic parameter prediction, and simulation processes, reducing the number of iterations between schematic design and layout design for chip designers, achieving highly efficient assistance in manual design, and greatly improving the design efficiency and speed of analog integrated circuits.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuit design technology, specifically to a method and system for predicting parasitic parameters in the pre-simulation process of analog integrated circuits. Background Technology

[0002] Analog integrated circuits are a type of integrated circuit that is difficult to design and heavily relies on the designer's experience. In actual design, designers not only need to design the schematic parameters under ideal conditions, but also need to modify the parasitic parameter information extracted from the actual layout. Moreover, the design process has high requirements for the final performance, thus requiring a high level of design experience from the designer.

[0003] During pre-simulation, designers may lack experience and struggle to estimate parasitic parameters in the layout, leading to circuit performance that fails to meet post-simulation performance requirements. In this case, designers manually analyze and adjust component parameters based on simulation results, redraw the layout, and then re-simulate and test both the schematic and layout. This necessitates iterative design processes between schematic and layout design until the designed circuit meets performance requirements.

[0004] Traditional schematic design and pre-simulation parameter tuning require continuous iteration between schematic design and layout design, which consumes a lot of effort; at the same time, manual modification of the layout is inefficient and takes up a lot of time; due to the cumbersome verification process, the development speed is slow in actual operation, which is not conducive to the efficient implementation of analog integrated circuit design flow. Summary of the Invention

[0005] This application provides a method and system for predicting parasitic parameters in the pre-simulation process of simulating integrated circuits.

[0006] In a first aspect, this application provides a method for predicting parasitic parameters in the pre-simulation process of an integrated circuit, including:

[0007] Obtain the schematic file to be predicted;

[0008] Device parameters and device relationships are extracted from the schematic file to be predicted to obtain a set of device abstract logic.

[0009] The device abstract logic set is input into a pre-established graph neural network model, and a pseudo-parasitic parameter set is output. The graph neural network model includes a mapping relationship between the device abstract logic set and the pseudo-parasitic parameter set. The pseudo-parasitic parameter set includes multiple pseudo-parasitic parameters of each device. The pseudo-parasitic parameters are the size parameters that actually affect the electrical properties of parasitic parameters.

[0010] The manufacturing process used in the analog integrated circuit is read, and the actual parasitic parameter set of the analog integrated circuit is obtained based on the manufacturing process and the pseudo parasitic parameter set.

[0011] In one implementation, the graph neural network model is established using the following method:

[0012] Obtain the actual parasitic parameter set of the historical analog integrated circuit layout and the device abstract logic set of the corresponding schematic diagram;

[0013] By combining the manufacturing process corresponding to the historical analog integrated circuit layout, the actual parasitic parameter set of the historical analog integrated circuit layout is processed into pseudo parasitic parameters to obtain the pseudo parasitic parameter set of the historical analog integrated circuit layout. The pseudo parasitic parameter processing refers to normalizing the process-related parameters in the actual parasitic parameter set in combination with the manufacturing process.

[0014] Generative graph neural network models are learned from a training sample set, which includes corresponding records of the device abstract logic set and pseudo-parasitic parameter set of historical analog integrated circuit layouts.

[0015] In one implementation, learning the generative graph neural network model from the training sample set includes:

[0016] Based on the device abstract logic set and the corresponding pseudo-parasitic parameter set, the abstract logic of each device, the circuit module to which each device belongs, and multiple pseudo-parasitic parameters of each device are determined. The abstract logic of each device includes the device parameters, port characteristics connected to other devices, device characteristics of the connected other devices, and multiple pseudo-parasitic parameters of the connected other devices. The device parameters, the port characteristics connected to other devices, and the device characteristics of the connected other devices are extracted from the device abstract logic set of the corresponding schematic diagram of the historical analog integrated circuit layout. The multiple pseudo-parasitic parameters of the connected other devices are extracted from the pseudo-parasitic parameter set of the historical analog integrated circuit layout.

[0017] A graph neural network model is trained and generated based on the corresponding records of the circuit module, abstract logic, and multiple pseudo-parasitic parameters to which each device belongs. The graph neural network model includes the mapping relationship between the abstract logic of the device in each circuit module and the multiple pseudo-parasitic parameters of the device.

[0018] In one implementation, the mapping relationship between the abstract logic of the devices in each circuit module and the multiple pseudo-parasitic parameters of the devices is expressed as follows:

[0019] h v =f(x) v x co[v] h ne[v] xne[v] );

[0020] Among them, h v Let x be a series of pseudo-parasitic parameters of device v, f be a mapping function from the abstract logic of device v to the corresponding pseudo-parasitic parameters of the device, and x be a series of pseudo-parasitic parameters of device v. v For the parameters of device v, x co[v] h represents the port characteristics of device v when it is connected to other devices. ne[v] For multiple pseudo-parasitic parameters of other devices connected to device v, x ne[v] For the device characteristics of other devices connected to device v.

[0021] In one implementation, the step of inputting the device abstract logic set into a pre-established graph neural network model and outputting a pseudo-parasitic parameter set includes:

[0022] Based on the device abstract logic set, determine the circuit module to which each device belongs;

[0023] Select the first device and determine whether the multiple pseudo-parasitic parameters of the other devices connected to the first device have been predicted. The first device is any device in the schematic file to be predicted.

[0024] If multiple pseudo-parasitic parameters of the first device connected to other devices have been predicted, then the abstract logic of the first device is determined by combining the device abstract logic set. The abstract logic of the first device includes the parameters of the first device, the port characteristics of the first device connected to other devices, the device characteristics of the other devices connected to the first device, and multiple pseudo-parasitic parameters of the first device connected to other devices.

[0025] Based on the mapping relationship between the abstract logic of the devices in the circuit module to which the first device belongs and multiple pseudo-parasitic parameters, multiple pseudo-parasitic parameters of the first device are determined.

[0026] The process involves iterating through other devices in the schematic file to be predicted, treating each other device as the first device, and repeatedly determining whether multiple pseudo-parasitic parameters of the first device connected to other devices have been predicted and determining multiple pseudo-parasitic parameters of the first device, until all devices in the schematic file to be predicted have been traversed, thus obtaining a set of pseudo-parasitic parameters.

[0027] In one implementation, after determining whether multiple pseudo-parasitic parameters of the first device connected to other devices have been predicted, the method further includes:

[0028] If multiple pseudo-parasitic parameters of the first device connected to other devices are not predicted, then the multiple pseudo-parasitic parameters of the first device connected to other devices are preset to zero, and the abstract logic of the first device is determined by combining the device abstract logic set.

[0029] Secondly, this application provides a system for predicting parasitic parameters in the pre-simulation process of analog integrated circuits, comprising:

[0030] The acquisition module is used to acquire the schematic file to be predicted;

[0031] The extraction module is used to extract device parameters and device relationships from the schematic file to be predicted, and obtain a set of device abstract logic.

[0032] The pseudo-parasitic parameter prediction module is used to input the device abstract logic set into a pre-established graph neural network model and output a pseudo-parasitic parameter set, wherein the graph neural network model includes a mapping relationship between the device abstract logic set and the pseudo-parasitic parameter set;

[0033] The actual parasitic parameter prediction module is used to read the manufacturing process used in the analog integrated circuit, and to obtain the actual parasitic parameter set of the analog integrated circuit based on the manufacturing process and the pseudo parasitic parameter set.

[0034] In one implementation, the pseudo-parasitic parameter prediction module includes a graph neural network model building unit, which is configured as follows:

[0035] Obtain the actual parasitic parameter set of the historical analog integrated circuit layout and the device abstract logic set of the corresponding schematic diagram;

[0036] By combining the manufacturing processes corresponding to the historical analog integrated circuit layouts, the actual parasitic parameter set of the historical analog integrated circuit layouts is processed with pseudo parasitic parameters to obtain the pseudo parasitic parameter set of the historical analog integrated circuit layouts.

[0037] Generative graph neural network models are learned from a training sample set, which includes corresponding records of the device abstract logic set and pseudo-parasitic parameter set of historical analog integrated circuit layouts.

[0038] Thirdly, this application provides an electronic device, including: a memory and one or more processors; the memory is coupled to the one or more processors, the memory is used to store computer program code, the computer program code including computer instructions; the one or more processors are used to invoke the computer instructions to cause the electronic device to implement the method provided in the first aspect above.

[0039] Fourthly, this application provides a computer storage medium including computer instructions that, when executed on a user device, cause the user device to perform the method provided in the first aspect.

[0040] As can be seen from the above technical solutions, this application provides a method for predicting parasitic parameters in the pre-simulation process of analog integrated circuits, including obtaining a schematic file to be predicted; extracting device parameters and device relationships from the schematic file to obtain a set of device abstract logic; inputting the set of device abstract logic into a pre-established graph neural network model to output a set of pseudo-parasitic parameters, wherein the graph neural network model includes a mapping relationship between the set of device abstract logic and the set of pseudo-parasitic parameters; reading the manufacturing process used in the analog integrated circuit; and obtaining the actual set of parasitic parameters of the analog integrated circuit based on the manufacturing process and the set of pseudo-parasitic parameters. This application effectively integrates schematic reading, parasitic parameter prediction, and simulation processes, reducing the number of iterations between schematic design and layout design for chip designers, and greatly improving the design efficiency and speed of analog integrated circuits. Attached Figure Description

[0041] Figure 1 A flowchart illustrating a method for predicting parasitic parameters in the pre-simulation process of an analog integrated circuit, provided in an embodiment of this application;

[0042] Figure 2 This is a schematic diagram of the structure of a predictive parasitic parameter system for the pre-simulation process of an analog integrated circuit, provided in an embodiment of this application. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0044] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this application, “at least one,” “one or more” refers to one, two, or more than two, and “multiple” refers to two or more. The term “and / or” is used to describe the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can indicate: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character “ / ” generally indicates that the preceding and following related objects are in an “or” relationship.

[0045] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0046] See Figure 1 This application provides a method for predicting parasitic parameters in the pre-simulation process of an analog integrated circuit, the method including steps S1 to S4.

[0047] S1. Obtain the schematic file to be predicted.

[0048] The schematic file of an analog integrated circuit includes the device parameters and relationships in the circuit, as well as the component graphic symbols, component text symbols, component netlists, component coordinates, component rotation angles, coordinates of each component pin, wiring, component tag coordinates, circuit node coordinates, and text annotations.

[0049] S2. Extract all device parameters and all device relationships from the schematic file to be predicted to obtain the device abstract logic set.

[0050] The device parameters and relationships are collected according to the format of the schematic file. For example, the schematic file to be predicted in the EDA (Electronic Design Automation) software is read, and the device parameters and relationships are collected according to the format of the schematic file. The device parameters include the parameters of active devices and the values ​​of passive devices. The parameters of active devices are such as the length and width of CMOS, and the values ​​of passive devices are such as the capacitance and resistance values. The device relationships include the connection methods between transistors, capacitors and resistors in the schematic.

[0051] After extracting device parameters and device relationships, they are logically abstracted into a unique standard format file that can be recognized by neural networks, resulting in a device abstract logic set. The carrier of the device abstract logic set is a unique standard format file that can be recognized by the corresponding model. The mathematical expression of the device abstract logic set is a matrix. The device abstract logic set includes the parameters of each device, the port characteristics of each device connected to other devices, and the device characteristics of other devices connected to each device.

[0052] S3. Input the device abstract logic set into the pre-established graph neural network model and output the pseudo-parasitic parameter set, wherein the graph neural network model includes the mapping relationship between the device abstract logic set and the pseudo-parasitic parameter set.

[0053] This application embodiment first establishes a graph neural network model, which includes the mapping relationship between the device abstract logic set and the pseudo-parasitic parameter set. The method for establishing this graph neural network model is as follows:

[0054] S301. Obtain the actual parasitic parameter set of the historical analog integrated circuit layout and the device abstract logic set of the corresponding schematic diagram.

[0055] This application embodiment obtains multiple historical analog integrated circuit layouts, extracts the actual parasitic parameter set for each historical analog integrated circuit layout, wherein the actual parasitic parameter set includes multiple actual parasitic parameters for each device. Furthermore, based on the schematic file corresponding to the historical analog integrated circuit layout, the device abstract logic set for each schematic file is extracted.

[0056] S302. Combining the manufacturing process corresponding to the historical analog integrated circuit layout, the actual parasitic parameter set of the historical analog integrated circuit layout is processed with pseudo parasitic parameters to obtain the pseudo parasitic parameter set of the historical analog integrated circuit layout.

[0057] By combining the process node file corresponding to each historical analog integrated circuit layout, pseudo-parasitic parameter processing is performed on the actual parasitic parameter set of the historical analog integrated circuit layout to obtain a corresponding pseudo-parasitic parameter set. This pseudo-parasitic parameter set includes multiple pseudo-parasitic parameters for each device in the corresponding historical analog integrated circuit layout. Pseudo-parasitic parameters are dimensional parameters that actually affect the electrical properties of parasitic parameters, such as the aspect ratio of resistors and the area of ​​capacitors. Since the same layout design will produce different actual parasitic parameters under different processes, this embodiment uses pseudo-parasitic parameters as an intermediate product to achieve universality. The process used for each historical analog integrated circuit layout is determined according to the process node file. Pseudo-parasitic parameter processing is performed on the actual parasitic parameter set of the historical analog integrated circuit layout in conjunction with the process file. Pseudo-parasitic parameter processing refers to normalizing process-related parameters such as the resistivity of resistors and the capacitance per unit area of ​​capacitors in the actual parasitic parameters.

[0058] For example, the resistance value of a resistor is generally defined as: Where ρ is the resistivity, which is related to the material constituting the resistor (in analog integrated circuits, this is related to the process used in the analog integrated circuit and the metal layer on which the wire is located), and L and S are the length and cross-sectional area of ​​the resistor (in analog integrated circuits, this is generally the length and width of the wire). When processing pseudo-parasitic parameters, the process-related parameter ρ is set to 1 to obtain the process-independent parameter. The size (in analog integrated circuits, the final result is) These are the length and width of the conductor, respectively.

[0059] S303. Learn a graph neural network model from the training sample set, wherein the training samples include corresponding records of the device abstract logic set and pseudo-parasitic parameter set of historical analog integrated circuit layouts.

[0060] For example, more than 3,000 historical analog integrated circuit layouts are obtained, and the actual parasitic parameter set and the device abstract logic set of the corresponding schematic diagram are extracted from each historical analog integrated circuit layout. After processing the actual parasitic parameter set with pseudo parasitic parameters, more than 3,000 corresponding records of pseudo parasitic parameter sets and device abstract logic sets are obtained.

[0061] After determining multiple sets of known training sample data, a graph neural network model is learned and generated. This graph neural network model includes a mapping relationship between a set of device abstract logic and a set of pseudo-parasitic parameters. In a preferred embodiment, firstly, based on the set of device abstract logic and the corresponding set of pseudo-parasitic parameters, the abstract logic of each device, the circuit module to which each device belongs, and multiple pseudo-parasitic parameters of each device are determined. The abstract logic of each device includes the device parameters, port characteristics connected to other devices, device characteristics of connected other devices, and multiple pseudo-parasitic parameters of connected other devices. The device parameters, the port characteristics connected to other devices, and the device characteristics of connected other devices are extracted from the set of device abstract logic of the corresponding schematic diagram of the historical analog integrated circuit layout. The multiple pseudo-parasitic parameters of connected other devices are extracted from the set of pseudo-parasitic parameters of the historical analog integrated circuit layout.

[0062] For example, based on the device abstract logic set, the parameters of device v, the port characteristics of device v connected to other devices, and the device characteristics of other devices connected to device v are extracted; based on the pseudo-parasitic parameter set corresponding to the device abstract logic set, multiple pseudo-parasitic parameters of other devices connected to device v are determined. Combining the parameters of device v, the port characteristics of device v connected to other devices, the device characteristics of other devices connected to device v, and the multiple pseudo-parasitic parameters of other devices connected to device v, the abstract logic of device v is determined.

[0063] The overall structure of a circuit can be divided into many modules. Even the same part of the circuit will play different roles in different modules within the overall structure. The same part of the circuit will have different parasitic parameters in different modules. In this application embodiment, the module to which each device belongs is determined based on the device abstract logic set. Based on the corresponding records of the circuit module, abstract logic, and multiple pseudo-parasitic parameters to which each device belongs, the mapping relationship between the device abstract logic and multiple pseudo-parasitic parameters of different modules is trained and learned.

[0064] For example, circuit module A, to which device v belongs, trains and learns the mapping relationship of circuit module A using the abstract logic of device v and multiple pseudo-parasitic parameters of device v; circuit module B, to which device u belongs, trains and learns the mapping relationship of circuit module B using the abstract logic of device u and multiple pseudo-parasitic parameters of device u.

[0065] The mapping relationship between the abstract logic of devices in each circuit module and the multiple pseudo-parasitic parameters of the devices can be represented by the following mathematical model:

[0066] h v =f(x) v x co[v] h ne[v] x ne[v] );

[0067] Among them, h v Let x be a series of pseudo-parasitic parameters of device v, f be a mapping function from the abstract logic of device v to the corresponding pseudo-parasitic parameters of the device, and x be a series of pseudo-parasitic parameters of device v. v For the parameters of device v, x co[v] h represents the port characteristics of device v when it is connected to other devices. ne[v] For multiple pseudo-parasitic parameters of other devices connected to device v, x ne[v] For the device characteristics of other devices connected to device v.

[0068] After establishing the graph neural network model, based on the mapping relationship between the device abstract logic set and the pseudo-parasitic parameter set, the device abstract logic set corresponding to the schematic file to be predicted is input into the graph neural network model, and the corresponding pseudo-parasitic parameter set is output.

[0069] In some of the preferred embodiments described above, according to the training method described above, when predicting the pseudo-parasitic parameter set, multiple pseudo-parasitic parameters of each device are predicted one by one to obtain the pseudo-parasitic parameter set. First, based on the input device abstract logic set, the circuit module to which each device belongs is determined, and the parameters of each device, the port characteristics of each device connected to other devices, and the device characteristics of other devices connected to each device are extracted.

[0070] The abstract logic of each device in this application embodiment also includes multiple pseudo-parasitic parameters of other connected devices. Since the pseudo-parasitic parameters of each device are known data during training, but when predicting multiple pseudo-parasitic parameters of a certain device, there may be cases where multiple pseudo-parasitic parameters of other connected devices have not yet been predicted. In this case, this application embodiment presets the multiple pseudo-parasitic parameters of other connected devices to 0 to obtain the abstract logic of the device. Based on the mapping relationship between the abstract logic of the devices in the corresponding circuit module and the multiple pseudo-parasitic parameters, the multiple pseudo-parasitic parameters of the device are obtained.

[0071] Specifically, a first device is selected, and it is determined whether multiple pseudo-parasitic parameters of other devices connected to the first device have been predicted. The first device is any device in the schematic file to be predicted. If multiple pseudo-parasitic parameters of other devices connected to the first device have been predicted, then the abstract logic of the first device is determined by combining the device abstract logic set. The abstract logic of the first device includes the parameters of the first device, the port characteristics of the first device connected to other devices, the device characteristics of the other devices connected to the first device, and the multiple pseudo-parasitic parameters of the other devices connected to the first device. If multiple pseudo-parasitic parameters of other devices connected to the first device have not been predicted, then the first... The pseudo-parasitic parameters of a device connected to other devices are preset to zero. The abstract logic of the first device is determined by combining the device's abstract logic set. Based on the mapping relationship between the abstract logic of the devices in the circuit module to which the first device belongs and the multiple pseudo-parasitic parameters, the multiple pseudo-parasitic parameters of the first device are determined. Other devices in the schematic file to be predicted are traversed, and each other device is treated as the first device. The process of determining whether the multiple pseudo-parasitic parameters of the first device connected to other devices have been predicted and the process of determining the multiple pseudo-parasitic parameters of the first device are repeated until all devices in the schematic file to be predicted have been traversed, resulting in a set of pseudo-parasitic parameters.

[0072] In another preferred embodiment, the optimization problem of the graph neural network model in this application utilizes the SGDM (stochastic gradient descent + moment) optimizer. This optimizer can provide faster neural network learning speed and convergence efficiency. Its mapping convergence method is as follows:

[0073] m t =β·m t-1 +(1-β)·g t ;

[0074] Where, m t Let m be the momentum at time t. t-1 Let g be the momentum at time t-1, β be an empirical value determined by the previously accumulated downward direction, and g be the momentum at time t-1. tLet be the gradient at time t.

[0075] S4. Read the manufacturing process used in the analog integrated circuit, and obtain the actual parasitic parameter set of the analog integrated circuit based on the manufacturing process and the pseudo parasitic parameter set.

[0076] Based on the circuit process address in the schematic file to be predicted, the location of the process file is located and read. Then, the specifications of various parasitic parameters in the process file, such as parasitic resistance, parasitic capacitance, and coupling capacitance, are recorded to ensure more accurate parasitic parameter prediction for different processes.

[0077] For example, the length and width of the conductor are predicted (pseudo-parasitic parameters), and combined with the conductivity and capacitance per unit area (parasitic parameter specifications in the process document), the parasitic resistance and capacitance on the conductor are determined (actual parasitic parameters); the distance between the conductors is predicted (pseudo-parasitic parameters), and combined with the relationship between the coupling capacitance and the distance between the conductors (parasitic parameter specifications in the process document), the magnitude of the coupling capacitance between the conductors is determined (actual parasitic parameters).

[0078] See Figure 2 This application also provides a system for predicting parasitic parameters in the pre-simulation process of an analog integrated circuit. This system is used to execute the aforementioned method for predicting parasitic parameters. The system includes an acquisition module for acquiring a schematic file to be predicted; an extraction module for extracting device parameters and device relationships from the schematic file to obtain a set of device abstract logic; a pseudo-parasitic parameter prediction module for inputting the set of device abstract logic into a pre-established graph neural network model and outputting a set of pseudo-parasitic parameters, wherein the graph neural network model includes a mapping relationship between the set of device abstract logic and the set of pseudo-parasitic parameters; and an actual parasitic parameter prediction module for reading the manufacturing process used in the analog integrated circuit and, based on the manufacturing process and the set of pseudo-parasitic parameters, obtaining the actual parasitic parameter set of the analog integrated circuit. Specific technical details of this system can be found in the aforementioned method for predicting parasitic parameters, and will not be repeated here.

[0079] As can be seen from the above technical solutions, this application provides a method for predicting parasitic parameters in the pre-simulation process of analog integrated circuits, including obtaining a schematic file to be predicted; extracting device parameters and device relationships from the schematic file to obtain a set of device abstract logic; inputting the set of device abstract logic into a pre-established graph neural network model to output a set of pseudo-parasitic parameters, wherein the graph neural network model includes a mapping relationship between the set of device abstract logic and the set of pseudo-parasitic parameters; reading the manufacturing process used in the analog integrated circuit; and obtaining the actual set of parasitic parameters of the analog integrated circuit based on the manufacturing process and the set of pseudo-parasitic parameters. This application, based on a deep learning neural network, effectively integrates schematic reading, parasitic parameter prediction, and simulation processes, reducing the number of iterations between schematic design and layout design for chip designers, achieving efficient assistance in manual design, and greatly improving the design efficiency and speed of analog integrated circuits.

[0080] In a specific implementation, embodiments of this application also provide a computer-readable storage medium, which includes instructions. Wherein, a computer-readable medium disposed in any device, when executed on a computer, can implement instructions including... Figure 1 All or part of the steps in the corresponding embodiments. The storage medium of the computer-readable medium may be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0081] The various illustrative logic units and circuits described in the embodiments of this application can be implemented or operate the described functions using a general-purpose processor, digital information processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor can be a microprocessor; alternatively, it can also be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented using a combination of computing devices, such as a digital information processor and a microprocessor, multiple microprocessors, one or more microprocessors combined with a digital information processor core, or any other similar configuration.

[0082] The steps of the method described in the embodiments of this application can be directly embedded in hardware, a software unit executed by a processor, or a combination of both. The software unit can be stored in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium in the art. Exemplarily, the storage medium can be connected to the processor so that the processor can read information from and write information to the storage medium. Optionally, the storage medium can also be integrated into the processor. The processor and storage medium can be disposed in an ASIC, which can be disposed in the UE. Optionally, the processor and storage medium can also be disposed in different components within the UE.

[0083] It should be understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0084] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0085] The same or similar parts between the various embodiments in this specification can be referred to interchangeably. Each embodiment focuses on the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to in the description of the method embodiments.

[0086] Those skilled in the art will clearly understand that the techniques in the embodiments of the present invention can be implemented using software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments of the present invention.

[0087] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0088] The embodiments described above do not constitute a limitation on the scope of protection of this application.

Claims

1. A method for predicting parasitic parameters in the pre-simulation process of an integrated circuit, characterized in that, include: Obtain the schematic file to be predicted; Device parameters and device relationships are extracted from the schematic file to be predicted to obtain a set of device abstract logic. The device abstract logic set is input into a pre-established graph neural network model, and a pseudo-parasitic parameter set is output. The graph neural network model includes a mapping relationship between the device abstract logic set and the pseudo-parasitic parameter set. The pseudo-parasitic parameter set includes multiple pseudo-parasitic parameters of each device. The pseudo-parasitic parameters are the size parameters that actually affect the electrical properties of parasitic parameters. The manufacturing process used in the analog integrated circuit is read, and the actual parasitic parameter set of the analog integrated circuit is obtained based on the manufacturing process and the pseudo parasitic parameter set; The graph neural network model is established using the following method: Obtain the actual parasitic parameter set of the historical analog integrated circuit layout and the device abstract logic set of the corresponding schematic diagram; By combining the manufacturing process corresponding to the historical analog integrated circuit layout, the actual parasitic parameter set of the historical analog integrated circuit layout is processed into pseudo parasitic parameters to obtain the pseudo parasitic parameter set of the historical analog integrated circuit layout. The pseudo parasitic parameter processing refers to normalizing the process-related parameters in the actual parasitic parameter set in combination with the manufacturing process. Generative graph neural network models are learned from a training sample set, which includes corresponding records of the device abstract logic set and pseudo-parasitic parameter set of historical analog integrated circuit layouts. The method of learning and generating a graph neural network model from a training sample set includes: Based on the device abstract logic set and the corresponding pseudo-parasitic parameter set, the abstract logic of each device, the circuit module to which each device belongs, and multiple pseudo-parasitic parameters of each device are determined. The abstract logic of each device includes the device parameters, port characteristics connected to other devices, device characteristics of the connected other devices, and multiple pseudo-parasitic parameters of the connected other devices. The device parameters, the port characteristics connected to other devices, and the device characteristics of the connected other devices are extracted from the device abstract logic set of the corresponding schematic diagram of the historical analog integrated circuit layout. The multiple pseudo-parasitic parameters of the connected other devices are extracted from the pseudo-parasitic parameter set of the historical analog integrated circuit layout. A graph neural network model is trained and generated based on the corresponding records of the circuit module, abstract logic, and multiple pseudo-parasitic parameters to which each device belongs. The graph neural network model includes the mapping relationship between the abstract logic of the device in each circuit module and the multiple pseudo-parasitic parameters of the device. The step of inputting the abstract logic set of the device into a pre-established graph neural network model and outputting a set of pseudo-parasitic parameters includes: Based on the device abstract logic set, determine the circuit module to which each device belongs; Select the first device and determine whether the multiple pseudo-parasitic parameters of the other devices connected to the first device have been predicted. The first device is any device in the schematic file to be predicted. If multiple pseudo-parasitic parameters of the first device connected to other devices have been predicted, then the abstract logic of the first device is determined by combining the device abstract logic set. The abstract logic of the first device includes the parameters of the first device, the port characteristics of the first device connected to other devices, the device characteristics of the other devices connected to the first device, and multiple pseudo-parasitic parameters of the first device connected to other devices. Based on the mapping relationship between the abstract logic of the device in the circuit module to which the first device belongs and the device in the corresponding circuit module and multiple pseudo-parasitic parameters, multiple pseudo-parasitic parameters of the first device are determined. The process involves iterating through other devices in the schematic file to be predicted, treating each other device as the first device, and repeatedly determining whether multiple pseudo-parasitic parameters of the first device connected to other devices have been predicted and determining multiple pseudo-parasitic parameters of the first device, until all devices in the schematic file to be predicted have been traversed, thus obtaining a set of pseudo-parasitic parameters.

2. The method for predicting parasitic parameters in the pre-simulation process of an analog integrated circuit according to claim 1, characterized in that, The mapping relationship between the abstract logic of the devices in each circuit module and the multiple pseudo-parasitic parameters of the devices is expressed as follows: h v =f(x v ,x co[v] ,h ne[v] ,x ne[v] ); Among them, h v Let x be a series of pseudo-parasitic parameters of device v, f be a mapping function from the abstract logic of device v to the corresponding pseudo-parasitic parameters of the device, and x be a series of pseudo-parasitic parameters of device v. v For the parameters of device v, x co[v] h represents the port characteristics of device v when it is connected to other devices. ne[v] For multiple pseudo-parasitic parameters of other devices connected to device v, x ne[v] For the device characteristics of other devices connected to device v.

3. The method for predicting parasitic parameters in the pre-simulation process of an analog integrated circuit according to claim 1, characterized in that, After determining whether the multiple pseudo-parasitic parameters of other devices connected to the first device have been predicted, the method further includes: If multiple pseudo-parasitic parameters of the first device connected to other devices are not predicted, then the multiple pseudo-parasitic parameters of the first device connected to other devices are preset to zero, and the abstract logic of the first device is determined by combining the device abstract logic set.

4. A system for predicting parasitic parameters in the pre-simulation process of analog integrated circuits, the system being applicable to the method for predicting parasitic parameters in the pre-simulation process of analog integrated circuits according to any one of claims 1 to 3, characterized in that, include: The acquisition module is used to acquire the schematic file to be predicted; The extraction module is used to extract device parameters and device relationships from the schematic file to be predicted, and obtain a set of device abstract logic. The pseudo-parasitic parameter prediction module is used to input the device abstract logic set into a pre-established graph neural network model and output a pseudo-parasitic parameter set, wherein the graph neural network model includes a mapping relationship between the device abstract logic set and the pseudo-parasitic parameter set; The actual parasitic parameter prediction module is used to read the manufacturing process used in the analog integrated circuit, and to obtain the actual parasitic parameter set of the analog integrated circuit based on the manufacturing process and the pseudo parasitic parameter set.

5. The system for predicting parasitic parameters in the pre-simulation process of an analog integrated circuit according to claim 4, characterized in that, The pseudo-parasitic parameter prediction module includes a graph neural network model building unit, which is configured as follows: Obtain the actual parasitic parameter set of the historical analog integrated circuit layout and the device abstract logic set of the corresponding schematic diagram; By combining the manufacturing processes corresponding to the historical analog integrated circuit layouts, the actual parasitic parameter set of the historical analog integrated circuit layouts is processed with pseudo parasitic parameters to obtain the pseudo parasitic parameter set of the historical analog integrated circuit layouts. Generative graph neural network models are learned from a training sample set, which includes corresponding records of the device abstract logic set and pseudo-parasitic parameter set of historical analog integrated circuit layouts.

6. An electronic device, characterized in that, include: A memory, and one or more processors; the memory is coupled to the one or more processors, the memory being used to store computer program code, the computer program code including computer instructions; the one or more processors being used to invoke the computer instructions to cause the electronic device to perform the method of any one of claims 1-3.

7. A computer storage medium, characterized in that, Includes computer instructions that, when executed on a user equipment, cause the user equipment to perform the method of any one of claims 1-3.

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