Wiring method and device, computing device and storage medium

Abstract

The present invention discloses a wiring method and device, a computing device and a storage medium. The wiring method is applied to integrated circuit simulation design, including obtaining a pattern to be wired and a minimum spacing rule for line ends; judging whether there is a line end in an existing layout, wherein when the line end exists, a prohibited area is determined according to the line end and the minimum spacing rule for the line end, and wiring is prohibited in the prohibited area. The wiring method and device, computing device and storage medium according to the embodiments of the present invention can accurately and efficiently complete automatic wiring.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit simulation, and in particular to a wiring method and device, a computing device and a storage medium applied to integrated circuit simulation design. Background Art

[0002] Integrated circuit technology is developing rapidly, and the growing demand requires chips to have shorter design cycles and time to market. Compared with the great progress made in digital integrated circuit layout design automation tools, analog integrated circuit layout design is still a cumbersome, time-consuming, and error-prone manual task due to its design flexibility and circuit sensitivity.

[0003] Routing is the last step in the physical design of integrated circuits. It determines the wire network interconnection scheme based on the logical interconnection relationship given by the netlist and the specific location of the components provided in the layout stage to ensure the correctness of the chip function. The basic requirement of wiring is to achieve 100% interconnection of all wire nets under the premise of meeting the physical design rules. On this basis, other optimization goals are further considered to meet specific constraints. As a very important step in the physical design of integrated circuits, the implementation plan of wiring seriously affects the length of the chip design cycle. Traditional analog layout is based on manual layout technology, but with the diversification of analog circuit design rules and the improvement of semiconductor processes, hand-drawn layouts are seriously lacking in flexibility and popularity when meeting increasingly stringent constraints. This situation has caused the automated wiring method of analog circuits to begin to receive attention, and the research on automatic wiring has become more and more extensive and in-depth.

[0004] The min end of line spacing constraint is one of the many constraints. This constraint requires that the distance from the end of a metal line to another metal line cannot be less than a certain value. If it is violated, it will cause lithography failure. In existing wiring tools, this constraint is not considered, and there is a possibility of design defects.

[0005] Therefore, it is hoped that a new wiring method and device, computing device and storage medium can solve the above problems. Summary of the invention

[0006] In view of the above problems, an object of the present invention is to provide a wiring method and device, a computing device and a storage medium, so as to accurately and efficiently complete automatic wiring.

[0007] According to one aspect of the present invention, there is provided a wiring method, which is applied to integrated circuit simulation design, and the wiring method comprises obtaining a pattern to be wired and a minimum spacing rule for line ends; judging whether there is a line end in an existing layout, wherein when the line end exists, a prohibited area is determined according to the line end and the minimum spacing rule for the line ends, and wiring is prohibited in the prohibited area.

[0008] Optionally, the line end minimum spacing rule includes a first constraint, wherein the first constraint requires that the distance from the line end is greater than a first distance; and a second constraint, wherein the second constraint requires that the distance from both ends of the line end is greater than a second distance.

[0009] Optionally, the prohibited area includes a first prohibited area and a second prohibited area; the first prohibited area is a rectangle whose side lengths are the first distance and the width of the line end, and one side of the first prohibited area coincides with the line end; the second prohibited area is a rectangle whose side lengths are the second distance and the first distance, and one vertex of the second prohibited area coincides with the endpoint of the line end.

[0010] Optionally, when the existing layout is a rectangle, the determining whether there is a line end in the existing layout includes determining whether the length of the first side of the existing layout is greater than the width of the line end, and when the length of the first side of the existing layout is greater than the width of the line end, the second side of the existing layout is a non-line end; and determining whether the length of the second side of the existing layout is greater than the width of the line end, and when the length of the second side of the existing layout is greater than the width of the line end, the first side of the existing layout is a non-line end.

[0011] Optionally, when the existing layout is a rectangle and the initial wiring position of the pattern to be wired is in contact with the existing layout, the judging whether there is a line end in the existing layout includes judging whether the length of the second side of the pattern to be wired is greater than or equal to the length of the second side of the existing layout, and when the length of the second side of the pattern to be wired is less than the length of the second side of the existing layout, the second side of the existing layout is a non-line end, wherein the second side of the pattern to be wired is adjacent to the second side of the existing layout; judging whether the combined pattern of the pattern to be wired at the initial wiring position and the existing layout satisfies the line shortest length constraint, and when the combined pattern of the pattern to be wired at the initial wiring position and the existing layout does not satisfy the line shortest length constraint, the corresponding side of the existing layout is a non-line end.

[0012] Optionally, the wiring method further comprises marking an existing layout at the end of the line to obtain a marking pattern; and determining the prohibited area according to the marking pattern.

[0013] Optionally, determining the prohibited area according to the line end and the minimum spacing rule of the line end includes expanding along the outer frame of the mark graphic according to the minimum spacing rule to obtain the prohibited area, wherein the prohibited area is in contact with the line end.

[0014] Optionally, expanding along the outer frame of the marking graphic includes respectively determining whether each side of the marking graphic is the line end, expanding the side determined to be the line end by a first distance, and expanding the side determined to be a non-line end by a second distance.

[0015] Optionally, the routing method further comprises routing the to-be-wired graphics using a maze routing algorithm according to the prohibited area.

[0016] According to another aspect of the present invention, there is provided a wiring device for use in integrated circuit simulation design, the wiring device comprising an acquisition unit for acquiring a pattern to be wired and a minimum spacing rule for line ends; a judgment unit for judging whether there is a line end in an existing layout; and a wiring unit for wiring, wherein when the line end exists, the wiring unit determines a prohibited area according to the line end and the minimum spacing rule for the line end, and wiring is prohibited in the prohibited area.

[0017] According to another aspect of the present invention, there is provided a computing device, comprising a processor; and a memory for storing one or more programs, wherein when the one or more programs are executed by the processor, the processor implements the wiring method as described above.

[0018] According to another aspect of the present invention, there is provided a computer-readable storage medium having a computer program stored thereon, wherein the program implements the wiring method as described above when executed by a processor.

[0019] According to the wiring method and device, computing device and storage medium of the embodiments of the present invention, the prohibited area for prohibited wiring is determined according to the minimum end of line spacing rule, so that automatic wiring can be completed accurately and efficiently without violating the min end of line spacing design rule.

[0020] Furthermore, during wiring, it is pre-determined whether the existing wiring has a wire end. If so, the existing wiring is expanded to obtain a prohibited area. If not, conventional wiring is used for wiring, which has high wiring efficiency.

[0021] Furthermore, during the wiring process, it is first determined whether there is a line end, and if so, the line end is marked, and then the marked pattern is expanded to obtain a prohibited area, so that the wiring efficiency is high and the wiring effect is good. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0023] Figure 1 A method flow chart of a wiring method according to the first embodiment of the present invention is shown.

[0024] Figure 2 A schematic diagram of a minimum spacing rule according to a first embodiment of the present invention is shown.

[0025] Figure 3 A method flow chart of a wiring method according to the second embodiment of the present invention is shown.

[0026] Figure 4 A schematic diagram showing the end of a judgment line according to a second embodiment of the present invention is shown;

[0027] Figure 5a to Figure 5d A schematic diagram of determining the end of a line according to the second embodiment of the present invention is shown.

[0028] Figure 6 A schematic diagram of external expansion according to the second embodiment of the present invention is shown.

[0029] Figure 7 A schematic diagram of a wiring interface according to Embodiment 3 of the present invention is shown.

[0030] Figure 8 A schematic diagram of wiring effect according to the third embodiment of the present invention is shown.

[0031] Fig. 9 A schematic diagram of the structure of a computing device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0032] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0033] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. Many specific details of the present invention, such as the structure, materials, dimensions, processing technology and techniques of the components are described below to provide a clearer understanding of the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0034] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0035] According to one aspect of the present invention, the inventor provides a wiring method, in particular, a wiring method for an integrated circuit layout that meets EOL Spacing. The wiring method for an integrated circuit layout that meets EOL Spacing (end of line spacing) is a wiring method that meets the design rule min End Of Line Spacing (minimum end of line spacing) during the wiring process of an EDA tool. Before wiring, the EOL (end of line) status of the wire net is marked to guide the wiring behavior.

[0036] Figure 1 FIG. 2 shows a flow chart of a wiring method according to Embodiment 1 of the present invention. Figure 1 As shown, the wiring method according to the first embodiment of the present invention includes the following steps:

[0037] In step S101, the minimum spacing rule between the pattern to be wired and the end of the line is obtained;

[0038] In integrated circuit simulation design, obtain the minimum spacing rules between the wiring graphics and the line ends.

[0039] In step S102, it is determined whether there is a line end in the existing layout;

[0040] Determine whether there is a line end in the existing layout.

[0041] In step S103, a prohibited area is determined.

[0042] When there are line ends in the existing layout, a prohibited area is determined according to the line ends and the minimum spacing rule between the line ends, and wiring is prohibited in the prohibited area.

[0043] Optionally, the minimum spacing rule for line ends includes a first constraint and a second constraint. The first constraint requires that the distance from the line end is greater than the first distance. The second constraint requires that the distance from both ends of the line end is greater than the second distance. Optionally, the prohibited area includes a first prohibited area and a second prohibited area. The first prohibited area is a rectangle with side lengths of the first distance and the width of the line end, and one side of the first prohibited area coincides with the line end. The second prohibited area is a rectangle with side lengths of the second distance and the first distance, and one vertex of the second prohibited area coincides with the endpoint of the line end.

[0044] Specifically, combined Figure 2 As shown, the prohibited area 30 is a min End Of Line Spacing (minimum spacing at the end of a line) design rule violation area, wherein the prohibited area 30 includes a first prohibited area 31 and a second prohibited area 32 .

[0045] The design rules stipulate that the spacing from the end of a metal line to another metal cannot be less than a value. Violating this will result in lithography failure. Therefore, if the edge of a metal line is determined to be the end-of-line, no graphics can exist in the area above the end of the line. Among them, when routing, eol Width is the width of the end of the metal line, that is, the width of the end of the line of the existing layout 10; eol space is the minimum spacing that needs to be satisfied between the end of a metal line to another metal line, that is, the first distance that needs to be satisfied between the end of the line of the existing layout 10 and the graphics 20 to be routed; eol Within is the distance from the two ends of the area to the two ends of the metal line, that is, the second distance required by the second constraint. Optionally, the two rule values ​​of eol within and eol spacing are directly given by the process, and the values ​​are obtained by reading the process file in the early stage of the implementation of the routing plan.

[0046] Figure 3 FIG. 2 shows a flow chart of a wiring method according to Embodiment 2 of the present invention. Figure 3 As shown, the wiring method according to the second embodiment of the present invention includes the following steps:

[0047] In step S201, the pattern to be wired and the process constraints are read;

[0048] Read the coordinates of the graphics to be wired and the process constraint min End Of Line Spacing value (minimum spacing rule at the end of the line).

[0049] In step S202, EOL determination and marking are performed;

[0050] Determine the end of line (EOL) in an existing layout and mark the determined end of line.

[0051] Combination Figure 4 and Figure 5a to Figure 5d As shown, the marked object is the existing layout ra, that is, when it is detected that one or more edges of the existing layout ra meet the line end condition, ra is marked. Then, a forbidden area is obtained near ra, and the layout rb to be wired is forbidden to appear in the forbidden area. Optionally, the existing layout ra can be a complete figure, or a part of a complete figure, such as the line end part of the complete figure.

[0052] Optionally, when the existing layout ra is rectangular, determine whether there is a line end in the existing layout ra, determine whether the length of the first side of the existing layout ra is greater than the width of the line end. When the length of the first side of the existing layout ra is greater than the width of the line end, the second side of the existing layout ra is not a line end; determine whether the length of the second side of the existing layout ra is greater than the width of the line end. When the length of the second side of the existing layout ra is greater than the width of the line end, the first side of the existing layout ra is not a line end. Combine Figure 4 As shown, first determine the width and height of the existing layout ra. If ra.width()>eol_width, it means that the yb and yt sides are not EOLs; if ra.height()>eol_width, it means that the xl and xr sides are not EOLs.

[0053] Optionally, when the existing layout ra is rectangular and the initial routing position of the routing pattern rb to be routed is in contact with the existing layout ra, determine whether there is a line end in the existing layout ra, determine whether the length of the second side of the routing pattern rb to be routed is greater than or equal to the length of the second side of the existing layout ra. When the length of the second side of the routing pattern rb to be routed is less than the length of the second side of the existing layout ra, the second side of the existing layout ra is not a line end, where the second side of the routing pattern rb to be routed is adjacent to the second side of the existing layout ra; or determine whether the combined pattern of the routing pattern rb to be routed at the initial routing position and the existing layout ra satisfies the minimum line length constraint. When the combined pattern of the routing pattern rb to be routed at the initial routing position and the existing layout ra does not satisfy the minimum line length constraint, the corresponding side of the existing layout ra is not a line end.

[0054] Figure 5a to Figure 5d Shows several possible intersection ways that the existing layout ra and the routing pattern rb to be routed that may violate the design rules may present. Combine Figure 4 and Figures 5a to 5d As shown, if the xl side of the existing layout ra is to be an EOL, the following conditions need to be met: First, it is required that rb.xl()>=ra.xl(). If violated, the xl side is not an EOL, Figure 5a Meets the requirements, Figure 5b Does not meet the requirements. Second, it is required that the length of the generalized L-shaped line formed by the two rectangles (the existing layout ra and the routing pattern rb to be routed) meets the minimum line length constraint requirements. There are two possibilities: rb.yb>ra.yb&&rb.yt<ra.yt. At this time, the length of the combined pattern of the existing layout ra and the routing pattern rb to be routed has met eol_length, or rb.xl()>=ra.xl()+eol_length, where eol_length is the minimum length of the metal line applying the EOL constraint requirement. Here, it corresponds to the L-shaped metal line. Figure 5c Meets the requirements, Figure 5dDoes not meet the requirements. Traverse all the to-be-wired graphics rb in the to-be-wired graphics set. If a to-be-wired graphics rb violates the above rules, the xl edge of the existing layout ra should be set to non-EOL. The judgment of the other three edges is similar. In summary, all to-be-wired graphics rb that are in contact with the existing wiring ra can be found, and it can be judged whether the to-be-wired graphics rb will cause a certain edge of the existing layout ra to be converted to non-EOL.

[0055] In step S203, the outer frame of the marking graphic is expanded by eol_spacing;

[0056] Expand the outer frame of the marking graphic by eol_spacing. Specifically, mark an existing layout where a line end exists, obtain the marking graphic, and determine the prohibited area (the prohibited area is the expanded eol_spacing part) according to the marking graphic. Optionally, according to the minimum spacing rule, expand along the outer frame of the marking graphic to obtain the prohibited area, wherein the prohibited area contacts the line end. Optionally, expanding along the outer frame of the marking graphic includes respectively determining whether each side of the marking graphic is a line end, expanding the side determined to be a line end by a first distance, and expanding the side determined to be a non-line end by a second distance.

[0057] Reference Figure 6 As shown, when at least one EOL exists, whether to expand outward is determined based on whether the four edges are EOLs. If the edge is EOL, eol_spacing is expanded outward; if not, eol_within is expanded outward. The lengths of eol_spacing and eol_within are determined by the process file, and the process file will be imported in advance before using this method.

[0058] In step S204, a path is searched and routed according to the new routing resources.

[0059] According to the new routing resources, the path is searched and routed, that is, when searching the path and routing, routing in the prohibited area is prohibited. Optionally, according to the prohibited area, the maze routing algorithm is used to route the routing pattern, that is, when routing, the external expansion pattern is used as the routing resource occupied by the identified EOL to guide the routing.

[0060] Figure 7 A schematic diagram of a wiring interface according to Embodiment 3 of the present invention is shown. Figure 8 FIG. 2 shows a schematic diagram of the wiring effect according to the third embodiment of the present invention. Figure 7 and Figure 8 As shown, in a specific embodiment, the wiring method includes the following steps:

[0061] Step 1: Read the coordinate information of the graphics to be wired on the layout, and read in the min End Of Line Spacing design rule (minimum spacing rule at the end of the line) specified by the process.

[0062] Step 2: Traverse the shapes on the layout to perform EOL judgment. If it is EOL, mark the shape; otherwise, continue to judge the next shape.

[0063] Step 3: Expand the outer frame of the marked shape by a distance of spacing: If all four sides are EOL, expand the rectangle by a distance of eol_spacing to obtain a legal routing space to prevent violation of the min End Of Line Spacing design rule. If not, expand by eol_within. During the routing search path stage, the expanded area is defaulted to non-routable resources, and no path search is performed on its inner area.

[0064] Step 4: The routing result is as Figure 8 shown. The left and right sides of the small rectangular obstacle in the middle are judged as EOL, so the original traces that could fit the obstacle would violate the EOL Spacing constraint. To avoid this constraint violation, the router chooses to expand the outer frame of the small rectangular obstacle by eol_within and then perform routing.

[0065] According to the routing method of the embodiment of the present invention, EOL judgment is performed based on the coordinate information of the shape to be routed before routing, and it is pre-determined whether it is EOL according to the possible metal wire intersection patterns. First, judge the width and height of rectangle ra. When ra.width() > eol_width, the yb and yt sides are not EOL; when ra.height() > eol_width, the xl and xr sides are not EOL. Secondly, it is required that the length of the generalized L-shaped line formed by two rectangles meets the requirements: rb.yb > ra.yb && rb.yt < ra.yt. At this time, the length of the shape formed by ra and rb is ra.length, which already meets eol_length, or rb.xl() >= ra.xl() + eol_length, where eol_length is the shortest length of the metal wire required by applying the EOL constraint, corresponding to the L-shaped metal wire here, so that automatic routing can be completed without violating the minimum end-to-end spacing rule.

[0066] According to another aspect of the present invention, a routing device is provided, for example, used to implement the above routing method. This routing device is applied to integrated circuit simulation design and includes an acquisition unit for acquiring the shape to be routed and the minimum end-to-end spacing rule; a judgment unit for judging whether there is an end of line in the existing layout; and a routing unit for routing. Among them, when there is the end of line, the routing unit determines a prohibited area according to the end of line and the minimum end-to-end spacing rule, and routing is prohibited in the prohibited area.

[0067] Fig. 9FIG. 2 shows a schematic diagram of the structure of a computing device according to an embodiment of the present invention. Fig. 9 , the present disclosure also provides a block diagram of an exemplary computing device suitable for implementing the embodiments of the present disclosure. It should be understood that Fig. 9 The computing device shown is only an example and should not bring any limitation to the functionality and scope of use of the embodiments of the present disclosure.

[0068] like Fig. 9 As shown, the computing device 200 is in the form of a general computing device. The components of the computing device 200 may include, but are not limited to: one or more processors or processing units 210, a memory 220, and a bus 201 connecting different system components (including the memory 220 and the processing unit 210).

[0069] Bus 201 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor or a local bus using any of a variety of bus structures. For example, these architectures include but are not limited to Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus and Peripheral Component Interconnect (PCI) bus.

[0070] The computing device 200 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the computing device 200, including volatile and non-volatile media, removable and non-removable media.

[0071] System memory 220 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 221 and / or cache memory 222. Computing device 200 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 223 may be used to read and write non-removable, non-volatile magnetic media ( Fig. 9 not shown, usually called a "hard drive"). Although Fig. 9 Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, a DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 201 via one or more data medium interfaces. Memory 220 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of each embodiment of the present disclosure.

[0072] A program / utility 224 having a set (at least one) of program modules 2241 may be stored, for example, in the memory 220, such program modules 2241 including but not limited to an operating system, one or more application programs, other program modules, and program data, each of which or some combination thereof may include an implementation of a network environment. The program modules 2241 generally perform the functions and / or methods of the embodiments described in the embodiments of the present disclosure.

[0073] Further, the computing device 200 may also be connected to a display 300 for displaying the results of the screening and sorting. The display 300 may include, but is not limited to, a liquid crystal display (LCD), a light emitting diode (LED) display, and a plasma display. In some embodiments, the display 300 may also be a touch screen.

[0074] Further, the computing device 200 may also communicate with one or more devices that enable a user to interact with the computing device 200, and / or communicate with any device (e.g., a network card, a modem, etc.) that enables the computing device 200 to communicate with one or more other computing devices. Such communication may be performed via an input / output (I / O) interface 230. Furthermore, the computing device 200 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 240. As shown, the network adapter 240 communicates with other modules of the computing device 200 via a bus 201. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the computing device 200, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0075] The processing unit 210 executes various functional applications and data processing by running programs stored in the system memory 220 .

[0076] According to another aspect of the present invention, there is provided a computer-readable storage medium having a computer program (or computer-executable instructions) stored thereon, which, when executed by a processor, is used to execute the wiring method provided by an embodiment of the present disclosure, and is applied to integrated circuit simulation design, wherein the wiring method comprises obtaining a pattern to be wired and a minimum spacing rule for line ends; and determining whether a line end exists in an existing layout, wherein, when the line end exists, a prohibited area is determined according to the line end and the minimum spacing rule for the line end, and wiring is prohibited in the prohibited area.

[0077] The computer storage medium of the embodiment of the present disclosure may adopt any combination of one or more computer-readable media. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by an instruction execution system, device or device or used in combination with it.

[0078] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0079] The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0080] Computer program code for performing the operation of the disclosed embodiments may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​(such as Java, Smalltalk, C++), and conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or computing device. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect through the Internet).

[0081] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0082] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A wiring method, applied to integrated circuit simulation design, the wiring method comprising: Get the minimum spacing rule between the graphics to be routed and the end of the line; Determine whether there is a line end in the existing layout, Wherein, when the line end exists, a prohibited area is determined according to the line end and the minimum spacing rule of the line end, and wiring is prohibited in the prohibited area; The minimum spacing rules for line ends include: a first constraint requiring that a distance from an end of the line be greater than a first distance; A second constraint, wherein the second constraint requires that the distance from both ends of the line be greater than a second distance; The prohibited area includes a first prohibited area and a second prohibited area; The first forbidden area is a rectangle whose side lengths are the first distance and the width of the line end, and one side of the first forbidden area coincides with the line end; The second forbidden area is a rectangle whose sides are the second distance and the first distance respectively, and a vertex of the second forbidden area coincides with an endpoint of the end of the line; When the existing layout is a rectangle, determining whether there is a line end in the existing layout includes: Determine whether the length of the first side of the existing layout is greater than the width of the line end, and when the length of the first side of the existing layout is greater than the width of the line end, the second side of the existing layout is a non-line end; It is determined whether the length of the second side of the existing layout is greater than the width of the line end. When the length of the second side of the existing layout is greater than the width of the line end, the first side of the existing layout is a non-line end.

2. The wiring method according to claim 1, wherein: In the case where the existing layout is a rectangle and the initial wiring position of the pattern to be wired contacts the existing layout, the determining whether there is a line end in the existing layout comprises: Determine whether the length of the second side of the pattern to be wired is greater than or equal to the length of the second side of the existing layout, when the length of the second side of the pattern to be wired is less than the length of the second side of the existing layout, the second side of the existing layout is a non-line end, wherein the second side of the pattern to be wired is adjacent to the second side of the existing layout; It is determined whether the combined graph of the to-be-wired graph at the initial wiring position and the existing layout meets the line shortest length constraint. When the combined graph of the to-be-wired graph at the initial wiring position and the existing layout does not meet the line shortest length constraint, the corresponding edge of the existing layout is a non-line end.

3. The wiring method according to claim 1, wherein: The wiring method further comprises: Marking the existing layout at the end of the line to obtain a marked pattern; The prohibited area is determined according to the marking pattern.

4. The wiring method according to claim 3, wherein: The determining of the prohibited area according to the line end and the line end minimum spacing rule comprises: According to the minimum spacing rule, the forbidden area is expanded along the outer frame of the marking graphic to obtain the forbidden area, wherein the forbidden area is in contact with the end of the line.

5. The wiring method according to claim 4, wherein: Expanding along the outer frame of the marking graphic includes: It is determined whether each side of the marking pattern is the line end, and the side determined to be the line end is expanded by a first distance, and the side determined to be not the line end is expanded by a second distance.

6. The wiring method according to claim 1, wherein: The wiring method further comprises: According to the prohibited area, the to-be-wired pattern is wired using a maze wiring algorithm.

7. A wiring device, applied to integrated circuit simulation design, the wiring device comprising: An acquisition unit, used for acquiring the minimum spacing rule between the graphics to be wired and the end of the wire; A judging unit, used to judge whether there is a line end in the existing layout; as well as Wiring unit for wiring, Wherein, when the line end exists, the wiring unit determines a prohibited area according to the line end and the minimum spacing rule of the line end, and the prohibited area prohibits wiring; The minimum spacing rules for line ends include: a first constraint requiring that a distance from an end of the line be greater than a first distance; A second constraint, wherein the second constraint requires that the distance from both ends of the line be greater than a second distance; The prohibited area includes a first prohibited area and a second prohibited area; The first forbidden area is a rectangle whose side lengths are the first distance and the width of the line end, and one side of the first forbidden area coincides with the line end; The second forbidden area is a rectangle whose sides are the second distance and the first distance respectively, and a vertex of the second forbidden area coincides with an endpoint of the end of the line; When the existing layout is a rectangle, determining whether there is a line end in the existing layout includes: Determine whether the length of the first side of the existing layout is greater than the width of the line end, and when the length of the first side of the existing layout is greater than the width of the line end, the second side of the existing layout is a non-line end; It is determined whether the length of the second side of the existing layout is greater than the width of the line end. When the length of the second side of the existing layout is greater than the width of the line end, the first side of the existing layout is a non-line end.

8. A computing device, comprising: processor; a memory for storing one or more programs, When the one or more programs are executed by the processor, the processor implements the wiring method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, wherein: When the program is executed by a processor, the wiring method according to any one of claims 1 to 6 is implemented.

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