Semiconductor memory structure and method for forming the same

Abstract

The present invention provides a semiconductor memory structure and a method for forming the same, wherein the method comprises forming a plurality of conductive wire structures on a semiconductor substrate, and forming a plurality of spacer structures along the sidewalls of the conductive wire structures. Each spacer structure comprises a first spacer. The method further comprises forming a plurality of dielectric strips across the conductive wire structures, forming a plurality of conductive strips extending above the dielectric strips and the conductive wire structures, patterning the conductive strips to form a plurality of conductive pads, and removing the first spacer of each spacer structure to form a gap in each spacer structure.

Description

Technical Field

[0001] The invention relates to a semiconductor memory structure, and in particular to a dynamic random access memory. Background Art

[0002] In order to increase the density of components in a dynamic random access memory (DRAM) device and improve its overall performance, the manufacturing technology of DRAM devices continues to strive towards miniaturization of component size. Therefore, improving the manufacturing method of DRAM devices is an important issue that must be faced at present. Summary of the invention

[0003] An embodiment of the present invention provides a method for forming a semiconductor memory structure. The method includes forming a plurality of conductive wire structures on a semiconductor substrate, and forming a plurality of spacer structures along the sidewalls of the conductive wire structures. Each spacer structure includes a first spacer. The method also includes forming a plurality of dielectric strips across the conductive wire structures, forming a plurality of conductive strips extending above the dielectric strips and the conductive wire structures, patterning the conductive strips to form a plurality of conductive pads, and removing the first spacer of each spacer structure to form a gap in each spacer structure.

[0004] An embodiment of the present invention provides a semiconductor memory structure. The semiconductor memory structure includes a first conductive line structure and a second conductive line structure disposed on a semiconductor substrate, a first spacer structure adjacent to a first side of the first conductive line structure, and a second spacer structure adjacent to a second side of the second conductive line structure. Each of the first spacer structure and the second spacer structure includes an air gap. The semiconductor memory structure also includes:

[0005] A first dielectric strip and a second dielectric strip extending across the first conductive line structure and the second conductive line structure, a first contact plug disposed in a space defined by the first conductive line structure, the second conductive line structure, the first dielectric strip and the second dielectric strip, and a first conductive pad disposed on the first contact plug. The first conductive pad partially covers both the first spacer structure and the second spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to make the features and advantages of the present invention more clearly understood, different embodiments are described in detail below with reference to the accompanying drawings:

[0007] Figures 1A to 1J 2 is a schematic plan view showing different stages of forming a semiconductor memory structure according to some embodiments of the present invention.

[0008] Figure 1A-1 to Figure 1J-1 , Figure 1A-2 to Figure 1J-2 , Figures 1A-3 to 1J-32 is a schematic cross-sectional view showing different stages of forming a semiconductor memory structure according to some embodiments of the present invention.

[0009] Figure 1C-4 to Figure 1J-4 2 is a schematic cross-sectional view showing different stages of forming a semiconductor memory structure according to some embodiments of the present invention.

[0010] Figure 2 , Figure 3 is a schematic plan view of a semiconductor memory structure according to some embodiments of the present invention.

[0011] Figure 2-1 , Figure 3-1 It is a cross-sectional schematic diagram showing the structure of a semiconductor memory.

[0012] Explanation of symbols

[0013] 100: semiconductor memory structure;

[0014] 102: semiconductor substrate;

[0015] 104: active area;

[0016] 106: isolation structure;

[0017] 108: lining;

[0018] 110: insulating material;

[0019] 112: gate structure;

[0020] 114: gate dielectric layer;

[0021] 116: gate electrode layer;

[0022] 118: protective layer;

[0023] 120: wire contact structure;

[0024] 121, 164, 164 1 , 164 2 , 164 3 : contact plug;

[0025] 122, 140, 142, 144: spacers;

[0026] 124, 125, 128: insulating layer;

[0027] 126, 126 1 , 126 2 :Wire structure;

[0028] 130: first conductive layer;

[0029] 132: second conductive layer;

[0030] 134: a third conductive layer;

[0031] 136: protective layer;

[0032] 138, 138', 138 1 ', 138 2 ': spacer structure;

[0033] 146: dielectric strip;

[0034] 148: Open your mouth;

[0035] 150, 152, 154, 156: conductive material;

[0036] 158: groove;

[0037] 160, 168: patterned mask layer;

[0038] 162: conductive strip;

[0039] 166: filling layer;

[0040] 172, 172 1 , 172 2 , 172 3 : Conductive pad;

[0041] 174: gap;

[0042] 176: protective layer;

[0043] 178: air gap;

[0044] 180: dielectric structure;

[0045] 182: capacitor;

[0046] 184: lower electrode layer;

[0047] 186: capacitor dielectric layer;

[0048] 188: upper electrode layer;

[0049] 200, 300: semiconductor memory structure;

[0050] D1: first direction;

[0051] D2: second direction;

[0052] D3: Third direction;

[0053] P1, P2: Pitch. DETAILED DESCRIPTION

[0054] The present invention is described more fully below with reference to the drawings of the embodiments of the present invention. However, the present invention may be implemented in various different embodiments and should not be limited to the embodiments described herein. The thickness of the layers and regions in the drawings may be exaggerated for clarity, and the same or similar reference numbers in the drawings represent the same or similar elements.

[0055] Figures 1A to 1J-4 FIG. 1 is a schematic diagram showing different stages of forming a semiconductor memory structure 100 according to some embodiments of the present invention. Figures 1A to 1J 1 is a schematic plan view of a semiconductor memory structure 100 at different stages, wherein reference directions are indicated for ease of explanation. The first direction D1 is a channel extension direction, the second direction D2 is a gate extension direction (or a word line extension direction), and the third direction D3 is a bit line extension direction. The first direction D1 is not perpendicular to the second direction D2, and the second direction D2 is approximately perpendicular to the third direction D3.

[0056] Figures 1A to 1J Reference cross sections are also indicated. Cross section AA is parallel to the gate extension direction (i.e., the second direction D2) and passes through the surface between the gate structures; cross section BB is parallel to the gate extension direction and passes through the surface of the gate structure; cross section CC is parallel to the channel extension direction (i.e., the first direction D1) and passes through the conductive strip (shown in FIG. Figure 1C ) plane; cross section DD is parallel to the channel extension direction and passes through the plane between adjacent conductive strips.

[0057] Figure 1A-1 to Figure 1J-1 Display along Figures 1A to 1J A schematic cross-sectional view of the semiconductor memory structure 100 captured along the cross-sectional plane AA; Figure 1A-2 to Figure 1J-2 Display along Figures 1A to 1J A schematic cross-sectional view of the semiconductor memory structure 100 captured along the cross-sectional plane BB; Figures 1A-3 to 1J-3 Display along Figures 1A to 1J A schematic cross-sectional view of the semiconductor memory structure 100 captured by the cross-section CC; Figure 1C-4 to Figure 1J-4 Display along Figure 1C to Figure 1J Schematic cross-sectional view of the semiconductor memory structure 100 captured along the cross-sectional plane DD.

[0058] Provide a semiconductor memory structure 100, such as Figure 1A , Figure 1A-1 , Figure 1A-2 and Figure 1A-3 The semiconductor memory structure 100 includes a semiconductor substrate 102, an isolation structure 106, a gate structure 112, a wire contact structure 120, a wire structure 126, a spacer structure 138, and a dielectric strip 146. For the sake of clarity, some components are not shown. Figure 1A , but can be seen in Figure 1A-1 , Figure 1A-2 and Figure 1A-3 .

[0059] The semiconductor substrate 102 includes an active region 104, an isolation region, and a truncation region. The active region 104 is a semiconductor block extending along a first direction D1. The isolation region extends along the first direction D1, thereby dividing the semiconductor substrate 102 into a plurality of semiconductor strips (not shown). The truncation region is arranged corresponding to the semiconductor strips, and truncates the semiconductor strips into a plurality of active regions 104. In this way, each active region 104 is defined by two isolation regions and two truncation regions. In the second direction D2, adjacent truncation regions are misaligned or non-overlapping.

[0060] An isolation structure 106 is formed in the isolation region and the truncation region of the semiconductor substrate 102. The isolation structure 106 extends downward from the upper surface of the semiconductor substrate 102 for a distance and surrounds and electrically isolates the active region 104. The isolation structure 106 may include a liner 108 and an insulating material 110. The liner 108 is lined between the insulating material 110 and the active region 104. The liner 108 is formed of a dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and / or a combination thereof. The insulating material 110 is formed of a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO), and / or a combination thereof.

[0061] A gate structure 112 is formed in the semiconductor substrate 102. The gate structure 112 extends along the second direction D2 and is arranged in parallel in the third direction D3. The gate structure 112 serves as a word line of the resulting semiconductor memory device, also known as a buried word line. The gate structure 112 extends alternately through the active region 104 and the isolation structure 106. Two gate structures 112 extend through a single active region 104, and two gate structures 112 extend through the truncation regions on both sides of the active region 104. The gate structure 112 includes a gate dielectric layer 114, a gate electrode layer 116, and a protection layer 118. The gate dielectric layer 114 is lined between the gate electrode layer 116 and the active region 104 (or the isolation structure 106), and is lined between the protection layer 118 and the active region 104 (or the isolation structure 106).

[0062] In some embodiments, the gate dielectric layer 114 is formed of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), a high-k dielectric material, and / or a combination thereof. In some embodiments, the gate electrode layer 116 is formed of a conductive material, such as a semiconductor material (e.g., polysilicon), a metal material (e.g., tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), or ruthenium (Ru)), or a metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN)), and / or a combination thereof. In some embodiments, the protective layer 118 is formed of a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO), and / or a combination thereof.

[0063] A conductive contact structure 120 is formed on the active region 104. The conductive contact structure 120 includes a contact plug 121 and a spacer 122 surrounding the contact plug 121. The contact plug 121 corresponds to and contacts the central portion of the active region 104. The central portion of the active region 104 is a source region or a drain region between adjacent gate structures 112. The spacer 122 can be configured to separate a contact plug formed subsequently from the contact plug 121, and to separate a contact plug formed subsequently from the central portion of the active region 104.

[0064] In some embodiments, the contact plug 121 is formed of a conductive material, such as a semiconductor material (e.g., polysilicon), a metal material (e.g., tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), or ruthenium (Ru)), or a metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN)), and / or a combination thereof. In some embodiments, the spacer 122 is formed of a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO), and / or a combination thereof.

[0065] A conductive line structure 126 is formed on the semiconductor substrate 102. The conductive line structure 126 extends along the third direction D3 and is arranged in parallel in the second direction D2. The conductive line structure 126 serves as a bit line of the obtained semiconductor memory device. The conductive line structure 126 includes an insulating layer 128, a first conductive layer 130 on the insulating layer 128, a second conductive layer 132 on the first conductive layer 130, a third conductive layer 134 on the second conductive layer 132, and a protective layer 136 on the third conductive layer 134.

[0066] In some embodiments, the insulating layer 128 is formed of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and / or a combination thereof. In some embodiments, the first conductive layer 130 is formed of polysilicon. In some embodiments, the second conductive layer 132 is formed of a barrier material, such as a metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN). A metal silicide may be formed between the first conductive layer 130 and the second conductive layer 132. In some embodiments, the third conductive layer 134 is formed of a metal material, such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), or ruthenium (Ru). In some embodiments, the protective layer 136 is formed of a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO), and / or a combination thereof.

[0067] The conductive line structure 126 is electrically connected to the central portion of the active region 104 through the contact plug 121 of the conductive line contact structure 120. For example, the portion of the insulating layer 128 directly above the contact plug 121 is removed so that the first conductive layer 130 of the conductive line structure 126 contacts the contact plug 121. In addition, the insulating layer 124 and the insulating layer 125 may be disposed between the conductive line structure 126 and the semiconductor substrate 102 (or the isolation structure 106, or the gate structure 112) so that the conductive material of the conductive line structure 126 is away from some other conductive components of the semiconductor memory structure 100. In some embodiments, the insulating layer 124 and the insulating layer 125 are formed of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and / or a combination thereof.

[0068] A spacer structure 138 is formed along the opposite sidewalls of the conductive line structure 126. The spacer structure 138 is configured to separate the contact plug formed subsequently from the conductive line structure 126. The spacer structure 138 includes a spacer 140, a spacer 142 formed along the sidewall of the spacer 140, and a spacer 144 formed along the sidewall of the spacer 142. In some embodiments, the spacer 140, the spacer 142, and the spacer 144 are formed of a dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and / or a combination of the foregoing. For example, the spacer 140 and the spacer 144 can be formed of the same material, such as silicon nitride. The spacer 142 can be formed of a material different from the spacer 140 and the spacer 144, such as silicon oxide.

[0069] A dielectric strip 146 is formed on the semiconductor substrate 102. The dielectric strip 146 extends along the second direction D2 and is arranged in parallel in the third direction D3. The dielectric strip 146 corresponds to and covers the gate structure 112. The dielectric strip 146 extends across the conductive line structure 126 and the spacer structure 138. The top surface of the portion of the conductive line structure 126 and the spacer structure 138 covered by the dielectric strip 146 may be lower than the top surface of the portion of the conductive line structure 126 and the spacer structure 138 exposed from the dielectric strip 146. In some embodiments, the dielectric strip 146 is formed of a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO), and / or a combination thereof.

[0070] The adjacent dielectric strips 146 and the adjacent conductive line structures 126 define an opening 148. The end portion of the active region 104 is exposed from the opening 148. The end portion of the active region 104 is a source region or a drain region outside the adjacent gate structure 112.

[0071] A plurality of conductive materials 150, 152, 154 and 156 are sequentially formed on the semiconductor substrate 102. Figure 1B , Figure 1B-1 , Figure 1B-2 and Figure 1B-3 148. Conductive material 150 fills the lower portion of opening 148. Conductive material 152 is formed on the top surface of conductive material 150. Conductive material 154 is formed along the top surface of conductive material 152 and the sidewalls of the upper portion of opening 148. Conductive material 154 is also formed along the top surface of spacer structure 138, the top surface of conductive line structure 126, and the top surface of dielectric strip 146. Conductive material 156 is formed on conductive material 154 and overfills the upper portion of opening 148.

[0072] In some embodiments, the conductive material 150 is a semiconductor layer, such as formed of polysilicon. In some embodiments, the conductive material 152 is formed of a metal silicide, such as cobalt silicide (CoSi), nickel silicide (NiSi), titanium silicide (TiSi), tungsten silicide (WSi). In some embodiments, the conductive material 154 is a barrier layer, such as formed of a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). In some embodiments, the conductive material 156 is a metal layer, such as tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta).

[0073] A first patterning process is performed on the conductive materials 154 and 156 to form a plurality of conductive strips 162, such as Figure 1C , 1C-1 , Figure 1C-2 , Figure 1C-3 and Figure 1C-4 The first patterning process includes forming a patterned mask layer 160 on the conductive material 156. The patterned mask layer 160 is a patterned photoresist layer formed by a photolithography process, or a patterned hard mask layer formed by depositing a dielectric material and subsequently performing photolithography and etching processes.

[0074] The first patterning process further includes etching back the portions of the conductive material 154 and the conductive material 156 not covered by the patterned mask layer 160 to form conductive strips 162 and trenches 158 between the conductive strips 162. The etching process also etches back the portions of the spacer structure 138, the conductive line structure 126, and the dielectric strips 146 not covered by the patterned mask layer 160.

[0075] The conductive strips 162 extend along the first direction D1 and are arranged in parallel in the second direction D2. The conductive strips 162 are located on the top surface of the conductive line structure 126 and the top surface of the dielectric strips 146, and extend across the conductive line structure 126 and the dielectric strips 146. In the second direction D2, the conductive strips 162 and the conductive line structure 126 may have the same pitch P1.

[0076] Conductive materials 150, 152, 154 and 156 are formed in opening 148 ( Figure 1A , Figure 1A-1 and Figure 1A-3 ) can be used as contact plugs 164 of the semiconductor memory structure 100. The contact plugs 164 correspond to and contact the end portions of the active regions 104. Each contact plug 164 is at least partially covered by the conductive strips 162.

[0077] After forming the conductive strips 162, the patterned mask layer 160 is removed. Next, a filling layer 166 is formed on the semiconductor structure 100. Figure 1D-1 , Figure 1D-2 , Figure 1D-3 and Figure 1D-4 For the sake of clarity, Figure 1D Filling layer 166 is not shown. Filling layer 166 fills trench 158 and covers conductive strip 162. Filling layer 166 can provide a flat upper surface for subsequent photolithography. In some embodiments, filling layer 166 is formed of a dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and / or a combination thereof. In some embodiments, filling layer 166 and spacer 142 are formed of the same material, such as silicon oxide. For illustration, Figure 1D-1 An interface between the fill layer 166 and the spacer 142 is shown, but there may be no interface between the two.

[0078] A second patterning process is performed on the conductive material 154 and the conductive material 156. The second patterning process includes forming a patterned mask layer 168 on the filling layer 166, such as Figure 1E , Figure 1E-1 , Figure 1E-2 , Figure 1E-3 and Figure 1E-4 As shown. The patterned mask layer 168 is a patterned photoresist layer formed by a photolithography process, or a patterned hard mask layer formed by depositing a dielectric material and subsequently performing a photolithography and etching process. Alternatively, the patterned mask layer 168 is formed by spin-on-coating carbon. The patterned mask layer 168 extends along the second direction D2 and is arranged in parallel in the third direction D3. The patterned mask layer 168 is staggered (for example, not overlapping) with the dielectric strips 146 and covers the contact plugs 164. The patterned mask layer 168 may also not cover the barrier layer 154 along the sidewalls of the dielectric strips 146. In the third direction D3, the patterned mask layer 168 may have the same pitch P2 as the dielectric strips 146.

[0079] The second patterning process further includes removing the portion of the filling layer 166 not covered by the patterned mask layer 168 by an etching process. The etching process then removes the portion of the conductive strip 162 not covered by the patterned mask layer 168, so that the conductive strip 162 including the conductive materials 154 and 156 is cut into a plurality of conductive pads 172, such as Figure 1F , Figure 1F-1 , Figure 1F-2 , Figure 1F-3 and Figure 1F-4 For the sake of clarity, Figure 1F The filling layer 166 and the patterned mask layer 168 are not shown. The etching process also recesses the portions of the dielectric strips 146 not covered by the patterned mask layer 168, so that the etched conductive material 156 protrudes from between the dielectric strips 146. In addition, the etching process also recesses the conductive material 154, so that the etched conductive material 156 protrudes from the conductive material 154, as shown in FIG. Figure 1F-3 shown.

[0080] Each conductive pad 172 corresponds to and partially covers each contact plug 164. Some conductive pads 172 partially cover both the conductive line structure 126 and the spacer structure 138. Figure 1F Some conductive pads 172 are shown not covering both the conductive structure 126 and the spacer structure 138 , but in some embodiments, these conductive pads 172 may cover the spacer structure 138 but not the conductive structure 126 , which will be described in detail later. In some embodiments, all conductive pads 172 do not cover the dielectric strips 146 .

[0081] The semiconductor structure 100 is etched to remove the patterned mask layer 168. Figure 1G-1 , Figure 1G-2 , Figure 1G-3 and Figure 1G-4 Next, the semiconductor structure 100 is etched to remove the filling layer 166 and the spacer 142 of the spacer structure 138, as shown in FIG. Figure 1H-1 , Figure 1H-2 , Figure 1H-3 and Figure 1H-4 As shown. In some embodiments, since the filling layer 166 and the spacer 142 are formed of the same material, the filling layer 166 and the spacer 142 can be removed continuously in the same etching equipment. The etching process is a wet etching process. The spacer 142 is removed so that the gap 174 is formed between the spacer 140 and the spacer 144. For the sake of clarity, Figure 1H The gap 174 is not shown. The bottom surface of the gap may be at a level lower than the first conductive layer 130 and between the bottom surface and the top surface of the conductive material 150.

[0082] A protection layer 176 is formed on the semiconductor structure 100, such as Figure 1I-1 , Figure 1I-2 , Figure 1I-3 and Figure 1I-4 For the sake of clarity, Fig. 1I Protection layer 176 is not shown. Protection layer 176 surrounds and covers conductive pad 172. Protection layer 176 also covers spacer structure 138 and seals gap 174. Sealed gap 174 forms air gap 178. Spacer structure including air gap 178 is labeled spacer structure 138'.

[0083] Since the spacer structure 138' includes the air gap 178, the capacitance of the spacer structure 138' as a whole can be reduced, thereby reducing the parasitic capacitance between the contact plug 164 and the conductive line structure 126. Therefore, the performance of the resulting semiconductor memory device is improved.

[0084] A dielectric structure 180 is formed on the semiconductor memory structure 100, and a capacitor 182 is formed in the dielectric structure 180. Figure 1J , Figure 1J-1 , Figure 1J-2 , Figure 1J-3 and Figure 1J-4As shown. The capacitor 182 passes through the dielectric structure 180 and the protection layer 176 to fall on the conductive pad 172. In some embodiments, the dielectric structure 180 may include a plurality of dielectric materials, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and / or a combination thereof. The capacitor 182 may include a lower electrode layer 184 contacting the conductive pad 172, a capacitor dielectric layer 186 located on the lower electrode layer 184, and an upper electrode layer 188 located on the capacitor dielectric layer 186. The lower electrode layer 184 of the capacitor 182 is electrically coupled to the end portion of the active region 104 through the conductive pad 172 and the contact plug 164.

[0085] Additional components may be formed on the semiconductor memory structure, such as interconnect structures, peripheral circuits, or other suitable components, to produce a semiconductor memory device. In some embodiments, the semiconductor memory device is a dynamic random access memory.

[0086] According to an embodiment of the present invention, the air gap 178 is formed by continuously removing the filling layer 166 and the spacer 142 in the same etching equipment, which can save an etching process and the time of transferring the semiconductor memory structure, so as to improve the manufacturing capacity of the semiconductor memory device. In addition, the overall time of the etching process can be reduced, thereby reducing the negative impact of the etching process on the conductive material of the conductive pad 172 and / or the contact plug 164. In addition, it can also prevent the conductive material from being exposed to an oxygen-containing environment due to the semiconductor memory structure being transferred between different etching equipment.

[0087] Figure 2 FIG. 2 is a schematic plan view of a semiconductor memory structure 200 according to some embodiments of the present invention. Figures 1A to 1J-4 The materials, processes and configurations described in the embodiments can be implemented in Figure 2 Embodiment of the invention. Figure 2-1 Display along Figure 2 A schematic cross-sectional view of the semiconductor memory structure 200 taken along the cross-sectional plane A1-A1. Figure 2 The semiconductor memory structure 200 and Fig. 1I The semiconductor memory structure 100 is similar to that of FIG. Figure 2 The spacer 140 and the spacer 144 of the spacer structure 138 ′ and the air gap 178 inserted therebetween are further illustrated to illustrate the arrangement of the conducting pad 172 and the spacer structure 138 ′. Figure 2 Display wire structure 126 1 and conductor structure 126 2 , and are respectively adjacent to the conductor structure 126 1 and conductor structure 126 2 Spacer structure 138 1 ' and spacer structure 138 2 '. Figure 2 Also shown is the spacer structure 138 1 'With spacer structure 138 2 'Conductive pad 172 between 1 , conductive pad 172 2 and conductive pad 172 3 , and are respectively disposed on the conductive pad 172 1 , conductive pad 172 2 and conductive pad 172 3 The contact plug 164 1 , contact plug 164 2 and contact plug 164 3 .

[0088] Conductive pad 172 1 , conductive pad 172 2 and conductive pad 172 3 The contact plugs 164 are arranged in sequence in the direction opposite to the first direction D1. 1 , contact plug 164 2 and contact plug 164 3 The conductive pads 172 are arranged in sequence in the third direction D3. 2 With the contact plug 164 2 The overlapping area between the conductive pads 172 is larger than 1 With the contact plug 164 1 The overlapping area between them is larger than the conductive pad 172 3 With the contact plug 164 3 The overlapping area between .

[0089] Conductive pad 172 1 Partially covered conductor structure 126 1 and a spacer structure 138 1 ' spacer 140 and spacer 144 and air gap 178. Conductive pad 172 1 Uncovered conductor structure 126 2 and spacer structure 138 2 '. Conductive pad 172 2 Partially covering the spacer structure 138 1 'The spacer 144 and the spacer structure 138 2 ' spacer 144. Conductive pad 172 2 Uncovered conductor structure 126 1 and conductor structure 126 2 . Conductive pad 172 2 The spacer structure 138 is not covered. 1 ' and spacer structure 138 2' spacer 140 and air gap 178. Conductive pad 172 3 Covering conductor structure 126 2 and a spacer structure 138 2 ' spacer 140 and spacer 144 and air gap 178. Conductive pad 172 3 Uncovered conductor structure 126 1 and spacer structure 138 1 '.

[0090] Figure 3 is a schematic plan view of a semiconductor memory structure 300 according to some embodiments of the present invention. Figure 3-1 Display along Figure 3 A schematic cross-sectional view of the semiconductor memory structure 300 taken along the cross-sectional plane A1-A1. Figure 3 The semiconductor memory structure 300 and Figure 2 The semiconductor memory structure 200 is similar to Figure 3 The spacers 144 and air gaps 178 are shown to have annular profiles.

[0091] After forming dielectric strip 146, spacers 142 and 144 ( Figure 1A-1 ) is formed in the opening 148 defined by the dielectric strip 146 and the conductive line structure 126. Figure 3 As shown, the spacers 144 and the air gaps 178 (formed by removing the spacers 142) extend continuously along the sidewalls of the dielectric strips 146 and the sidewalls of the spacers 140, and the spacers 144 and the air gaps 178 have an annular profile. 2 The spacers 144 along the dielectric strips 146 and the air gaps 178 are also partially covered.

[0092] According to the above, the embodiment of the present invention provides a spacer structure including an air gap, which is formed by continuously removing a filling layer and a spacer. Therefore, the manufacturing capacity of a semiconductor memory device can be improved. In addition, the negative impact of the etching process on the conductive material is reduced, and the conductive material is prevented from being exposed to an oxygen-containing environment.

[0093] Although the present invention is disclosed in the above embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor memory structure, It is characterized in that include: forming a plurality of conductive line structures on a semiconductor substrate; forming a plurality of spacer structures along the sidewalls of the conductive line structure, wherein each of the spacer structures comprises a first spacer; forming a plurality of dielectric strips across the conductive line structure, wherein at least one of the dielectric strips includes a portion that extends continuously over at least two of the conductive line structures; forming a plurality of conductive strips extending above the dielectric strips and the conductive line structure; Performing a patterning process on the conductive strip to form a plurality of conductive pads; as well as The first spacer of each of the spacer structures is removed to form a gap in each of the spacer structures.

2. The method for forming a semiconductor memory structure according to claim 1, It is characterized in that The patterning process includes: forming a filling layer on the conductive strip; forming a patterned mask layer on the filling layer; and The filling layer, the conductive strips and the dielectric strips that are not covered by the patterned mask layer are etched to form the conductive pads.

3. The method for forming a semiconductor memory structure according to claim 2, It is characterized in that Also includes: removing the patterned mask layer; as well as The filling layer is removed, wherein the filling layer and the first spacer are removed continuously in the same etching equipment.

4. The method for forming a semiconductor memory structure according to claim 1, It is characterized in that The conductive strips extend along a first direction, the dielectric strips extend along a second direction, and the conductive wire structure extends along a third direction, the second direction is perpendicular to the third direction, and the first direction is not perpendicular to the second direction and the third direction.

5. The method for forming a semiconductor memory structure according to claim 1, It is characterized in that The pitch between the conductive strips is equal to the pitch between the conductive line structures.

6. The method for forming a semiconductor memory structure according to claim 1, It is characterized in that Each of the spacer structures further includes: a second spacer and a third spacer between which the first spacer is inserted, wherein a material of the first spacer is different from a material of the second spacer and a material of the third spacer.

7. The method for forming a semiconductor memory structure according to claim 1, It is characterized in that Also includes: A plurality of contact plugs are formed in a plurality of openings defined by the conductive line structure and the dielectric strip, wherein the conductive pads are correspondingly formed on the contact plugs.

8. The method for forming a semiconductor memory structure according to claim 1, It is characterized in that Also includes: A protection layer is formed to surround the conductive pad and seal the gap, thereby forming a plurality of air gaps.

9. A semiconductor memory structure, It is characterized in that include: A first conductive line structure and a second conductive line structure are disposed on a semiconductor substrate; a first spacer structure, adjacent to a first side of the first conductive line structure; a second spacer structure adjacent to a second side of the second conductive line structure, wherein each of the first spacer structure and the second spacer structure comprises an air gap; a first dielectric strip and a second dielectric strip extending across the first conductive line structure and the second conductive line structure, wherein each of the first dielectric strip and the second dielectric strip includes a portion extending continuously over the first conductive line structure and the second conductive line structure; a first contact plug disposed in a space defined by the first conductive line structure, the second conductive line structure, the first dielectric strip, and the second dielectric strip; as well as A first conducting pad is disposed on the first contact plug, wherein the first conducting pad partially covers both the first spacer structure and the second spacer.

10. The semiconductor memory structure according to claim 9, It is characterized in that Also includes: a third dielectric strip extending across the first conductive line structure and the second conductive line structure; a second contact plug disposed in a space defined by the first conductive line structure, the second conductive line structure, the first dielectric strip, and the third dielectric strip; as well as A second conducting pad is disposed on the second contact plug, wherein a first overlapping area between the first conducting pad and the first contact plug is greater than a second overlapping area between the second conducting pad and the second contact plug.

11. The semiconductor memory structure according to claim 9, It is characterized in that The first conducting pad does not overlap both the first conductive line structure and the second conductive line structure.

12. The semiconductor memory structure according to claim 9, It is characterized in that The first conducting pad does not overlap the first dielectric strip and the second dielectric strip.

13. The semiconductor memory structure according to claim 9, It is characterized in that The first conductive pad partially overlaps the air gap of the first spacer structure and the air gap of the second spacer.

14. The semiconductor memory structure according to claim 9, It is characterized in that The air gap of the first spacer structure is connected to the air gap of the second spacer.

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