Alignment mark and method for forming the same

Abstract

An alignment mark and a method for forming the same, wherein the alignment mark comprises: a substrate, the substrate comprising an alignment region and a chip region, the alignment region having a mark origin; a first layer to be processed located on the alignment region; and a plurality of mutually separate mark openings located within the first layer to be processed, each mark opening having a corresponding projection pattern on the alignment region, the projection patterns being distributed with the mark origin as the center of a circle. By using the plurality of mutually separate mark openings located within the first layer to be processed, overlap between the mark openings is avoided, thereby avoiding etching penetration caused by repeated etching of the same position within the alignment region, thereby avoiding etching environment pollution and the generation of residues caused by etching penetration. Furthermore, the effect of residues in the alignment region entering the chip region and affecting the device structure is avoided, effectively improving the performance of the resulting semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an alignment mark and a forming method thereof. Background Art

[0002] Photolithography is a crucial technology in semiconductor manufacturing, enabling the transfer of patterns from a mask onto the surface of a silicon wafer, creating semiconductor products that meet design requirements. The photolithography process begins with an exposure step, where light passes through the translucent or reflective areas of the mask onto a photoresist-coated silicon wafer, reacting photochemically with the photoresist. Next, a development step utilizes the solubility of the developer in the photosensitive and unsensitive photoresists to form a photoresist pattern, enabling the transfer of the mask pattern. Finally, an etching step involves etching the silicon wafer based on the photoresist pattern, further transferring the mask pattern to the wafer.

[0003] Before photolithography, the wafer must be aligned so that the pattern can be accurately transferred to the photoresist layer of the wafer. There are two types of alignment marks in the prior art: zero-layer mark and scribe line mark.

[0004] However, the alignment marks formed by the prior art still have many problems. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide an alignment mark and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

[0006] To solve the above problems, the present invention provides an alignment mark, comprising: a substrate, the substrate comprising an alignment area and a chip area, the alignment area being located at the intersection of a horizontal cut and a vertical cut, the alignment area having a mark origin; a first layer to be processed located on the alignment area; and a plurality of mutually separate mark openings located in the first layer to be processed, each of the mark openings having a corresponding projection pattern on the alignment area, and the plurality of projection patterns being distributed with the mark origin as the center of a circle.

[0007] Optionally, the method further includes: a second layer to be processed located on the chip area.

[0008] Optionally, it further includes a plurality of device openings located in the second layer to be processed.

[0009] Optionally, the projection figure is a rectangle, and each projection figure has a different extension direction. In each extension direction, there is an origin spacing dimension between the midpoint of the edge line of each projection figure close to the mark origin and the mark origin, and each origin spacing dimension is equal.

[0010] Optionally, the origin spacing size range is less than 2 microns.

[0011] Optionally, in a direction perpendicular to the extension direction of each projection pattern, each projection pattern has a width dimension, and each width dimension is equal.

[0012] Optionally, the width dimension range is greater than 0.2 microns.

[0013] Optionally, the range of the closest vertex distances between adjacent projection patterns is greater than 0.15 microns.

[0014] Optionally, the angle between adjacent projection patterns is less than 90 degrees.

[0015] Optionally, the substrate further includes: a base and a layer to be etched located on the base, and the first layer to be processed is located on the layer to be etched.

[0016] Optionally, the layer to be etched includes: a device layer and a hard mask layer located on the device layer, and the first layer to be processed is located on the hard mask layer.

[0017] Optionally, it also includes: a first stop layer, the first stop layer is located between the substrate and the device layer; a second stop layer, the second stop layer is located between the device layer and the hard mask layer; and a third stop layer, the third stop layer is located between the hard mask layer and the first layer to be processed.

[0018] Optionally, the plurality of projection graphics are distributed at equal intervals with the mark origin as the center.

[0019] Correspondingly, the technical solution of the present invention also provides a method for forming an alignment mark, including: providing a substrate, the substrate including an alignment area and a chip area, the alignment area being located at the intersection of the horizontal cutting and the vertical cutting, and the alignment area having a mark origin; forming a first layer to be processed on the alignment area; using several times of graphical processing to form several separate mark openings in the first layer to be processed, each of the mark openings having a corresponding projection pattern on the alignment area, and several of the projection patterns are distributed with the mark origin as the center of the circle.

[0020] Optionally, the method of graphical processing includes: forming a graphical layer on the first layer to be processed, the graphical layer exposing a portion of the top surface of the first layer to be processed; etching the first layer to be processed using the graphical layer as a mask to form the marking opening in the first layer to be processed.

[0021] Optionally, before forming the patterned layer, the method further includes: forming a sacrificial layer on the first layer to be processed and an anti-reflection layer on the sacrificial layer, wherein the patterned layer is located on the anti-reflection layer.

[0022] Optionally, in the process of forming the first layer to be processed on the alignment area, the method further includes: forming a second layer to be processed on the chip area.

[0023] Optionally, in the process of forming the plurality of mark openings, the method further includes: forming a plurality of device openings in the second layer to be processed.

[0024] Optionally, the projection figure is a rectangle, and the extension direction of each projection figure is different. In the extension direction of each projection figure, there is an origin spacing dimension between the midpoint of the edge line of each projection figure close to the marked origin and the marked origin, and the origin spacing dimensions are equal.

[0025] Optionally, the origin spacing size range is less than 2 microns.

[0026] Optionally, each of the marking openings has a width dimension in a direction perpendicular to the extension direction of the respective projection patterns, and the width dimensions are equal.

[0027] Optionally, the width dimension range is greater than 0.2 microns.

[0028] Optionally, the range of the closest vertex distances between adjacent projection patterns is greater than 0.15 microns.

[0029] Optionally, the angle between adjacent projection patterns is less than 90 degrees.

[0030] Optionally, the substrate further includes: a base and a layer to be etched located on the base, and the first layer to be processed is located on the layer to be etched.

[0031] Optionally, the layer to be etched includes: a device layer and a hard mask layer located on the device layer, and the first layer to be processed is located on the hard mask layer.

[0032] Optionally, it also includes: a first stop layer, the first stop layer is located between the substrate and the device layer; a second stop layer, the second stop layer is located between the device layer and the hard mask layer; and a third stop layer, the third stop layer is located between the hard mask layer and the first layer to be processed.

[0033] Optionally, after forming the device openings, the method further includes: forming a first sidewall spacer on the sidewall of each device opening.

[0034] Optionally, during the process of forming the first sidewalls, the method further includes: forming second sidewalls on the sidewalls of each of the marking openings.

[0035] Optionally, after forming the first sidewall spacer and the second sidewall spacer, the method further includes: removing the first to-be-processed layer; and etching a substrate using the first sidewall spacer and the second sidewall spacer as masks to form a patterned opening in the substrate.

[0036] Optionally, the plurality of projection graphics are distributed at equal intervals with the mark origin as the center.

[0037] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0038] The alignment mark of the present invention utilizes multiple, discrete mark openings within the first processed layer to prevent overlap. This prevents etch-through from repeated etching of the same location within the alignment region, thereby avoiding environmental contamination and residue generation caused by etch-through. Furthermore, it prevents residue from the alignment region from entering the chip region and impacting the device structure, effectively improving the performance of the resulting semiconductor structure.

[0039] In the formation method of the technical solution of the present invention, multiple patterning processes are performed to form a plurality of discrete marking openings in the first processed layer, thereby preventing overlap between the marking openings. This prevents etching through the same location within the alignment region due to repeated etching, thereby avoiding etching environmental pollution and the generation of residues caused by etching through. Furthermore, it prevents residues in the alignment region from entering the chip region and affecting the device structure, effectively improving the performance of the resulting semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figures 1 to 3 It is a schematic diagram of the structure of an alignment mark;

[0041] Figures 4 to 16 1 is a schematic structural diagram of each step of an embodiment of a method for forming an alignment mark of the present invention. DETAILED DESCRIPTION

[0042] As described in the background art, however, the alignment marks formed by the prior art still have many problems, which will be described in detail below with reference to the accompanying drawings.

[0043] Please refer to Figure 1, providing a substrate 100, wherein the substrate 100 includes a marking area, and the substrate has a first layer to be processed 101; forming a first sacrificial layer 102 on the first layer to be processed 101; forming a first patterned layer 103 on the first sacrificial layer 102, wherein the first patterned layer 103 exposes a portion of the top surface of the first sacrificial layer 102; etching the first sacrificial layer 102 and the first layer to be processed 101 using the first patterned layer 103 as a mask, and forming a first marking opening 104 in the first layer to be processed 101.

[0044] Please refer to Figure 2 After forming the first mark opening 104, the first patterned layer 103 and the first sacrificial layer 102 are removed; a second sacrificial layer 105 is formed on the first layer to be processed 101, and the second sacrificial layer 105 fills the first mark opening 104; a second patterned layer 106 is formed on the second sacrificial layer 105, and the second patterned layer 106 exposes a portion of the top surface of the second sacrificial layer 105; the second sacrificial layer 105 and the first layer to be processed 101 are etched using the second patterned layer 106 as a mask to form a second mark opening 107 in the first layer to be processed 101, and the first mark opening 104 and the second mark opening 107 overlap.

[0045] Please refer to Figure 3 After forming the second mark opening 107 , the second patterned layer 106 and the second sacrificial layer 105 are removed.

[0046] In this embodiment, the first mark opening 104 and the second mark opening 107 serve as alignment marks during the photolithography process to facilitate device dimension measurement during the same etching process. However, in this embodiment, since the first mark opening 104 and the second mark opening 107 overlap within the first layer to be processed, the first mark opening 104 and the second mark opening 107 are both formed at the same position on the first layer to be processed 101, making it easy to etch through the first layer to be processed 101. This causes the etching solution or etching gas used to etch the second mark opening 107 to react with the hard mask layer beneath the first layer to be processed, easily leaving residual substances in the hard mask layer. These residual substances can easily enter the chip area and affect the device structure. In addition, the gases generated after the reaction also pollute the etching environment.

[0047] Based on this, the present invention provides an alignment mark and a method for forming the same. By using a plurality of discrete mark openings within the first layer to be processed, the mark openings are prevented from overlapping, thus avoiding environmental contamination and residue generation caused by etching penetration. Furthermore, this method prevents residue in the alignment area from entering the chip region and impacting the device structure, effectively improving the performance of the resulting semiconductor structure.

[0048] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0049] Figures 4 to 16 It is a structural schematic diagram of a formation process of an alignment mark according to an embodiment of the present invention.

[0050] Please refer to Figure 4 and Figure 5 , Figure 5 for Figure 4 Schematic diagram of the cross section along line AA, Figure 4 for Figure 5 A top view of a substrate is provided, wherein the substrate includes an alignment area I and a chip area II, the alignment area I is located at the intersection of the horizontal cutting and the vertical cutting, and the alignment area I has a marking origin O.

[0051] In this embodiment, the alignment region I is used to form corresponding alignment marks during each photolithography process, providing a measurement reference for the device structures formed in the chip region II. The chip region II is used to form device structures with actual functions. While the device structures are formed in the chip region II, corresponding device structures are also formed in the alignment region I due to the global process. However, the device structures formed in the alignment region I do not have actual functions.

[0052] In this embodiment, the number of the alignment areas I is four, each located at a corner of the chip area II.

[0053] In this embodiment, please continue to refer to Figure 4 and Figure 5 , further comprising: forming a first to-be-processed layer 203 on the alignment area I.

[0054] In this embodiment, during the process of forming the first to-be-processed layer 203 on the alignment area I, the process further includes: forming a second to-be-processed layer 212 on the chip area II.

[0055] In this embodiment, the substrate further includes: a base 200 and a layer to be etched located on the base 200 , and the first layer to be processed 203 is located on the layer to be etched.

[0056] In this embodiment, the layer to be etched includes: a device layer 201 and a hard mask layer 202 located on the device layer 201 , and the first layer to be processed 203 is located on the hard mask layer 202 .

[0057] In this embodiment, the device layer 201 is made of a low-K dielectric material.

[0058] In this embodiment, the material of the hard mask layer 202 is titanium nitride; in other embodiments, the material of the hard mask layer may also be tantalum nitride.

[0059] In this embodiment, it also includes: a first stop layer 204, the first stop layer 204 is located between the substrate 200 and the device layer 201; a second stop layer 205, the second stop layer 205 is located between the device layer 201 and the hard mask layer 202; and a third stop layer 206, the third stop layer 206 is located between the hard mask layer 202 and the first layer to be processed 203.

[0060] The first stop layer 204 , the second stop layer 205 and the third stop layer 206 function to stop each etching process on the corresponding stop layer to prevent the etching process from damaging the underlying structure.

[0061] After forming the first to-be-processed layer 203, the process further includes: forming a plurality of mutually separated marking openings in the first to-be-processed layer 203 by performing a plurality of patterning processes, each of the marking openings having a corresponding projection pattern on the alignment area I, and the plurality of projection patterns being distributed with the marking origin O as the center of the circle. For the specific process, please refer to Figures 6 to 14 .

[0062] It should be noted that in this embodiment, five marking openings are formed in the first to-be-processed layer 203, namely, a first marking opening, a second marking opening, a third marking opening, a fourth marking opening, and a fifth marking opening. The corresponding projection patterns on the alignment area I are the first projection pattern, the second projection pattern, the third projection pattern, the fourth projection pattern, and the fifth projection pattern, respectively. The corresponding patterning processes are the first patterning process, the second patterning process, the third patterning process, and the fourth patterning process, respectively. The first marking opening and the second marking opening are simultaneously formed using the first patterning process, the third marking opening is formed using the second patterning process, the fourth marking opening is formed using the third patterning process, and the fifth marking opening is formed using the fourth patterning process.

[0063] Please refer to Figures 6 to 8 , Figure 7 yes Figure 6 A schematic diagram of the enlarged structure of part A. Figure 8 yes Figure 7 In the cross-sectional diagram along line BB, a first marking opening 207 and a second marking opening 208 are formed in the first to-be-processed layer 203 on the reserved area I by adopting a first patterning process.

[0064] In this embodiment, the method for the first patterning treatment includes: forming a first patterning layer (not shown) on the first layer to be processed 203, the first patterning layer exposing a portion of the top surface of the first layer to be processed 203; etching the first layer to be processed 203 using the first patterning layer as a mask to form the first mark opening 207 and the second mark opening 208 in the first layer to be processed 203; after forming the first mark opening 207 and the second mark opening, removing the first patterning layer.

[0065] In this embodiment, the material of the first patterned layer is photoresist.

[0066] In this embodiment, before forming the first patterned layer, the method further includes: forming a first sacrificial layer on the first layer to be processed 203; forming a first anti-reflection layer (not shown) on the first sacrificial layer, and the first patterned layer is located on the first anti-reflection layer.

[0067] In this embodiment, the material of the first sacrificial layer is amorphous carbon. The first sacrificial layer is used to provide a flat top surface for etching the first to-be-processed layer 203 .

[0068] In this embodiment, the first anti-reflection layer is used to reduce light reflection during photolithography exposure, thereby improving the photolithography effect.

[0069] In this embodiment, the first marking opening 207 has a first projection pattern S1 on the reserved area I; the second marking opening 208 has a second projection pattern S2 on the reserved area.

[0070] In this embodiment, the angle between the first projection pattern S1 and the second projection pattern S2 is 90 degrees.

[0071] Please refer to Figure 9 and Figure 10 , Figure 10 yes Figure 9 In the cross-sectional diagram along line CC, a third marking opening 209 is formed in the first to-be-processed layer 203 on the reserved area I by adopting a second graphic treatment.

[0072] In this embodiment, the method for the second graphical processing includes: forming a second graphical layer (not shown) on the first layer to be processed 203, the second graphical layer exposing a portion of the top surface of the first layer to be processed 203; etching the first layer to be processed 203 using the second graphical layer as a mask to form the third mark opening 209 in the first layer to be processed 203; after forming the third mark opening 209, removing the second graphical layer.

[0073] In this embodiment, the material of the second patterned layer is photoresist.

[0074] In this embodiment, before forming the second patterned layer, it also includes: forming a second sacrificial layer on the first layer to be processed 203, the second sacrificial layer filling the first mark opening 207 and the second mark opening 208; forming a second anti-reflection layer (not shown) on the second sacrificial layer, and the second patterned layer is located on the second anti-reflection layer.

[0075] In this embodiment, the third marking opening 209 has a third projection pattern S3 on the reserved area I.

[0076] Please refer to Figure 11 and Figure 12 , Figure 12 yes Figure 11 In the cross-sectional diagram along line DD, a fourth marking opening 210 is formed in the first to-be-processed layer 203 on the reserved area I by adopting the third patterning process.

[0077] In this embodiment, the method of the third patterning treatment includes: forming a third patterning layer (not shown) on the first layer to be processed 203, wherein the third patterning layer exposes a portion of the top surface of the first layer to be processed 203; etching the first layer to be processed 203 using the third patterning layer as a mask to form the fourth mark opening 210 in the first layer to be processed 203; after forming the fourth mark opening 210, removing the third patterning layer.

[0078] In this embodiment, the material of the third patterned layer is photoresist.

[0079] In this embodiment, before forming the third patterned layer, it also includes: forming a third sacrificial layer on the first layer to be processed 203, and the third sacrificial layer fills the third marking opening 209; forming a third anti-reflection layer (not shown) on the third sacrificial layer, and the third patterned layer is located on the third anti-reflection layer.

[0080] In this embodiment, the fourth marking opening 210 has a fourth projection pattern S4 on the reserved area I.

[0081] Please refer to Figure 13 and Figure 14 , Figure 14 yes Figure 13 In the cross-sectional diagram along line EE, a fifth marking opening 211 is formed in the first to-be-processed layer 203 on the reserved area I by adopting the fourth patterning process.

[0082] In this embodiment, the method of the fourth patterning treatment includes: forming a fourth patterning layer (not shown) on the first layer to be processed 203, wherein the fourth patterning layer exposes a portion of the top surface of the first layer to be processed 203; etching the first layer to be processed 203 using the fourth patterning layer as a mask to form the fifth mark opening 211 in the first layer to be processed 203; and removing the fourth patterning layer after forming the fifth mark opening.

[0083] In this embodiment, the material of the fourth patterned layer is photoresist.

[0084] In this embodiment, before forming the fourth patterned layer, it also includes: forming a fourth sacrificial layer on the first layer to be processed 203, and the fourth sacrificial layer fills the fourth marking opening 210; forming a fourth anti-reflection layer (not shown) on the fourth sacrificial layer, and the fourth patterned layer is located on the fourth anti-reflection layer.

[0085] In this embodiment, the fifth marking opening 211 has a fifth projection pattern S5 on the reserved area.

[0086] At this point, the process of forming several marking openings in the first layer to be processed 203 is complete. By employing multiple patterning processes to form several discrete marking openings in the first layer to be processed 203, overlap between the marking openings is eliminated, preventing etch-through from repeated etching of the same location within the alignment region I. This, in turn, avoids etching environment contamination and residue generation caused by etch-through. Furthermore, this prevents residue from the alignment region I from entering the chip region II and impacting the device structure, effectively improving the performance of the resulting semiconductor structure.

[0087] In this embodiment, the projection figures are rectangles, and the extension direction of each projection figure is different, that is, the first projection figure S1, the second projection figure S2, the third projection figure S3, the fourth projection figure S4 and the fifth projection figure S5 are all rectangles, and the extension directions of the first projection figure S1, the second projection figure S2, the third projection figure S3, the fourth projection figure S4 and the fifth projection figure S5 are different.

[0088] In this embodiment, in the extension direction of each of the projection figures, there is an origin spacing dimension d1 between the midpoint O1 of the edge line of each projection figure close to the marking origin O and the marking origin O, and each of the origin spacing dimensions d1 is equal.

[0089] In this embodiment, the origin distance dimension d1 is less than 2 microns.

[0090] In this embodiment, in a direction perpendicular to the extending direction of the respective projection patterns, each of the marking openings has a width dimension d2, and the width dimensions d2 are equal.

[0091] In this embodiment, the width dimension d2 is greater than 0.2 micrometers.

[0092] In this embodiment, the range of the closest vertex distance d3 between adjacent projection patterns is greater than 0.15 micrometers.

[0093] In this embodiment, the plurality of projection patterns are equally spaced about the mark origin O. Since the angle between the first projection pattern S1 and the second projection pattern S2 is 90 degrees, the third projection pattern S3, the fourth projection pattern S4, and the fifth projection pattern S5 are all located between the first projection pattern S1 and the second projection pattern S2, and the angle between adjacent projection patterns is 22.5 degrees.

[0094] In this embodiment, the process of forming the first mark opening 207, the second mark opening 208, the third mark opening 209, the fourth mark opening 210 and the fifth mark opening 211 also includes: forming a plurality of device openings (not shown) in the second to-be-processed layer 212 on the chip region II.

[0095] Please refer to Figure 15 , Figure 15 and Figure 14 In accordance with the viewing direction, after the device opening is formed, a first sidewall spacer (not shown) is formed on the sidewall of the device opening.

[0096] In this embodiment, the process of forming the first sidewall further includes forming a second sidewall 213 on the sidewalls of the first mark opening 207 , the second mark opening 208 , the third mark opening 209 , the fourth mark opening 210 and the fifth mark opening.

[0097] In this embodiment, the method for forming the first sidewall spacer and the second sidewall spacer 213 includes: forming an initial sidewall spacer (not shown) in the device opening, the first mark opening 207, the second mark opening 208, the third mark opening 209, the fourth mark opening 210, and the fifth mark opening 211, and on the top surfaces of the first layer to be processed 203 and the second layer to be processed 212; and etching back the initial sidewall spacer until the top surfaces of the first layer to be processed 203, the second layer to be processed 212, and the third stop layer 206 are exposed, thereby forming the first sidewall spacer and the second sidewall spacer 211.

[0098] In this embodiment, the purpose of forming the first sidewall on the sidewall of the device opening is to achieve spatial frequency doubling of the lithographic pattern by using self-aligned double patterning (SADP) technology, that is, after one lithography is completed, non-lithography process steps (thin film deposition, etching, etc.) are successively used.

[0099] Please refer to Figure 16 After forming the first sidewall spacer and the second sidewall spacer 211, the first to-be-processed layer 203 and the second to-be-processed layer 212 are removed; the substrate is etched using the first sidewall spacer and the second sidewall spacer 213 as masks to form a patterned opening 214 in the substrate.

[0100] In this embodiment, the process of removing the first layer to be processed 203 and the second layer to be processed 212 is a wet etching process; in other embodiments, the process of removing the first layer to be processed and the second layer to be processed may also be a dry etching process.

[0101] In this embodiment, the process of etching the substrate using the first sidewall and the second sidewall 211 as a mask adopts a wet etching process; in other embodiments, the process of etching the substrate using the first sidewall and the second sidewall as a mask may also adopt a dry etching process.

[0102] Accordingly, an alignment mark is also provided in the embodiment of the present invention, please continue to refer to Figure 16 , comprising: a substrate, the substrate comprising an alignment area I and a chip area II, the alignment area I being located at the intersection of a horizontal cut and a vertical cut, the alignment area I having a marking origin O; a first layer to be processed 203 located on the alignment area I; a plurality of mutually discrete marking openings located in the first layer to be processed 203, each of the marking openings having a corresponding projection pattern on the alignment area I, and the plurality of projection patterns being distributed with the marking origin O as the center of a circle.

[0103] By providing a plurality of discrete marking openings within the first unprocessed layer 203, overlap between the marking openings is avoided, thereby preventing etching through the same location within the alignment region I due to repeated etching. This, in turn, avoids etching environment contamination and the generation of residues due to etching through. Furthermore, this prevents residues in the alignment region I from entering the chip region II and affecting the device structure, effectively improving the performance of the resulting semiconductor structure.

[0104] In this embodiment, the present invention further includes: a second to-be-processed layer 212 located on the chip region II.

[0105] In this embodiment, it further includes a plurality of device openings located in the second layer to be processed 212 .

[0106] In this embodiment, the projection figure is a rectangle, and each projection figure has a different extension direction. In each extension direction, each projection figure has an origin spacing dimension d1 between the midpoint O1 of the edge line close to the marking origin O and the marking origin O, and each origin spacing dimension d1 is equal.

[0107] In this embodiment, the origin distance dimension d1 is less than 2 microns.

[0108] In this embodiment, in a direction perpendicular to the extending direction of each projection pattern, each projection pattern has a width dimension d2, and each width dimension d2 is equal.

[0109] In this embodiment, the width dimension d2 is greater than 0.2 micrometers.

[0110] In this embodiment, the range of the closest vertex distance d3 between adjacent projection patterns is greater than 0.15 micrometers.

[0111] In this embodiment, the angle between adjacent projection patterns is less than 90 degrees.

[0112] In this embodiment, the substrate further includes: a base 200 and a layer to be etched located on the base 200 , and the first layer to be processed 203 is located on the layer to be etched.

[0113] In this embodiment, the layer to be etched includes: a device layer 201 and a hard mask layer 202 located on the device layer 201 , and the first layer to be processed 203 is located on the hard mask layer 202 .

[0114] In this embodiment, it also includes: a first stop layer 204, the first stop layer 203 is located between the substrate 200 and the device layer 201; a second stop layer 205, the second stop layer 204 is located between the device layer 201 and the hard mask layer 202; and a third stop layer 206, the third stop layer 206 is located between the hard mask layer 202 and the first layer to be processed 203.

[0115] In this embodiment, the plurality of projection graphics are distributed at equal intervals with the marking origin O as the center.

[0116] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. An alignment mark, characterized in that: include: A substrate, comprising an alignment area and a chip area, wherein the alignment area is located at the intersection of the transverse cut and the longitudinal cut, and has a marking origin in the alignment area; a first layer to be processed located on the alignment area; A plurality of mutually separated mark openings are located in the first layer to be processed, the etching depth of the plurality of mark openings is the same, each of the mark openings has a corresponding projection pattern on the alignment area, the projection patterns are distributed at equal intervals with the mark origin as the center of the circle, the projection patterns are distributed at equal intervals with the mark origin as the center of the circle, and the projection patterns are distributed in a circle around the center of the circle, and the angles between adjacent projection patterns are equal; wherein, The plurality of mutually separated marking openings are formed in the first layer to be processed by adopting a plurality of patterning processes.

2. The alignment mark according to claim 1, wherein Also includes: A second layer to be processed is located on the chip area.

3. The alignment mark according to claim 2, wherein: The method further includes a plurality of device openings located in the second layer to be processed.

4. The alignment mark according to claim 1, wherein The projection figures are rectangular, and each projection figure has a different extension direction. In their respective extension directions, there is an origin spacing dimension between the midpoint of the edge line of each projection figure close to the mark origin and the mark origin, and the origin spacing dimensions are equal.

5. The alignment mark according to claim 4, wherein: The origin spacing size range is less than 2 microns.

6. The alignment mark according to claim 4, wherein: In a direction perpendicular to the extending direction of each projection pattern, each projection pattern has a width dimension, and each width dimension is equal.

7. The alignment mark according to claim 6, wherein: The width dimension ranges from greater than 0.2 microns.

8. The alignment mark according to claim 4, wherein: The range of the closest vertex distances between adjacent projection patterns is greater than 0.15 microns.

9. The alignment mark according to claim 1, wherein: The angle between adjacent projection patterns is less than 90 degrees.

10. The alignment mark according to claim 1, wherein: The substrate further includes: a base and a layer to be etched located on the base, and the first layer to be processed is located on the layer to be etched.

11. The alignment mark according to claim 10, wherein: The layer to be etched includes: a device layer and a hard mask layer located on the device layer, and the first layer to be processed is located on the hard mask layer.

12. The alignment mark according to claim 11, wherein: Also includes: a first stop layer, the first stop layer being located between the substrate and the device layer; a second stop layer, the second stop layer being located between the device layer and the hard mask layer; A third stop layer is located between the hard mask layer and the first layer to be processed.

13. A method for forming an alignment mark, characterized in that: include: Providing a substrate, the substrate comprising an alignment area and a chip area, the alignment area being located at the intersection of a transverse cut and a longitudinal cut, and having a marking origin in the alignment area; forming a first layer to be processed on the alignment area; Several graphic processings are used to form several discrete mark openings in the first layer to be processed. The etching depths of the several mark openings are the same. Each of the mark openings has a corresponding projection pattern on the alignment area. The projection patterns are evenly spaced with the mark origin as the center of the circle. The projection patterns are evenly spaced with the mark origin as the center of the circle. The projection patterns are distributed in a circle around the center of the circle, and the angles between adjacent projection patterns are equal.

14. The method for forming an alignment mark according to claim 13, wherein: The patterning method includes: forming a patterning layer on the first layer to be processed, wherein the patterning layer exposes a portion of the top surface of the first layer to be processed; and etching the first layer to be processed using the patterning layer as a mask to form the marking opening in the first layer to be processed.

15. The method for forming an alignment mark according to claim 14, wherein: Before forming the patterned layer, the method further includes: forming a sacrificial layer and an anti-reflection layer on the first layer to be processed, wherein the patterned layer is located on the anti-reflection layer.

16. The method for forming an alignment mark according to claim 13, wherein: The process of forming the first layer to be processed on the alignment area further includes: forming a second layer to be processed on the chip area.

17. The method for forming an alignment mark according to claim 16, wherein: The process of forming the plurality of mark openings further includes: forming a plurality of device openings in the second layer to be processed.

18. The method for forming an alignment mark according to claim 13, wherein: The projection figures are rectangular, and the extension direction of each projection figure is different. In the extension direction of each projection figure, there is an origin spacing size between the midpoint of the edge line of each projection figure close to the marked origin and the marked origin, and the origin spacing sizes are equal.

19. The method for forming an alignment mark according to claim 18, wherein: The origin spacing size range is less than 2 microns.

20. The method for forming an alignment mark according to claim 18, wherein: In a direction perpendicular to the extending direction of the respective projection patterns, each of the marking openings has a width dimension, and the width dimensions are equal.

21. The method for forming an alignment mark according to claim 20, wherein: The width dimension ranges from greater than 0.2 microns.

22. The method for forming an alignment mark according to claim 18, wherein: The range of the closest vertex distances between adjacent projection patterns is greater than 0.15 microns.

23. The method for forming an alignment mark according to claim 13, wherein: The angle between adjacent projection patterns is less than 90 degrees.

24. The method for forming an alignment mark according to claim 13, wherein: The substrate further includes: a base and a layer to be etched located on the base, and the first layer to be processed is located on the layer to be etched.

25. The method for forming an alignment mark according to claim 24, wherein: The layer to be etched includes: a device layer and a hard mask layer located on the device layer, and the first layer to be processed is located on the hard mask layer.

26. The method for forming an alignment mark according to claim 25, wherein: Also includes: a first stop layer, the first stop layer being located between the substrate and the device layer; a second stop layer, the second stop layer being located between the device layer and the hard mask layer; A third stop layer is located between the hard mask layer and the first layer to be processed.

27. The method for forming an alignment mark according to claim 17, wherein: After forming the device openings, the method further includes: forming first sidewall spacers on sidewalls of each of the device openings.

28. The method for forming an alignment mark according to claim 27, wherein: The process of forming the first sidewalls further includes forming second sidewalls on the sidewalls of each of the marking openings.

29. The method for forming an alignment mark according to claim 28, wherein: After forming the first sidewall spacer and the second sidewall spacer, the method further includes: removing the first to-be-processed layer; and etching a substrate using the first sidewall spacer and the second sidewall spacer as masks to form a patterned opening in the substrate.

Images