Light-emitting diode epitaxial wafer and preparation method thereof, and light-emitting diode

Abstract

The present invention discloses a light-emitting diode epitaxial wafer and a preparation method thereof, and a light-emitting diode. The light-emitting diode epitaxial wafer comprises a substrate and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer sequentially stacked on the substrate; the multi-quantum well layer comprises an In adjustment layer, a quantum well layer, and a quantum barrier layer, and the In adjustment layer, the quantum well layer, and the quantum barrier layer are repeatedly stacked in sequence to form the multi-quantum well layer. The present invention can alleviate the segregation of In in the quantum well layer, make the In distribution more uniform, improve the uniformity of the light-emitting wavelength of the epitaxial wafer, and also improve the luminous efficiency of the multi-quantum well.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic technology, and in particular to a light emitting diode epitaxial wafer and a preparation method thereof, and a light emitting diode. Background Art

[0002] At present, GaN-based light-emitting diodes have been widely used in the fields of solid-state lighting and display, attracting more and more attention. GaN-based light-emitting diodes have been industrialized and used in backlight sources, lighting, landscape lights, etc.

[0003] As the active region, the multi-quantum well layer is the core structure of the light-emitting diode and has attracted extensive attention from researchers. By adjusting the In content of the InGaN well layer, the emission wavelength of the LED can cover a very wide wavelength range from near infrared to near ultraviolet, so the distribution uniformity of the In component has a crucial influence on the uniformity of the emission wavelength.

[0004] However, due to the low thermal stability of InN in the quantum well layer of the traditional multi-layer quantum well InGaN quantum well layer and GaN quantum barrier layer superlattice structure, it is easy to cause InN vacancies that are decomposed by heat, thereby aggravating the segregation and enrichment of In in the InGaN layer, which will cause uneven stress between the heterojunction materials in the InGaN layer and the GaN layer superlattice structure in the multi-layer quantum well, resulting in problems such as poor wavelength uniformity and low luminous efficiency. In addition, due to the serious lattice mismatch between the GaN quantum barrier layer and the InGaN quantum well layer heterogeneous materials, the stress in the quantum well region increases, the defects increase, and the segregation of In is aggravated, which will also cause problems such as poor wavelength uniformity and low luminous efficiency. This phenomenon is particularly serious for long-wavelength light-emitting diodes with a high In component, such as green and yellow light. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a light-emitting diode epitaxial wafer, which can alleviate the segregation of In in the quantum well layer, make the In distribution more uniform, improve the uniformity of the emission wavelength of the epitaxial wafer, and also improve the luminous efficiency of the multi-quantum well.

[0006] The technical problem to be solved by the present invention is to provide a method for preparing a light-emitting diode epitaxial wafer, which has a simple process and can stably prepare a light-emitting diode epitaxial wafer with uniform luminous wavelength and good luminous efficiency.

[0007] In order to solve the above technical problems, the present invention provides a light-emitting diode epitaxial wafer, comprising a substrate and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer sequentially stacked on the substrate;

[0008] The multi-quantum well layer comprises an In regulating layer, a quantum well layer and a quantum barrier layer, and the In regulating layer, the quantum well layer and the quantum barrier layer are repeatedly stacked in sequence to form the multi-quantum well layer.

[0009] In one embodiment, the In regulating layer includes an Al layer, an Al x N 1-x Three-dimensional layer, In y N 1-y 3D Layer and In z Ga 1-z N buffer layer, wherein the value range of x is 0.05-0.1, the value range of y is 0.1-0.2, and the value range of z is 0.05-0.1.

[0010] In one embodiment, the thickness of the Al layer is about 0.1 nm-1 nm;

[0011] The Al x N 1-x The thickness of the three-dimensional layer is about 0.5nm-2nm;

[0012] In y N 1-y The thickness of the three-dimensional layer is about 0.5nm-2nm;

[0013] In z Ga 1-z The thickness of the N buffer layer is 0.5nm-2nm.

[0014] In one embodiment, the thickness of the In adjustment layer is 1.5 nm to 7 nm;

[0015] The thickness of the quantum well layer is 2nm-5nm;

[0016] The thickness of the quantum barrier layer is 3nm-15nm;

[0017] The repeated stacking period of the In regulating layer, the quantum well layer and the quantum barrier layer is 3-15.

[0018] In one embodiment, the thickness of the buffer layer is 20nm-100nm;

[0019] The thickness of the intrinsic GaN layer is 300nm-800nm;

[0020] The thickness of the N-type GaN layer is 1 μm-3 μm, the N-type GaN layer is doped with Si, and the doping concentration of Si is 5×10 18 -1×10 19 cm -3 ;

[0021] The thickness of the P-type GaN layer is 200nm-300nm, and the P-type GaN layer is doped with Mg, and the doping concentration of Mg is 5×10 17 -1×10 20 cm -3 .

[0022] In one embodiment, the electron blocking layer comprises an alternately stacked Al a Ga 1-a N layer and In b Ga 1-b N layers, the number of stacking cycles is 3-15, where the value range of a is 0.05-0.2, and the value range of b is 0.1-0.5;

[0023] The Al a Ga 1-a The thickness of the N layer is 5nm-7nm;

[0024] In b Ga 1-b The thickness of the N layer is 5nm-7nm;

[0025] The thickness of the electron blocking layer is 20nm-50nm.

[0026] To solve the above problems, the present invention also provides a method for preparing a light emitting diode epitaxial wafer, comprising the following steps:

[0027] preparing a substrate;

[0028] Depositing a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer in sequence on the substrate;

[0029] The multi-quantum well layer comprises an In regulating layer, a quantum well layer and a quantum barrier layer, and the In regulating layer, the quantum well layer and the quantum barrier layer are repeatedly stacked in sequence to form the multi-quantum well layer.

[0030] In one embodiment, the deposition of the In regulating layer is completed by the following method:

[0031] Al layer, Al x N 1-x Three-dimensional layer, In y N 1-y 3D Layer and In z Ga 1-z The N buffer layer forms the In adjustment layer, wherein the value range of x is 0.05-0.1, the value range of y is 0.1-0.2, and the value range of z is 0.05-0.1.

[0032] In one embodiment, the deposition of the Al layer is completed by the following method:

[0033] The temperature of the reaction chamber is controlled at 800°C-900°C, and TMAl is introduced as an Al source to complete the deposition;

[0034] And / or, the Al is completed by the following method x N 1-x Deposition of 3D layers:

[0035] The temperature of the reaction chamber is controlled at 700°C-800°C, TMAl is introduced as an Al source, and NH3 is introduced as a N source to complete the deposition;

[0036] And / or, the following method is used to complete the In y N 1-y Deposition of 3D layers:

[0037] The temperature of the reaction chamber is controlled at 700℃-800℃, TMIn is introduced as the In source, and NH3 is introduced as the N source to complete the deposition;

[0038] And / or, the following method is used to complete the In z Ga 1-z N deposition:

[0039] The temperature of the reaction chamber is controlled at 800°C-900°C, TMIn is introduced as an In source, NH3 is introduced as a N source, and TMGa is introduced as a Ga source to complete the deposition.

[0040] In one embodiment, the deposition of the multi-quantum well layer is completed by the following method:

[0041] Repeatingly stacking an In regulating layer, a quantum well layer and a quantum barrier layer on the N-type GaN layer in sequence, wherein the repeated stacking period is 3-15;

[0042] The deposition of the quantum well layer is completed by the following method:

[0043] The temperature of the reaction chamber is controlled at 700°C-800°C, TMIn is introduced as an In source, NH3 is introduced as a N source, and TMGa is introduced as a Ga source to complete the deposition.

[0044] And / or, the deposition of the quantum barrier layer is completed by the following method:

[0045] The temperature of the reaction chamber is controlled at 800°C-900°C, NH3 is introduced as the N source, and TMGa is introduced as the Ga source to complete the deposition.

[0046] In one embodiment, the buffer layer is deposited on the front side of the substrate by the following method:

[0047] The temperature of the reaction chamber is controlled at 500° C.-700° C., TMAl is introduced as an Al source, and NH3 is introduced as an N source to complete the deposition of a buffer layer on the front side of the substrate;

[0048] And / or, the intrinsic GaN layer is deposited on the buffer layer by the following method:

[0049] The temperature of the reaction chamber is controlled at 1100° C.-1150° C., NH 3 is introduced as a N source, and TMGa is introduced as a Ga source to complete the deposition of the intrinsic GaN layer on the buffer layer;

[0050] And / or, depositing the N-type GaN layer on the intrinsic GaN layer by the following method:

[0051] The temperature of the reaction chamber is controlled at 1100° C.-1150° C., SiN4 is introduced as a Si source, NH3 is introduced as a N source, and TMGa is introduced as a Ga source to complete the deposition of the N-type GaN layer on the intrinsic GaN layer;

[0052] And / or, the P-type GaN layer is deposited on the electron blocking layer by the following method:

[0053] The temperature of the reaction chamber is controlled at 800° C.-1000° C., NH 3 is introduced as an N source, TMGa is introduced as a Ga source, and CP2Mg is introduced as a Mg source to complete the deposition of the P-type GaN layer on the electron blocking layer.

[0054] In one embodiment, the electron blocking layer is deposited on the multi-quantum well layer by the following method:

[0055] Al is alternately deposited on the multi-quantum well layer. a Ga 1-a N layer and In b Ga 1-b N layers, the number of stacked layers is between 3 and 15, the value range of a is 0.05-0.2, and the value range of b is 0.1-0.5;

[0056] Among them, the Al a Ga 1-a The deposition steps of the N layer include:

[0057] The temperature of the reaction chamber is controlled at 900°C-1000°C, TMAL is introduced as an Al source, NH3 is introduced as a N source, and TMGa is introduced as a Ga source to complete the deposition;

[0058] In b Ga 1-b The deposition steps of the N layer include:

[0059] The temperature of the reaction chamber is controlled at 900°C-1000°C, TMIn is introduced as an In source, NH3 is introduced as a N source, and TMGa is introduced as a Ga source to complete the deposition.

[0060] Correspondingly, the present invention further provides a light emitting diode, which includes the light emitting diode epitaxial wafer described above.

[0061] The implementation of the present invention has the following beneficial effects:

[0062] The light-emitting diode epitaxial wafer provided by the present invention, the multi-quantum well layer proposed by the present invention includes an In adjustment layer, a quantum well layer and a quantum barrier layer, and the In adjustment layer, the quantum well layer and the quantum barrier layer are repeatedly stacked in sequence to form the multi-quantum well layer. The In component adjustment layer relieves the stress of the quantum well layer and reduces the lattice mismatch between the quantum barrier layer and the quantum well layer, thereby avoiding the generation of too many defects and becoming the center of the "In cluster". It also effectively regulates the distribution of the In component in the quantum well layer, alleviates the segregation of In in the quantum well, makes its distribution more uniform, improves the uniformity of the light-emitting wavelength of the epitaxial wafer, and also improves the light-emitting efficiency of the multi-quantum well. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 This is a schematic structural diagram of a light-emitting diode epitaxial wafer provided by the present invention, wherein a substrate is 1, a buffer layer is 2, an intrinsic GaN layer is 3, an N-type GaN layer is 4, a multi-quantum well layer is 5, an electron blocking layer is 6, and a P-type GaN layer is 7. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is described in further detail below.

[0065] Unless otherwise specified or incompatible herewith, the terms and phrases used herein shall have the following meanings:

[0066] In the present invention, "combinations thereof", "any combinations thereof", "any combination thereof" and the like used include all suitable combinations of any two or more of the listed items.

[0067] In the present invention, “preferred” is only used to describe an implementation method or example with better effects, and it should be understood that it does not constitute a limitation on the protection scope of the present invention.

[0068] In the present invention, the technical features described in an open manner include closed technical solutions composed of the listed features, and also include open technical solutions containing the listed features.

[0069] In the present invention, reference to a numerical range includes both endpoints of the numerical range unless otherwise specified.

[0070] There is serious In segregation in the traditional multi-layer quantum well InGaN quantum well layer and GaN quantum barrier layer superlattice structure. Due to the well-barrier lattice mismatch, the stress in the quantum well layer is also very large and the lattice quality is poor, which affects the wavelength uniformity and luminescence efficiency.

[0071] To solve the above problems, the present invention provides a light emitting diode epitaxial wafer, such as Figure 1 As shown, it includes a substrate 1 and a buffer layer 2, an intrinsic GaN layer 3, an N-type GaN layer 4, a multi-quantum well layer 5, an electron blocking layer 6, and a P-type GaN layer 7 which are sequentially stacked on the substrate 1;

[0072] The multi-quantum well layer 5 includes an In regulating layer, a quantum well layer and a quantum barrier layer. The In regulating layer, the quantum well layer and the quantum barrier layer are repeatedly stacked in sequence to form the multi-quantum well layer.

[0073] The light-emitting diode epitaxial wafer provided by the present invention, the multi-quantum well layer proposed by the present invention includes an In adjustment layer, a quantum well layer and a quantum barrier layer, and the In adjustment layer, the quantum well layer and the quantum barrier layer are repeatedly stacked in sequence to form the multi-quantum well layer. The In component adjustment layer relieves the stress of the quantum well layer and reduces the lattice mismatch between the quantum barrier layer and the quantum well layer, thereby avoiding the generation of too many defects and becoming the center of the "In cluster". It also effectively regulates the distribution of the In component in the quantum well layer, alleviates the segregation of In in the quantum well, makes its distribution more uniform, improves the uniformity of the light-emitting wavelength of the epitaxial wafer, and also improves the light-emitting efficiency of the multi-quantum well.

[0074] The multi-quantum well layer is the core structure of the light-emitting diode. In one embodiment, the thickness of the In regulating layer is 1.5nm-7nm; the thickness of the quantum well layer is 2nm-5nm; the thickness of the quantum barrier layer is 3nm-15nm; the repeated stacking period of the In regulating layer, quantum well layer and quantum barrier layer is 3-15.

[0075] In one embodiment, the In regulating layer includes an Al layer, an Al x N 1-x Three-dimensional layer, In y N 1-y 3D Layer and In z Ga 1-z N buffer layer, wherein the value range of x is 0.05-0.1, the value range of y is 0.1-0.2, and the value range of z is 0.05-0.1. In one embodiment, the thickness of the Al layer is about 0.1nm-1nm; x N 1-x The thickness of the three-dimensional layer is about 0.5nm-2nm; y N 1-yThe thickness of the three-dimensional layer is about 0.5nm-2nm; z Ga 1-z The thickness of the N buffer layer is 0.5nm-2nm.

[0076] It should be noted that the Al layer in the present invention is thinly adsorbed on the surface of the epitaxial layer; x N 1-x The three-dimensional layer grows into uniformly distributed island shapes on the surface of the epitaxial layer; y N 1-y The three-dimensional layer preferentially adsorbs on the uniformly distributed Al x N 1-x On the small island, the three-dimensional island continues to grow, and the In y N 1-y The In atoms are distributed very uniformly in the three-dimensional layer; z Ga 1-z In atoms in the N buffer layer are also preferentially adsorbed on In y N 1-y On the island, at the same time z Ga 1-z N gradually fills up In y N 1-y The three-dimensional layer also makes the distribution of In atoms more uniform. z Ga 1-z The N buffer layer also becomes a preparation layer for the growth of the quantum well layer. It has a small lattice mismatch with the quantum well layer, which can relieve the stress of the multi-quantum well layer, reduce the lattice mismatch when the quantum barrier layer and the quantum well layer grow, and avoid excessive defects that become the center of the "In cluster". On the other hand, the In atoms are evenly distributed in the low In component. z Ga 1-z The quantum well layer is grown on the N buffer layer, and the In atoms in the quantum well layer are more likely to be adsorbed and grown on the uniformly distributed In component on the In component adjustment layer, so that the distribution of In in the grown quantum well layer is more uniform.

[0077] In one embodiment, the buffer layer is an AlGaN buffer layer or an AlN buffer layer. The buffer layer is mainly used to provide seed crystals, alleviate the lattice mismatch between the substrate and the epitaxial layer, and improve the lattice quality of the epitaxial wafer. In one embodiment, the buffer layer has a thickness of 20nm-100nm.

[0078] The intrinsic GaN layer is an undoped GaN layer. In one embodiment, the thickness of the intrinsic GaN layer is 300nm-800nm.

[0079] The N-type GaN layer mainly provides electrons. In one embodiment, the thickness of the N-type GaN layer is 1 μm-3 μm, and the N-type GaN layer is Si-doped, and the doping concentration of Si is 5×10 18 -1×10 19 cm -3 The P-type GaN layer mainly provides holes. In one embodiment, the thickness of the P-type GaN layer is 200nm-300nm, and the P-type GaN layer is Mg-doped, and the Mg doping concentration is 5×10 17 -1×10 20 cm -3 .

[0080] The electron blocking layer is mainly used to block electrons and prevent electron overflow. In one embodiment, the electron blocking layer includes alternately stacked Al a Ga 1-a N layer and In b Ga 1-b N layers, the number of stacking cycles is 3-15, where the value range of a is 0.05-0.2, and the value range of b is 0.1-0.5;

[0081] The Al a Ga 1-a The thickness of the N layer is 5nm-7nm;

[0082] In b Ga 1-b The thickness of the N layer is 5nm-7nm;

[0083] The thickness of the electron blocking layer is 20nm-50nm.

[0084] Accordingly, the present invention also provides a method for preparing the above-mentioned light-emitting diode epitaxial wafer, comprising the following steps:

[0085] S1. Prepare substrate;

[0086] In one embodiment, the substrate is a sapphire substrate. Then, the temperature of the reaction chamber is controlled to be 1000° C. to 1200° C., the pressure of the reaction chamber is controlled to be 200 Torr to 600 Torr, and the substrate is subjected to high temperature annealing for 5 min to 8 min in a H2 atmosphere to clean particles and oxides on the surface of the substrate.

[0087] S2, depositing a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer on the substrate in sequence;

[0088] The multi-quantum well layer comprises an In regulating layer, a quantum well layer and a quantum barrier layer, and the In regulating layer, the quantum well layer and the quantum barrier layer are repeatedly stacked in sequence to form the multi-quantum well layer.

[0089] In one embodiment, step S2 comprises the following steps:

[0090] S21, depositing the buffer layer on the front side of the substrate by the following method:

[0091] In one embodiment, the buffer layer is an AlGaN buffer layer or an AlN buffer layer. Preferably, the buffer layer is an AlN buffer layer, and the AlN buffer layer is prepared by the following method: controlling the temperature of the reaction chamber at 500°C-700°C, introducing TMAl as an Al source, introducing NH3 as an N source, and completing the deposition of the buffer layer on the front side of the substrate.

[0092] S22, using the following method to complete the deposition of the intrinsic GaN layer on the buffer layer:

[0093] The temperature of the reaction chamber is controlled at 1100° C.-1150° C., NH 3 is introduced as an N source, and TMGa is introduced as a Ga source to complete the deposition of the intrinsic GaN layer on the buffer layer.

[0094] S23, using the following method to complete the deposition of the N-type GaN layer on the intrinsic GaN layer:

[0095] The temperature of the reaction chamber is controlled at 1100° C.-1150° C., SiN4 is introduced as a Si source, NH3 is introduced as a N source, and TMGa is introduced as a Ga source to complete the deposition of the N-type GaN layer on the insertion layer;

[0096] S24, using the following method to complete the deposition of the multi-quantum well layer on the N-type GaN layer:

[0097] Repeatingly stacking an In regulating layer, a quantum well layer and a quantum barrier layer on the N-type GaN layer in sequence, wherein the repeated stacking period is 3-15;

[0098] The deposition of the quantum well layer is completed by the following method:

[0099] The temperature of the reaction chamber is controlled at 700°C-800°C, TMIn is introduced as an In source, NH3 is introduced as a N source, and TMGa is introduced as a Ga source to complete the deposition.

[0100] And / or, the deposition of the quantum barrier layer is completed by the following method:

[0101] The temperature of the reaction chamber is controlled at 800°C-900°C, NH3 is introduced as the N source, and TMGa is introduced as the Ga source to complete the deposition.

[0102] In one embodiment, the deposition of the In regulating layer is completed by the following method:

[0103] Al layer, Al x N 1-x Three-dimensional layer, In y N 1-y 3D Layer and In z Ga 1-z The N buffer layer forms the In adjustment layer, wherein the value range of x is 0.05-0.1, the value range of y is 0.1-0.2, and the value range of z is 0.05-0.1.

[0104] Preferably, the deposition of the Al layer is completed by the following method:

[0105] The temperature of the reaction chamber is controlled at 800°C-900°C, and TMAl is introduced as an Al source to complete the deposition;

[0106] And / or, the Al is completed by the following method x N 1-x Deposition of 3D layers:

[0107] The temperature of the reaction chamber is controlled at 700°C-800°C, TMAl is introduced as an Al source, and NH3 is introduced as a N source to complete the deposition;

[0108] And / or, the following method is used to complete the In y N 1-y Deposition of 3D layers:

[0109] The temperature of the reaction chamber is controlled at 700℃-800℃, TMIn is introduced as the In source, and NH3 is introduced as the N source to complete the deposition;

[0110] And / or, the following method is used to complete the In z Ga 1-z N deposition:

[0111] The temperature of the reaction chamber is controlled at 800°C-900°C, TMIn is introduced as an In source, NH3 is introduced as a N source, and TMGa is introduced as a Ga source to complete the deposition.

[0112] It should be noted that the In adjustment layer of the present invention first deposits the Al layer. During the process, the Al atoms are introduced for a short time, so they are temporarily adsorbed on the surface of the epitaxial layer. Then the Al layer is grown. x N 1-x Three-dimensional layer, Al source and NH3 are introduced into the reaction chamber. NH3 reacts with Al atoms on the Al layer to form AlN nucleation points, which continuously absorb AlN in the atmosphere and grow into small islands.x N 1-x The three-dimensional layer has uniform distribution of AlN islands with strong size consistency. x N 1-x In growth on three-dimensional layers y N 1-y After the In source and N source are introduced into the three-dimensional layer, InN is preferentially adsorbed on the evenly distributed AlN islands, and the three-dimensional islands continue to grow. At this time, the In atoms in the InN layer formed are very evenly distributed. z Ga 1-z N buffer layer. When the InGaN material grows, In atoms are more likely to be adsorbed on the InN islands and grow. When InGaN gradually fills the three-dimensional layer, the distribution of In atoms is more uniform. z Ga 1-z The N buffer layer becomes a preparation layer for the growth of the quantum well layer. It has a small lattice mismatch with the InGaN quantum well layer, which can relieve the stress of the multi-quantum well layer, reduce the lattice mismatch when the quantum barrier layer and the quantum well layer grow, and avoid excessive defects that become the center of the "In cluster". On the other hand, the In atoms are evenly distributed in the low In component of the In z Ga 1-z An InGaN quantum well layer is grown on the N buffer layer, and the In atoms in the quantum well layer are more likely to be adsorbed and grown on the uniformly distributed In component on the In component adjustment layer, so that the distribution of In in the grown quantum well layer is more uniform.

[0113] In addition, the Al layer growth temperature is 800-900°C. x N 1-x The growth temperature of the three-dimensional layer is 700-800°C. y N 1-y The growth temperature of the three-dimensional layer is 700-800°C. z Ga 1-z The growth temperature of the N buffer layer is 800-900°C; x N 1-x Three-dimensional layer and the In y N 1-y The growth temperature of the three-dimensional layer is relatively low, and low temperature is conducive to three-dimensional growth. The temperature of the Al layer is relatively high, which is mainly conducive to the migration of Al atoms on the surface of the epitaxial wafer, making the distribution of Al atoms more uniform. z Ga 1-z The temperature of the N buffer layer is relatively high in order to make the surface of the epitaxial layer smoother, the lattice quality better, and fewer defects formed.

[0114] S25, using the following method to complete the deposition of the electron blocking layer on the multi-quantum well layer:

[0115] Al is alternately deposited on the multi-quantum well layer. a Ga 1-a N layer and In b Ga 1-b N layers, the number of stacked layers is between 3 and 15, the value range of a is 0.05-0.2, and the value range of b is 0.1-0.5;

[0116] Among them, the Al a Ga 1-a The deposition steps of the N layer include:

[0117] The temperature of the reaction chamber is controlled at 900°C-1000°C, TMAL is introduced as an Al source, NH3 is introduced as a N source, and TMGa is introduced as a Ga source to complete the deposition;

[0118] In b Ga 1-b The deposition steps of the N layer include:

[0119] The temperature of the reaction chamber is controlled at 900°C-1000°C, TMIn is introduced as an In source, NH3 is introduced as a N source, and TMGa is introduced as a Ga source to complete the deposition.

[0120] S26, using the following method to complete the deposition of the P-type GaN layer on the electron blocking layer:

[0121] The temperature of the reaction chamber is controlled at 800° C.-1000° C., NH 3 is introduced as an N source, TMGa is introduced as a Ga source, and CP2Mg is introduced as a Mg source to complete the deposition of the P-type GaN layer on the electron blocking layer.

[0122] Correspondingly, the present invention further provides a light emitting diode, which includes the light emitting diode epitaxial wafer described above.

[0123] The above deposition process is completed by using MOCVD equipment or PVD equipment, and the present invention does not limit the deposition method. In addition, the above Al source, N source, Ga source, Si source, Mg source, Sc source, and In source are exemplary and are not limited to the above examples.

[0124] The present invention is further described below with specific embodiments:

[0125] Example 1

[0126] This embodiment provides a light-emitting diode epitaxial wafer, comprising a substrate and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer sequentially stacked on the substrate;

[0127] The multi-quantum well layer comprises an In regulating layer, a quantum well layer and a quantum barrier layer, and the In regulating layer, the quantum well layer and the quantum barrier layer are repeatedly stacked in sequence to form the multi-quantum well layer;

[0128] The In regulating layer includes an Al layer, an Al x N 1-x Three-dimensional layer, In y N 1-y 3D Layer and In z Ga 1-z N buffer layer, wherein x is 0.07, y is 0.15, z is 0.07, and the repeated stacking period of the In adjustment layer, quantum well layer and quantum barrier layer is 10.

[0129] The method for preparing the light emitting diode epitaxial wafer comprises the following steps:

[0130] S1. Prepare a substrate; the substrate is a sapphire substrate.

[0131] S2, buffer layer, intrinsic GaN layer, N-type GaN layer, multi-quantum well layer, electron blocking layer, P-type GaN layer;

[0132] Specifically, S2 includes the following steps:

[0133] S21, depositing the buffer layer on the front side of the substrate by the following method:

[0134] The temperature of the reaction chamber was controlled at 600° C., TMAl was introduced as an Al source, NH 3 was introduced as an N source, and a buffer layer was deposited on the front side of the substrate. The deposition was completed and the thickness of the deposited buffer layer was controlled to be 30 nm.

[0135] S22, using the following method to complete the deposition of the intrinsic GaN layer on the buffer layer:

[0136] The temperature of the reaction chamber was controlled at 1150°C, NH3 was introduced as the N source, and TMGa was introduced as the Ga source to complete the deposition and control the deposition thickness to 400nm;

[0137] S23, using the following method to complete the deposition of the N-type GaN layer on the intrinsic GaN layer:

[0138] The temperature of the reaction chamber was controlled at 1050°C, SiN4 was introduced as the Si source, NH3 was introduced as the N source, and TMGa was introduced as the Ga source to complete the deposition and control the deposition thickness to be 2 μm, and the Si doping concentration was 1*10 19 cm -3 ;

[0139] S24, using the following method to complete the deposition of the multi-quantum well layer on the N-type GaN layer:

[0140] Repeatingly stacking an In regulating layer, a quantum well layer and a quantum barrier layer on the N-type GaN layer in sequence, wherein the repeated stacking period is 10;

[0141] The deposition of the In regulating layer is completed by the following method:

[0142] Al layer, Al x N 1-x Three-dimensional layer, In y N 1-y 3D Layer and In z Ga 1-z The N buffer layer forms the In regulating layer, wherein x is 0.07, y is 0.15, and z is 0.07.

[0143] The deposition of the Al layer is completed by the following method:

[0144] The temperature of the reaction chamber was controlled at 850°C, TMAl was introduced as an Al source, and the deposition was completed and the deposition thickness was controlled to be 0.5 nm;

[0145] The following method is used to complete the Al x N 1-x Deposition of 3D layers:

[0146] The temperature of the reaction chamber was controlled at 750°C, TMAl was introduced as the Al source, and NH3 was introduced as the N source to complete the deposition and control the deposition thickness to be 1 nm;

[0147] The following method is used to complete the In y N 1-y Deposition of 3D layers:

[0148] The temperature of the reaction chamber was controlled at 750°C, TMIn was introduced as the In source, NH3 was introduced as the N source, and the deposition was completed and the deposition thickness was controlled to be 1 nm;

[0149] The following method is used to complete the In z Ga 1-z N deposition:

[0150] The temperature of the reaction chamber was controlled at 850°C, TMIn was introduced as the In source, NH3 was introduced as the N source, and TMGa was introduced as the Ga source to complete the deposition and control the deposition thickness to be 1 nm.

[0151] Then, the deposition of the quantum well layer is completed by the following method:

[0152] The temperature of the reaction chamber was controlled at 750°C, TMIn was introduced as the In source, NH3 was introduced as the N source, and TMGa was introduced as the Ga source to complete the deposition and control the deposition thickness to be 3 nm.

[0153] The deposition of the quantum barrier layer is completed by the following method:

[0154] The temperature of the reaction chamber was controlled at 850°C, NH3 was introduced as the N source, TMGa was introduced as the Ga source, the deposition was completed and the deposition thickness was controlled to be 10 nm.

[0155] S25, using the following method to complete the deposition of the electron blocking layer on the multi-quantum well layer:

[0156] Al is alternately deposited on the multi-quantum well layer. a Ga 1-a N layer and In b Ga 1-b N layers, the number of stacked layers is between 3 and 15, the value range of a is 0.1, and the value range of b is 0.3;

[0157] Among them, the Al a Ga 1-a The deposition steps of the N layer include:

[0158] The temperature of the reaction chamber was controlled at 950°C, TMAL was introduced as the Al source, NH3 was introduced as the N source, and TMGa was introduced as the Ga source to complete the deposition and control the deposition thickness to be 6nm. ;

[0159] In b Ga 1-b The deposition steps of the N layer include:

[0160] The temperature of the reaction chamber was controlled at 950°C, TMIn was introduced as the In source, NH3 was introduced as the N source, and TMGa was introduced as the Ga source to complete the deposition and control the deposition thickness to be 6 nm.

[0161] S26, using the following method to complete the deposition of the P-type GaN layer on the electron blocking layer:

[0162] The temperature of the reaction chamber was controlled at 850 °C, Mg source was introduced as the doping source, NH3 was introduced as the N source, and TMGa was introduced as the Ga source to complete the deposition and control the deposition thickness to be 4 nm, and the Mg doping concentration was 5*10 19 cm -3 .

[0163] Example 2

[0164] This embodiment provides a light-emitting diode epitaxial wafer, comprising a substrate and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer sequentially stacked on the substrate;

[0165] The multi-quantum well layer comprises an In regulating layer, a quantum well layer and a quantum barrier layer, and the In regulating layer, the quantum well layer and the quantum barrier layer are repeatedly stacked in sequence to form the multi-quantum well layer;

[0166] The In regulating layer includes an Al layer, an Al x N 1-x Three-dimensional layer, In y N 1-y 3D Layer and In z Ga 1-z N buffer layer, wherein x is 0.07, y is 0.2, z is 0.07, and the repeated stacking period of the In regulating layer, the quantum well layer and the quantum barrier layer is 15.

[0167] The method for preparing the above-mentioned light-emitting diode epitaxial wafer refers to Example 1.

[0168] Comparative Example 1

[0169] This comparative example provides a light-emitting diode epitaxial wafer, comprising a substrate and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer sequentially stacked on the substrate;

[0170] The multi-quantum well layer comprises a quantum well layer and a quantum barrier layer, and the quantum well layer and the quantum barrier layer are repeatedly stacked in sequence to form the multi-quantum well layer;

[0171] The preparation method of the light emitting diode epitaxial wafer is as described in Example 1. Meanwhile, the multi-quantum well layer is controlled so that the emission wavelength is the same as that in Example 1.

[0172] Comparative Example 2

[0173] This comparative example provides a light-emitting diode epitaxial wafer, comprising a substrate and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer sequentially stacked on the substrate;

[0174] The multi-quantum well layer comprises a quantum well layer and a quantum barrier layer, and the quantum well layer and the quantum barrier layer are repeatedly stacked in sequence to form the multi-quantum well layer;

[0175] The preparation method of the light emitting diode epitaxial wafer is as described in Example 1. Meanwhile, the multi-quantum well layer is controlled so that the emission wavelength is the same as that in Example 2.

[0176] The light-emitting diode epitaxial wafers prepared in Examples 1-3 and Comparative Examples 1-2 were used to make chips for performance testing, wherein the epitaxial wafers prepared in Example 1 and Comparative Example 1 were made into 10*24mil chips, and the brightness test current was 120mA, and the epitaxial wafers prepared in Example 2 and Comparative Example 2 were made into 5*7mil chips, and the brightness test current was 6mA. The specific test results are shown in Table 1.

[0177] Table 1 is the performance test results of the light emitting diode epitaxial wafers obtained in Example 1-2 and Comparative Example 1-2

[0178]

[0179] From the above results, it can be seen that the epitaxial structure with the In component adjustment layer proposed in the present invention has a more uniform distribution of the In component and a significant improvement in wavelength uniformity, especially for long-wavelength light-emitting diodes with a higher In component, the wavelength uniformity is improved by 0.3nm, and the luminous brightness also shows a great advantage.

[0180] The above is a preferred embodiment of the invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the invention. These improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A light emitting diode epitaxial wafer, characterized in that: It includes a substrate and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer stacked in sequence on the substrate; The multi-quantum well layer comprises an In regulating layer, a quantum well layer and a quantum barrier layer, and the In regulating layer, the quantum well layer and the quantum barrier layer are repeatedly stacked in sequence to form the multi-quantum well layer; The In regulating layer includes an Al layer, an Al x N 1-x Three-dimensional layer, In y N 1-y 3D Layer and In z Ga 1-z N buffer layer, wherein the value range of x is 0.05-0.1, the value range of y is 0.1-0.2, and the value range of z is 0.05-0.

1.

2. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The thickness of the Al layer is 0.1nm-1nm; The Al x N 1-x The thickness of the three-dimensional layer is 0.5nm-2nm; In y N 1-y The thickness of the three-dimensional layer is 0.5nm-2nm; In z Ga 1-z The thickness of the N buffer layer is 0.5nm-2nm.

3. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The thickness of the In adjustment layer is 1.5nm-7nm; The thickness of the quantum well layer is 2nm-5nm; The thickness of the quantum barrier layer is 3nm-15nm; The repeated stacking period of the In regulating layer, the quantum well layer and the quantum barrier layer is 3-15.

4. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The thickness of the buffer layer is 20nm-100nm; The thickness of the intrinsic GaN layer is 300nm-800nm; The thickness of the N-type GaN layer is 1 μm-3 μm, the N-type GaN layer is doped with Si, and the doping concentration of Si is 5×10 18 -1×10 19 cm -3 ; The thickness of the P-type GaN layer is 200nm-300nm, and the P-type GaN layer is doped with Mg, and the doping concentration of Mg is 5×10 17 -1×10 20 cm -3 .

5. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The electron blocking layer includes alternately stacked Al a Ga 1-a N layer and In b Ga 1-b N layers, the number of stacking cycles is 3-15, where the value range of a is 0.05-0.2, and the value range of b is 0.1-0.5; The Al a Ga 1-a The thickness of the N layer is 5nm-7nm; In b Ga 1-b The thickness of the N layer is 5nm-7nm; The thickness of the electron blocking layer is 20nm-50nm.

6. A method for preparing a light emitting diode epitaxial wafer according to any one of claims 1 to 5, characterized in that: The following steps are involved: preparing a substrate; Depositing a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer in sequence on the substrate; The multi-quantum well layer comprises an In regulating layer, a quantum well layer and a quantum barrier layer, and the In regulating layer, the quantum well layer and the quantum barrier layer are repeatedly stacked in sequence to form the multi-quantum well layer.

7. The method for preparing a light emitting diode epitaxial wafer according to claim 6, characterized in that: The deposition of the In regulating layer is completed by the following method: Al layer, Al x N 1-x Three-dimensional layer, In y N 1-y 3D Layer and In z Ga 1-z The N buffer layer forms the In adjustment layer, wherein the value range of x is 0.05-0.1, the value range of y is 0.1-0.2, and the value range of z is 0.05-0.

1.

8. The method for preparing a light emitting diode epitaxial wafer according to claim 7, characterized in that: The deposition of the Al layer is completed by the following method: The temperature of the reaction chamber is controlled at 800°C-900°C, and TMAl is introduced as an Al source to complete the deposition; And / or, the Al is completed by the following method x N 1-x Deposition of 3D layers: The temperature of the reaction chamber is controlled at 700°C-800°C, TMAl is introduced as an Al source, and NH3 is introduced as a N source to complete the deposition; And / or, the following method is used to complete the In y N 1-y Deposition of 3D layers: The temperature of the reaction chamber is controlled at 700℃-800℃, TMIn is introduced as the In source, and NH3 is introduced as the N source to complete the deposition; And / or, the following method is used to complete the In z Ga 1-z N deposition: The temperature of the reaction chamber is controlled at 800°C-900°C, TMIn is introduced as an In source, NH3 is introduced as a N source, and TMGa is introduced as a Ga source to complete the deposition.

9. A light emitting diode, characterized in that: The light emitting diode comprises the light emitting diode epitaxial wafer as claimed in any one of claims 1-5.

Images