On-chip Peltier cooling device and manufacturing method thereof

Abstract

The present application relates to the field of semiconductor technology and discloses an on-chip Peltier cooling device and a method for manufacturing the same. The device comprises: a first type well region located in a semiconductor substrate, a polysilicon gate and a dummy gate located on the surface of the semiconductor substrate, a first type doped region located in the first type well region, a second type doped region located in the first type well region, a first through hole located above the first section, and a second through hole located above the second section. The dummy gate is formed into a two-section structure with a gap, and a portion of the two-section structure away from the gap does not have a gate insulating layer between the semiconductor substrate and the semiconductor substrate. The first type doped region at least overlaps with the orthographic projection area of the first section of the dummy gate on the semiconductor substrate. The second type doped region at least overlaps with the orthographic projection area of the second section of the polysilicon gate and the dummy gate on the semiconductor substrate. In an embodiment of the present application, the direction of heat flow is from the inside of the device to the surface, thereby achieving heat dissipation and cooling.

Description

Technical Field

[0001] The present invention generally relates to the field of semiconductor technology, and in particular to an on-chip Peltier cooling device and a manufacturing method thereof. Background Art

[0002] Chips, known as the "food" of modern industry, are essential components of the information technology industry. They are crucial for the development of mobile phones, computers, automobiles, industrial control, the Internet of Things, big data, and artificial intelligence. In addition to performing their designed functions, chips inevitably generate heat during use. Efficiently dissipating this heat to maintain safe operating temperatures within the chip's internal components is crucial for ensuring product safety and reliability. As chip sizes and speeds increase, this challenge becomes increasingly challenging, necessitating the introduction of innovative approaches and methods.

[0003] The Peltier effect refers to the phenomenon in which heat is absorbed and released at the junctions of different conductors when current flows through a loop. Existing metal-based Peltier effect designs have limited cooling effectiveness, are incompatible with existing semiconductor CMOS processes, and require additional cooling modes, which is inconvenient for application. Therefore, there is a need for an on-chip Peltier cooling device to achieve better process compatibility and cooling effectiveness. Summary of the Invention

[0004] The purpose of the present invention is to provide an on-chip Peltier cooling device and a manufacturing method thereof, to provide a Peltier device compatible with existing CMOS processes, and to improve the cooling effect.

[0005] The present application discloses an on-chip Peltier cooling device, comprising:

[0006] a first type well region located in the semiconductor substrate;

[0007] a polysilicon gate and a dummy gate located on the surface of the semiconductor substrate, wherein the dummy gate is formed into a two-stage structure with a gap, wherein a portion of the two-stage structure away from the gap has no gate insulating layer between it and the semiconductor substrate;

[0008] a first-type doped region located in the first-type well region, the first-type doped region at least overlapping with an orthographic projection area of the first segment of the dummy gate on the semiconductor substrate;

[0009] a second-type doped region located in the first-type well region, the second-type doped region at least overlapping with an orthographic projection area of the polysilicon gate and the second segment of the dummy gate on the semiconductor substrate;

[0010] A first through hole is located above the first segment and a second through hole is located above the second segment.

[0011] In a preferred example, it also includes: a first three-state control gate connected to the first through hole and a second three-state control gate connected to the second through hole, the output end of the first three-state control gate is connected to the first through hole, the first input end and the second input end of the first three-state control gate are respectively connected to the first control signal and the first enable signal, the output end of the second three-state control gate is connected to the second through hole, and the first input end and the second input end of the second three-state control gate are respectively connected to the second control signal and the second enable signal.

[0012] In a preferred example, the device includes a normal mode, a cooling mode and a heating mode, wherein when the first and second enable signals are both low, the device is in normal mode; when the first and second enable signals are both high and the first control signal is low, and the second control signal is high, the device is in cooling mode; when the first and second enable signals are both high and the second control signal is low, and the first control signal is high, the device is in heating mode.

[0013] In a preferred embodiment, a region of the first section of the dummy gate close to the gap is doped with a first type of doping.

[0014] In a preferred embodiment, the region of the second section of the dummy gate close to the gap is doped with the second type.

[0015] In a preferred embodiment, the distance between the polysilicon gate and the dummy gate is greater than 0.5 microns.

[0016] The present application also discloses an on-chip Peltier cooling device, comprising:

[0017] A first type well region and a second type well region adjacent to each other in a semiconductor substrate;

[0018] a first polysilicon gate and a first dummy gate located above the first type well region, and a second polysilicon gate and a second dummy gate located above the second type well region, wherein the first dummy gate and the second dummy gate are respectively formed into a two-segment structure with a gap, wherein a portion of the two-segment structure away from the gap has no gate insulating layer between the semiconductor substrate, and the second segment of the first dummy gate is connected to the second segment of the second dummy gate;

[0019] a first-type doped region located in the semiconductor substrate, the first-type doped region at least overlapping with an orthographic projection area of the first segment of the first dummy gate on the semiconductor substrate, and an orthographic projection area of the second polysilicon gate and the first segment of the second dummy gate on the semiconductor substrate, and the first segment of the first dummy gate is doped with the first type;

[0020] a second-type doped region located in the semiconductor substrate, the second-type doped region at least overlapping with an orthographic projection area of the second segment of the second dummy gate on the semiconductor substrate, and an orthographic projection area of the first polysilicon gate and the second segment of the first dummy gate on the semiconductor substrate, and the second segment of the second dummy gate is doped with the second type;

[0021] A first through hole is located above the first segment of the first dummy gate, and a second through hole is located above the first segment of the second dummy gate.

[0022] In a preferred embodiment, the area covered by the first type doping region is equal to the area of the second type well region.

[0023] In a preferred embodiment, the area covered by the second type doping region is equal to the area of the first type well region.

[0024] The present application also discloses a method for manufacturing an on-chip Peltier cooling device, comprising:

[0025] forming a gate insulating layer on the first type well region in the semiconductor substrate, wherein the gate insulating layer exposes a portion of the first type well region;

[0026] forming a polysilicon gate and a dummy gate on the first-type well region, wherein the dummy gate is formed into a two-stage structure with a gap, wherein a portion of the two-stage structure away from the gap has no gate insulating layer between it and the semiconductor substrate, and the gap is located in the exposed portion of the first-type well region;

[0027] forming a first-type doped region in the first-type well region, wherein the first-type doped region at least overlaps with an orthographic projection area of the first segment of the dummy gate on the semiconductor substrate, and the first segment of the dummy gate is doped with the first type;

[0028] forming a second-type doped region in the first-type well region, wherein the second-type doped region at least overlaps with an orthographic projection area of the polysilicon gate and the second segment of the dummy gate on the semiconductor substrate, and the second segment of the dummy gate is doped with the second type;

[0029] A first through hole is formed above the first segment and a second through hole is formed above the second segment.

[0030] The present application also discloses a method for manufacturing an on-chip Peltier cooling device, comprising:

[0031] forming a gate insulating layer on the first type well region and the second type well region in the semiconductor substrate, wherein the gate insulating layer exposes a portion of the first type well region and a portion of the second type well region;

[0032] forming a first polysilicon gate and a first dummy gate on the first type well region and forming a second polysilicon and a second dummy gate on the second type well region, wherein the first dummy gate and the second dummy gate are respectively formed into a two-segment structure with a gap, wherein a portion of the two-segment structure away from the gap has no gate insulating layer between it and the semiconductor substrate, and the gap is located in the exposed portion of the first type well region and the portion of the second type well region;

[0033] forming a first-type doped region in the semiconductor substrate, the first-type doped region at least overlapping with an orthographic projection area of the first segment of the first dummy gate on the semiconductor substrate, and an orthographic projection area of the second polysilicon gate and the first segment of the second dummy gate on the semiconductor substrate, and the first segment of the first dummy gate is doped with the first type;

[0034] forming a second-type doped region in the semiconductor substrate, the second-type doped region at least overlapping with an orthographic projection area of the second segment of the second dummy gate on the semiconductor substrate, and an orthographic projection area of the first polysilicon gate and the second segment of the first dummy gate on the semiconductor substrate, and the second segment of the second dummy gate is doped with the second type;

[0035] A first through hole is formed over the first segment of the first dummy gate and a second through hole is formed over the first segment of the second dummy gate.

[0036] In a preferred example, the second section of the first dummy gate and the second section of the second dummy gate are connected.

[0037] In the embodiments of this application, heat flows from the interior of the device to the surface, thereby achieving heat dissipation and cooling. Because the Seebeck coefficient of semiconductor materials is relatively large, approximately 30 times greater than that of metal materials, only 1 / 30 of the current is required to achieve the same effect as a metal-based Peltier device.

[0038] Compared to existing CMOS processes, only one additional photolithography and etching process is required to remove the gate insulation layer between the dummy gate and the semiconductor substrate. In the polysilicon patterning process and the P-type and N-type ion implantation processes, only the layout design needs to be modified, without the need for additional photolithography processes. The embodiments of this application are fully compatible with existing CMOS processes, do not introduce special materials and processes, and are fully feasible. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 FIG. 4 shows a top view of an on-chip Peltier cooling device in an embodiment of the present application.

[0040] Figure 2A cross-sectional view of an on-chip Peltier cooling device in one embodiment of the present application is shown.

[0041] Figure 3 A schematic diagram of a three-state control gate in an embodiment of the present application is shown.

[0042] Figure 4 FIG. 4 shows a top view of an on-chip Peltier cooling device in another embodiment of the present application.

[0043] Figure 5 FIG. 4 shows a top view of an on-chip Peltier cooling device in another embodiment of the present application.

[0044] Figure 6 A cross-sectional view of an on-chip Peltier cooling device in another embodiment of the present application is shown.

[0045] Figure 7 FIG. 4 shows a top view of an on-chip Peltier cooling device in another embodiment of the present application.

[0046] Figure 8 A flow chart of a method for manufacturing an on-chip Peltier cooling device in one embodiment of the present application is shown.

[0047] Figure 9(a)-Figure 9(e) A structural schematic diagram of each step of a method for manufacturing an on-chip Peltier cooling device in an embodiment of the present application is shown.

[0048] Figure 10 A flow chart of a method for manufacturing an on-chip Peltier cooling device in another embodiment of the present application is shown.

[0049] Figure 11 A structural schematic diagram of performing P-type injection in a method for manufacturing an on-chip Peltier cooling device in another embodiment of the present application is shown.

[0050] Figure 12 A structural schematic diagram of performing N-type implantation in a method for manufacturing an on-chip Peltier cooling device in another embodiment of the present application is shown. DETAILED DESCRIPTION

[0051] In the following description, many technical details are provided to help readers better understand this application. However, those skilled in the art will understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented.

[0052] Several different embodiments are given below based on the different features of the present invention. The specific elements and arrangements in the present invention are for simplification, but the present invention is not limited to these embodiments. For example, the description of forming a first element on a second element may include an embodiment in which the first element is in direct contact with the second element, and also includes an embodiment in which an additional element is formed between the first element and the second element so that the first element and the second element are not in direct contact. In addition, for the sake of simplicity, the present invention is represented by repeated element symbols and / or letters in different examples, but it does not mean that there is a specific relationship between the various embodiments and / or structures described. It must be understood that when a layer is "on" other layers or substrates, it may mean directly on other layers or substrates, or it may mean that other layers are sandwiched between other layers or substrates.

[0053] Example 1

[0054] In one embodiment of the present application, an on-chip Peltier cooling device is disclosed. Figure 1 A top view of an on-chip Peltier cooling device 100 is shown. Device 100 includes: a first-type well region 110 located in a semiconductor substrate (not shown); a polysilicon gate 111 and a dummy gate located on the surface of the semiconductor substrate; a first-type doped region 113 located in the first-type well region 110; and a second-type doped region 114 located in the first-type well region 110. Polysilicon gate 111 is located between two dummy gates. In some embodiments, polysilicon gate 111 and the dummy gates may be parallel to each other; in some embodiments, polysilicon gate 111 and the dummy gates may not be parallel to each other and may be spaced apart. The dummy gate is formed into a two-segment structure with a gap, including a first segment 1121 and a second segment 1122, with a gap 1123 between the first segment 1121 and the second segment 1122. Device 100 also includes: a first through-hole 1161 located above first segment 1121 and a second through-hole 1162 located above second segment 1122.

[0055] In one embodiment, the polysilicon gate and the dummy gate are formed in the same process step. To better account for the proximity effect, the spacing L between the polysilicon gate 111 and the dummy gate should be greater than a certain threshold to avoid affecting the threshold voltage of the transistor. For example, for a 40nm process, the spacing L is greater than 0.5 microns. For simplicity, only the first type doped region 113, dummy gate, through hole, and other structures on the left side are marked in the figure. In one embodiment, the structure on the right side of the figure is the same or similar to that on the left side.

[0056] The first type doping region 113 at least overlaps with the orthographic projection area of the first section 1121 of the dummy gate on the semiconductor substrate, and the first section 1121 of the dummy gate is doped with the first type. The second type doping region 114 at least overlaps with the orthographic projection area of the polysilicon gate 111 and the second section 1122 of the dummy gate on the semiconductor substrate, and the second section 1122 of the dummy gate is doped with the second type. Figure 1 As shown, the second type doping region 114 is located in most areas of the first type well region 110, and the first type doping region 113 is located in the remaining small area of the first type well region 110. The polysilicon gate 111 and the second section 1122 of the dummy gate are formed on part of the second type doping region 114, and the first section 1121 of the dummy gate is formed on part of the first type doping region 113. In one embodiment, the first type is N-type and the second type is P-type. The device 100 forms a P-type doping region in the N-type well region, and the P-type doping region is used as the source region and the drain region, respectively, to form a PMOS transistor structure. It should be noted that Figure 1 The middle dashed box 115 is the active area of the device 100 , and the surrounding area is where shallow trench isolation (STI) is formed.

[0057] In one embodiment, a gate insulating layer is provided between the polysilicon gate 111 and the semiconductor substrate, and no gate insulating layer is provided between a portion of the two-stage dummy gate structure away from the spacer 1123 and the semiconductor substrate.

[0058] It should be understood that the device 100 in this embodiment also has multiple layers of metal interconnection lines for interconnecting with the through holes, which will not be described in detail here.

[0059] Figure 2 FIG. 1 shows a simplified cross-sectional view of the on-chip Peltier cooling device 100 along the AA′ direction. It should be noted that Figure 2 middle Figure 1 Part of the structure is simplified. It should be noted that Figure 2 Sidewalls are formed around the dummy gates 1121 and 1122, and silicide is formed on the surfaces of the dummy gates 1121 and 1122 and the well regions 110 and 113. This is well known to those skilled in the art and will not be described in detail here. In one embodiment, a high level is applied to the through hole 1161, and a low level or ground is applied to the through hole 1162. Current (as shown by the arrow in the figure) flows from the through hole 1161 through the first section 1121 of the dummy gate to the first type doped region 113. The first section 1121 of the dummy gate and the first type doped region 113 are both N-type doped, and the carrier is electron e - , carrier e -The direction of current is from the first type doping region 113 to the first segment 1121. The current flows from the first type doping region 113 to the second type doping region 114, and from the second type doping region 114 to the second segment 1122 of the dummy gate. The second type doping region 114 and the second segment 1122 are both P-type doped, and the carriers are holes h + , carrier h + The heat flows from the second-type doped region 114 to the second segment 1122. Inside the device 100, the heat flow is in the direction of carrier flow. Therefore, the heat flow is sequentially from the first-type doped region 113 to the first segment 1121 and from the second-type doped region 114 to the second segment 1122, that is, from the inside of the device to the surface, thereby achieving heat dissipation and cooling.

[0060] In other embodiments, the device 100 further includes: a first tri-state control gate connected to the first through hole 1161 and a second tri-state control gate connected to the second through hole 1162. The structure of the tri-state control gate is as follows: Figure 3 As shown, the output end of the tri-state control gate is connected to the through hole, and the two input ends are respectively connected to the control signal and the enable signal. Specifically, the output end M of the first tri-state control gate is connected to the first through hole 1161, and the first input end and the second input end of the first tri-state control gate are respectively connected to the first control signal CTL(M) and the first enable signal EN(M). The output end N of the second tri-state control gate is connected to the second through hole 1162, and the first input end and the second input end of the second tri-state control gate are respectively connected to the second control signal CTL(N) and the second enable signal EN(N).

[0061] In one embodiment, different signal controls are implemented on the tri-state control gate to realize the normal mode, cooling mode, and heating mode of the device 100. As shown in Table 1 below, when the first enable signal EN(M) and the second enable signal EN(N) are both low (0), the device is in normal mode, that is, the M and N terminals are both in high impedance state, there is no current, and the device is in normal working mode. When the first enable signal EN(M) and the second enable signal EN(N) are both high (1) and the first control signal CTL(M) is low (0), and the second control signal CTL(N) is high (1), the device is in cooling mode, that is, current flows from the M terminal to the N terminal, realizing the heat dissipation and cooling function as described above. When the first enable signal EN(M) and the second enable signal EN(N) are both high (1) and the second control signal CTL(N) is low (0), and the first control signal CTL(M) is high (1), the device is in heating mode, that is, the current flows from the N terminal to the M terminal. In contrast to the cooling mode, the heat flow flows from the surface of the device to the inside, achieving the heating function. Wherein, "-" in Table 1 represents a high level or a low level, that is, in normal mode, the first enable signal EN(M) and the second enable signal EN(N) are both low (0), the three-state control gate is not open, and the first control signal CTL(M) and the second control signal CTL(N) do not matter whether they are high or low. It should be understood that the operating mode of the device 100 can be selected according to actual conditions. For example, when the chip is not overheating, the normal operating mode can be selected to maximize performance; when the chip is threatened by overheating, it can be switched to the cooling mode to reduce the junction temperature and return to the safe operating temperature range. When the chip is in a low temperature environment, the heating mode can be activated to ensure normal operation.

[0062] Table 1: Device control mode using tri-state control gates

[0063] CTL(M) CTL(N) EN(M) EN(N) Normal mode - - 0 0 Cooling mode 0 1 1 1 Heating mode 1 0 1 1

[0064] Example 2

[0065] Figure 4 A top view of an on-chip Peltier device 200 in another embodiment is shown. The device 200 includes a second-type well region 210 located in a semiconductor substrate (not shown), a polysilicon gate 211 and a dummy gate located on the surface of the semiconductor substrate, a second-type doped region 213 located in the second-type well region 210, and a first-type doped region 214 located in the second-type well region 210. The dummy gate is formed into a two-segment structure with a gap, including a first segment 2121 and a second segment 2122, with a gap 2123 between the first segment 2121 and the second segment 2122. The device 200 also includes a first through-hole 2161 located above the first segment 2121 and a second through-hole 2162 located above the second segment 2122.

[0066] The second type doping region 213 at least overlaps with the orthographic projection area of the first section 2121 of the dummy gate on the semiconductor substrate. The first type doping region 214 at least overlaps with the orthographic projection area of the polysilicon gate 211 and the second section 2122 of the dummy gate on the semiconductor substrate. Figure 4 As shown, the first type doping region 214 is located in most areas of the second type well region 210, and the second type doping region 213 is located in the remaining small area of the second type well region 210. The polysilicon gate 211 and the second section 2122 of the dummy gate are formed on part of the first type doping region 214, and the first section 2121 of the dummy gate is formed on part of the second type doping region 213. In one embodiment, the first type is N-type and the second type is P-type. The device 200 forms an N-type doping region in the P-type well region, and the N-type doping region is used as the source region and the drain region, respectively, to form an NMOS transistor structure. It should be noted that Figure 4 The middle dashed box 215 is the active area of the device 200 , and the surrounding area is where shallow trench isolation (STI) is formed.

[0067] In this embodiment, the cross-sectional structure of the device 200 along the BB' direction is similar to the cross-sectional structure of the device 100 along the AA' direction (ie, Figure 2 ) is similar, and its working principle is the same as the embodiment described above, which will not be described in detail here. In this embodiment, the direction of heat flow is from the inside of the device to the surface, thereby achieving heat dissipation and cooling.

[0068] Example 3

[0069] Figure 5 FIG1 shows a top view of an on-chip Peltier device 300 in another embodiment. The device 300 includes a first component 301 and a second component 302. Component 301 is a PMOS transistor, and its structure can be referred to FIG1 . Figure 1 Component 302 is an NMOS transistor, and its structure can be referred to Figure 4 shown.

[0070] Component 301 includes a first type well region, a first polysilicon gate and a first dummy gate, component 302 includes a second type well region, a second polysilicon gate and a second dummy gate, and the second segment of the first dummy gate in component 301 is connected to the second segment of the corresponding second dummy gate in component 302.

[0071] The first type doped region at least overlaps with the orthographic projection area of the first segment of the first dummy gate in component 301 on the semiconductor substrate, and the orthographic projection area of the first segment of the second polysilicon gate and the second dummy gate in component 302 on the semiconductor substrate. Furthermore, the first segment of the first dummy gate is doped with the first type. In one embodiment, the area covered by the first type doped region is equal to the area of the second type well region. The second type doped region at least overlaps with the orthographic projection area of the second segment of the second dummy gate in component 302 on the semiconductor substrate, and the orthographic projection area of the second segment of the first polysilicon gate and the first dummy gate in component 301 on the semiconductor substrate. Furthermore, the second segment of the second dummy gate is doped with the second type. In one embodiment, the area covered by the second type doped region is equal to the area of the first type well region.

[0072] Figure 6 FIG shows a simplified cross-sectional view of the on-chip Peltier cooling device 300 along the CC' direction. It should be noted that Figure 6 middle Figure 5 The current direction, carrier direction and heat flow direction of the device in this embodiment are as follows: Figure 6 As shown, its working principle is the same as that of the embodiment described above and will not be described in detail here. The direction of heat flow in this embodiment is from the inside of the device to the surface, thereby achieving heat dissipation and cooling.

[0073] Example 4

[0074] Figure 7 FIG1 shows a top view of an on-chip Peltier device 400 in another embodiment. The device 400 includes a first component 401 and a second component 402. Components 401 and 402 are both PMOS transistors. Figure 1 Components 401 and 402 both include a first type well region, a polysilicon gate, and a dummy gate, and the first section of the dummy gate in component 401 is connected to the first section of the dummy gate in component 402.

[0075] In this embodiment, the cross-sectional structure of the device 400 along the DD' direction is similar to the cross-sectional structure of the device 300 along the CC' direction (ie, Figure 6 ) is similar, and its working principle is the same as the embodiment described above, which will not be described in detail here. In this embodiment, the direction of heat flow is from the inside of the device to the surface, thereby achieving heat dissipation and cooling.

[0076] Example 5

[0077] This application also discloses a method for manufacturing an on-chip Peltier cooling device. Figure 8 A flow chart showing a method of making a product, which can form, for example, Figure 1 and Figure 4 The devices 100, 200 shown are combined Figure 9(a) to Figure 9(e)In describing this method, it should be noted that Figure 9(a) to Figure 9(e) Corresponding to a cross section of the device 100 along the EE' direction or the device 200 along the FF' direction, the method includes the following steps:

[0078] In step 801, referring to FIG9(a), a gate insulating layer 920 is formed on a first type well region 910 in a semiconductor substrate (not shown), a patterned photoresist 930 is formed in the gate insulating layer 920, and the gate insulating layer 920 is etched so that the gate insulating layer 920 exposes a portion of the first type well region.

[0079] In step 802, as shown in FIG9(b), polysilicon 940 is formed on the first type well region 910, and the polysilicon 940 is etched to form a polysilicon gate and a dummy gate, as shown in FIG9(c). In addition, the method further includes removing the gate insulating layer outside the polysilicon gate region. The dummy gate is formed into a two-stage structure with a gap, wherein the portion of the two-stage structure away from the gap does not have a gate insulating layer between it and the semiconductor substrate, and the gap is located in the exposed portion of the first type well region.

[0080] In step 803, as shown in FIG9(d), a patterned photoresist 950 is formed on the first-type well region 910. P-type ion implantation is performed on the first-type well region 910 to form a first-type doped region in the first-type well region 910. The first-type doped region at least overlaps with the orthographic projection of the first segment of the dummy gate on the semiconductor substrate. Furthermore, the first segment of the dummy gate is doped with the first type. Next, the patterned photoresist 950 is removed.

[0081] In step 804, as shown in FIG9(e), a patterned photoresist 960 is formed on the first-type well region 910. N-type ion implantation is performed on the first-type well region 910 to form a second-type doped region in the first-type well region 910. The second-type doped region at least overlaps with the orthographic projection of the polysilicon gate and the second segment of the dummy gate on the semiconductor substrate. Furthermore, the second segment of the dummy gate is doped with the second type. Next, the patterned photoresist 960 is removed.

[0082] Step 805 , forming a first through hole above the first segment and a second through hole above the second segment.

[0083] In this embodiment, compared with the existing CMOS process, only one photolithography and etching process needs to be added to remove the gate insulation layer between the dummy gate and the semiconductor substrate. In the polysilicon patterning process and the P-type and N-type ion implantation processes, only the design of the graphics in the layout needs to be modified, and no additional photolithography process needs to be added.

[0084] Example 6

[0085] This application also discloses a method for manufacturing an on-chip Peltier cooling device. Figure 10 A flow chart showing a method of making a product, which can form, for example, Figure 5 The device 300 shown is combined with Figures 11 and 12 The method is described, and the method comprises the following steps:

[0086] Step 1001: forming a gate insulating layer on a first-type well region and a second-type well region in a semiconductor substrate, wherein the gate insulating layer exposes a portion of the first-type well region and a portion of the second-type well region.

[0087] In step 1002, a first polysilicon gate and a first dummy gate are formed on the first type well region, and a second polysilicon gate and a second dummy gate are formed on the second type well region, wherein the first dummy gate and the second dummy gate are respectively formed as two-segment structures with a gap, wherein there is no gate insulating layer between a portion of the two-segment structure away from the gap and the semiconductor substrate, and the gap is located at the exposed portion of the first type well region and the portion of the second type well region.

[0088] In one embodiment, the second segment of the first dummy gate is connected to the second segment of the second dummy gate.

[0089] Step 1003: Form a first-type doped region in the semiconductor substrate. The first-type doped region at least overlaps with an orthographic projection of the first segment of the first dummy gate on the semiconductor substrate, and with an orthographic projection of the second polysilicon gate and the first segment of the second dummy gate on the semiconductor substrate. Furthermore, the first segment of the first dummy gate is doped with the first type.

[0090] Step 1004: Form a second-type doped region in the semiconductor substrate. The second-type doped region at least overlaps with an orthographic projection of the second segment of the second dummy gate on the semiconductor substrate, and an orthographic projection of the first polysilicon gate and the second segment of the first dummy gate on the semiconductor substrate. Furthermore, the second segment of the second dummy gate is doped with the second type.

[0091] refer to Figure 11 As shown, Figure 11 (a) and Figure 11 (b) Schematic diagram of the structure in which P-type ion implantation is performed in the PMOS transistor 301 and the NMOS transistor 302. Figure 12 As shown, Figure 12 (a) and Figure 12(b) Schematic diagram of the structure of performing N-type ion implantation in PMOS transistor 301 and NMOS transistor 302, respectively. In traditional CMOS processes, only P-type ion implantation is required to form PMOS transistors, and only N-type ion implantation is required to form NMOS transistors. However, in the present application, P-type ion implantation is performed in the P-type well region when performing P-type ion implantation in the N-type well region, and N-type ion implantation is performed in the N-type well region when performing N-type ion implantation in the P-type well region, respectively, to form Peltier structures in the PMOS transistor and NMOS transistor, thereby achieving heat dissipation and cooling. The P-type and N-type ion implantation processes of this embodiment only require modification of the pattern design in the layout, without the need for additional photolithography processes.

[0092] Step 1005 : forming a first through hole above the first segment of the first dummy gate and forming a second through hole above the first segment of the second dummy gate.

[0093] According to the data of commercial semiconductor cooling chips, the temperature difference between the two ends of a chip with an area of about 8mmX8mm can reach 67℃ under a current of 2.5A and a voltage of 0.85V. According to the ratio, if a circuit with an area of 100umX100um on the chip needs to implement the cooling effect by introducing the method of this application, the required current is 2.5 / (8*8*10*10)=0.39mA. If only a temperature difference of about 20℃ is required, then only 0.12mA of current is needed. Even if it is 1mm 2 To achieve this effect on a chip of this size, the required current is only 12mA and the power required is 10mW. Considering that the height of the P+ / N+ polysilicon in the chip is much less than 4mm, the heat conduction path is much shorter, and the actual thermal efficiency should be even better than this estimate. Utilizing this principle, significant accelerated cooling of the chip's junction temperature can be achieved with negligible additional power consumption.

[0094] It should be noted that in this patent application, relational terms such as first and second, etc., are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. Without further limitation, an element specified by the phrase "comprising a" does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element. In this patent application, reference to performing an action in accordance with an element means performing the action in accordance with at least that element, including two situations: performing the action in accordance with that element alone, and performing the action in accordance with that element and other elements. Expressions such as "plurality," "multiple times," and "many" include "two," "twice," "two kinds," and "more than two," "more than two times," and "more than two kinds."

[0095] All documents mentioned in this specification are considered to be included in their entirety in the disclosure of this application so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above description is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.

[0096] In some cases, the actions or steps recited in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. Additionally, the processes depicted in the accompanying drawings do not necessarily require the particular order shown or sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. An on-chip Peltier cooling device, characterized in that: include: a first type well region located in the semiconductor substrate; a polysilicon gate and a dummy gate located on the surface of the semiconductor substrate, wherein the dummy gate is formed into a two-stage structure with a gap, wherein a portion of the two-stage structure away from the gap has no gate insulating layer between it and the semiconductor substrate; a first-type doped region located in the first-type well region, the first-type doped region at least overlapping with an orthographic projection area of the first segment of the dummy gate on the semiconductor substrate; a second-type doped region located in the first-type well region, the second-type doped region at least overlapping with an orthographic projection area of the polysilicon gate and the second segment of the dummy gate on the semiconductor substrate; A first through hole is located above the first segment and a second through hole is located above the second segment.

2. The on-chip Peltier cooling device according to claim 1, characterized in that: Also includes: A first three-state control gate connected to the first through hole and a second three-state control gate connected to the second through hole, wherein the output end of the first three-state control gate is connected to the first through hole, the first input end and the second input end of the first three-state control gate are respectively connected to a first control signal and a first enable signal, the output end of the second three-state control gate is connected to the second through hole, and the first input end and the second input end of the second three-state control gate are respectively connected to a second control signal and a second enable signal.

3. The on-chip Peltier cooling device according to claim 2, characterized in that: The device includes a normal mode, a cooling mode and a heating mode, wherein when the first and second enable signals are both low, the device is in the normal mode; when the first and second enable signals are both high and the first control signal is low, and the second control signal is high, the device is in the cooling mode; when the first and second enable signals are both high and the second control signal is low, and the first control signal is high, the device is in the heating mode.

4. The on-chip Peltier cooling device according to claim 1, characterized in that: A region of the first section of the dummy gate close to the spacer is doped with a first type of doping.

5. The on-chip Peltier cooling device according to claim 1, characterized in that: A region of the second section of the dummy gate close to the spacer is doped with a second type of doping.

6. The on-chip Peltier cooling device according to claim 1, characterized in that: The distance between the polysilicon gate and the dummy gate is greater than 0.5 microns.

7. An on-chip Peltier cooling device, characterized in that: include: A first type well region and a second type well region adjacent to each other in a semiconductor substrate; a first polysilicon gate and a first dummy gate located above the first type well region, and a second polysilicon gate and a second dummy gate located above the second type well region, wherein the first dummy gate and the second dummy gate are respectively formed into a two-segment structure with a gap, wherein a portion of the two-segment structure away from the gap has no gate insulating layer between the semiconductor substrate, and the second segment of the first dummy gate is connected to the second segment of the second dummy gate; a first-type doped region located in the semiconductor substrate, the first-type doped region at least overlapping with an orthographic projection area of the first segment of the first dummy gate on the semiconductor substrate, and an orthographic projection area of the second polysilicon gate and the first segment of the second dummy gate on the semiconductor substrate, and the first segment of the first dummy gate is doped with the first type; a second-type doped region located in the semiconductor substrate, the second-type doped region at least overlapping with an orthographic projection area of the second segment of the second dummy gate on the semiconductor substrate, and an orthographic projection area of the first polysilicon gate and the second segment of the first dummy gate on the semiconductor substrate, and the second segment of the second dummy gate is doped with the second type; A first through hole is located above the first segment of the first dummy gate, and a second through hole is located above the first segment of the second dummy gate.

8. The on-chip Peltier cooling device according to claim 7, characterized in that: The area covered by the first type doping region is equal to the area of the second type well region.

9. The on-chip Peltier cooling device according to claim 7, characterized in that: The area covered by the second type doping region is equal to the area of the first type well region.

10. A method for manufacturing an on-chip Peltier cooling device, characterized in that: include: forming a gate insulating layer on the first type well region in the semiconductor substrate, wherein the gate insulating layer exposes a portion of the first type well region; forming a polysilicon gate and a dummy gate on the first-type well region, wherein the dummy gate is formed into a two-stage structure with a gap, wherein a portion of the two-stage structure away from the gap has no gate insulating layer between it and the semiconductor substrate, and the gap is located in the exposed portion of the first-type well region; forming a first-type doped region in the first-type well region, wherein the first-type doped region at least overlaps with an orthographic projection area of the first segment of the dummy gate on the semiconductor substrate, and the first segment of the dummy gate is doped with the first type; forming a second-type doped region in the first-type well region, wherein the second-type doped region at least overlaps with an orthographic projection area of the polysilicon gate and the second segment of the dummy gate on the semiconductor substrate, and the second segment of the dummy gate is doped with the second type; A first through hole is formed above the first segment and a second through hole is formed above the second segment.

11. A method for manufacturing an on-chip Peltier cooling device, characterized in that: include: forming a gate insulating layer on the first type well region and the second type well region in the semiconductor substrate, wherein the gate insulating layer exposes a portion of the first type well region and a portion of the second type well region; forming a first polysilicon gate and a first dummy gate on the first type well region and forming a second polysilicon gate and a second dummy gate on the second type well region, wherein the first dummy gate and the second dummy gate are respectively formed into a two-segment structure with a gap, wherein a portion of the two-segment structure away from the gap has no gate insulating layer between it and the semiconductor substrate, and the gap is located in the exposed portion of the first type well region and the portion of the second type well region; forming a first-type doped region in the semiconductor substrate, the first-type doped region at least overlapping with an orthographic projection area of the first segment of the first dummy gate on the semiconductor substrate, and an orthographic projection area of the second polysilicon gate and the first segment of the second dummy gate on the semiconductor substrate, and the first segment of the first dummy gate is doped with the first type; forming a second-type doped region in the semiconductor substrate, the second-type doped region at least overlapping with an orthographic projection area of the second segment of the second dummy gate on the semiconductor substrate, and an orthographic projection area of the first polysilicon gate and the second segment of the first dummy gate on the semiconductor substrate, and the second segment of the second dummy gate is doped with the second type; A first through hole is formed over the first segment of the first dummy gate and a second through hole is formed over the first segment of the second dummy gate.

12. The method for manufacturing an on-chip Peltier cooling device according to claim 11, wherein: The second section of the first dummy gate is connected to the second section of the second dummy gate.

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