A radar power supply and distribution system based on time sequence control

Abstract

The application provides a radar power supply and distribution system based on timing control, which comprises three hardware parts of array power supply, wave control unit and power amplifier assembly and instruction control software; the instruction control software sends an enabling instruction to the array power supply, the enabling instruction is divided into a first-level enabling instruction and a second-level enabling instruction according to the system timing sequence; the instruction control software sends a third control signal to the wave control unit, the wave control unit sends a fourth control signal to the power amplifier assembly after processing the received third control signal; after receiving the enabling instruction, the array power supply starts to output corresponding voltage signals to supply power to the wave control unit and the power amplifier assembly. The radar power supply and distribution system of the application adopts the combination of array power supply hardware protection circuit and upper-level instruction software, can prevent the system power supply timing disorder caused by software failure, and can effectively ensure the correct and reliable operation of the power supply and distribution system.

Description

Technical Field

[0001] This invention belongs to the field of radar power supply and distribution, and relates to a radar power supply and distribution system based on timing control. Background Technology

[0002] With the gradual strengthening of my country's military science and technology capabilities, the radar industry in all fields of land, sea, air, and space has flourished in recent years, and the demand for radar products is increasing daily. The main components of a radar array are the beam control unit, the power amplifier assembly, and the array power supply. As the "heart" of the system's energy, the radar array power supply powers both the beam control unit and the power amplifier assembly, requiring extremely high reliability, as well as features such as multi-channel isolated output, applicability to pulse loads, and strict power supply timing requirements.

[0003] The FPGA chip in the beam control unit needs a certain amount of time to start up, and the power amplifier component needs to start working according to the control signal output after the beam control unit has started up. Therefore, the power supply of the array system needs to ensure the voltage required by the beam control unit first.

[0004] In addition, the gate of the power amplifier chip in current power amplifier components is generally powered by a negative voltage, while the drain is generally powered by a positive high voltage. There are also extremely strict power supply timing requirements between them. When turning on, the drain supply voltage must be established later than the gate supply voltage; when turning off, the drain supply voltage must be established earlier than the gate supply voltage. Otherwise, the power amplifier chip of the component may be damaged.

[0005] To address this, many researchers have focused on the internal power amplifier components. Patent applications CN201820473882.7 (a power module capable of positive and negative voltage timing control) and CN201910391971.6 (a gallium nitride power amplifier timing protection power supply device) present two timing solutions for the power amplifier's internal power supply. Their general principle is the same: the gate signal is compared with a threshold signal to drive a power switching device (PMOS) connected in series in the drain power supply circuit. The amplitude of the gate signal determines whether the power switching transistor is turned on to supply power to the drain, thereby achieving timing control. The above methods basically solve the power supply timing problem of a single power amplifier component, but there are also some application limitations: 1. Power switching devices have a short-circuit failure mode. Once a short-circuit failure occurs, the drain power supply is no longer controlled by the power switch and will continue to supply power to the drain of the component, which will damage the component's power amplifier chip; 2. In actual system applications, power amplifier components often need to be used in conjunction with a beam control unit. One beam control unit controls the operation of dozens or even hundreds of power amplifier components. Therefore, when applying radar systems, it is not only necessary to consider the internal timing of the power amplifier components, but also to consider the coordination of the power supply timing between the beam control unit and the power amplifier components. Summary of the Invention

[0006] To address the challenges of existing technologies, this invention provides a radar power supply and distribution system based on timing control, comprising three main hardware components: an array power supply, a beam control unit, and a power amplifier assembly, as well as command control software. The command control software sends an enable command to the array power supply, which is divided into a first-level enable command and a second-level enable command according to the system timing sequence. The command control software sends a third control signal to the beam control unit, which processes the received third control signal and then sends a fourth control signal to the power amplifier assembly. Upon receiving the enable command, the array power supply turns on and outputs the corresponding voltage signal to power the beam control unit and the power amplifier assembly.

[0007] Furthermore, the voltage signal includes a first-level voltage signal and a second-level voltage signal; the first-level voltage signal includes a first-level positive voltage signal and a first-level negative voltage signal, and the second-level voltage signal is specifically a second-level positive voltage signal; the array power supply sends the first-level positive voltage signal to the wave control unit, and sends the first-level positive voltage signal, the negative voltage signal and the second-level positive voltage signal to the corresponding power amplifier components.

[0008] Furthermore, the array power supply includes an input timing protection circuit, an output interlock circuit, a first-stage voltage conversion circuit, and a second-stage voltage conversion circuit. The input timing protection circuit receives the first-stage enable command and the second-stage enable command sent sequentially by the command control software. After processing the first-stage enable command and the second-stage enable command, it outputs a first control signal and a second control signal to the first-stage voltage conversion circuit and the second-stage voltage conversion circuit, respectively. The first-stage voltage conversion circuit processes the first control signal and outputs a first-stage voltage signal. The second-stage voltage conversion circuit processes the second control signal and outputs a second-stage voltage signal.

[0009] Furthermore, the output interlock circuit receives the first sampled voltage from the first-stage voltage conversion circuit, generates a sampled voltage after voltage division by resistors, compares the sampled voltage with the reference voltage, and if the sampled voltage is lower than the reference voltage, outputs an interlock protection signal to the second-stage voltage conversion circuit, and the second-stage voltage conversion circuit stops outputting the second-stage voltage signal.

[0010] Furthermore, the input timing protection circuit includes a positive input line and an input ground. Resistors R1 and R2 are connected in series between the positive input line and the input ground. A capacitor C1 is connected in parallel across resistor R2, and the two ends of capacitor C1 are connected to the switching transistor circuit. Resistors R3 and R4 are also connected in series between the positive input line and the input ground. The connection point between resistors R3 and R4 is connected to an isolation controller. The isolation controller simultaneously receives a second-level enable command, processes it, and outputs a second control signal. The second-level enable circuit is connected in series after the switching transistor circuit. The second-level enable circuit includes resistors R3 and R4 and the isolation controller.

[0011] Furthermore, the isolation control device is specifically an optocoupler.

[0012] Furthermore, the switching transistors in the switching transistor circuit are NMOS or PMOS.

[0013] Furthermore, the output interlock circuit includes resistors R6, R7, and R8. Resistors R6 and R7 are connected in series, with one end grounded and the other end connected to the first sampling voltage A1. The connection point of resistors R6 and R7 is connected to the non-inverting input of comparator N5A. The inverting input of comparator N5A is connected to the reference voltage. The power supply terminal of comparator N5A is connected to voltage VCC. The output terminal of comparator N5A outputs an interlock protection signal. One end of resistor R8 is connected to voltage VCC, and the other end is connected to the output terminal of comparator N5A.

[0014] Furthermore, the output interlock circuit includes an operational amplifier.

[0015] Compared with the prior art, the present invention has the following technical effects:

[0016] (1) The radar power supply and distribution system based on timing control described in this invention adopts a combination of array power supply hardware protection circuit and upper-level instruction software, which can prevent system power supply timing disorder caused by software failure and effectively ensure the correct and reliable operation of the power supply and distribution system.

[0017] (2) The input timing protection circuit of the array power supply in this invention uses a switching transistor circuit connected in series on the input positive line circuit to realize hardware interlocking of the first-level enable and the second-level enable control, which can prevent power supply timing errors caused by instruction software timing disorder.

[0018] (3) The input timing protection circuit in this invention has a simple principle and achieves timing protection with fewer components.

[0019] (4) The output interlock circuit of the array power supply in this invention achieves the output interlock between the first-level voltage signal and the second-level voltage signal with only a few components, which can prevent voltage timing disorder caused by faults in the array power supply itself.

[0020] (5) The present invention comprehensively utilizes a variety of timing protection methods to eliminate the problem of equipment damage caused by timing errors, and greatly improves the safety and reliability of the radar system. Attached Figure Description

[0021] Figure 1 This is a block diagram illustrating the working principle of a radar power supply and distribution system based on timing control, according to an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of one implementation method of the source input timing protection circuit for the array current according to an embodiment of the present invention.

[0023] Figure 3This is a schematic diagram of a second implementation method of the input timing protection circuit for the array power supply according to an embodiment of the present invention.

[0024] Figure 4 This is a schematic diagram of the implementation method of the array power output interlock circuit in an embodiment of the present invention.

[0025] Figure 5 This is a schematic diagram of the circuit structure of the array power supply according to an embodiment of the present invention. Detailed Implementation

[0026] This application proposes a system-level radar array power supply timing solution, which comprehensively considers the system timing control and protection measures of the wave control unit and component power amplifier module on the array, and provides a system application implementation method to meet the timing control and protection requirements of radar system power supply and distribution.

[0027] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0028] As attached Figure 1 As shown, a radar power supply and distribution system based on timing control in this application embodiment includes three main hardware components: array power supply, wave control unit, and power amplifier assembly, as well as command control software.

[0029] The command control software sends an enable command to the array power supply. This enable command is divided into a first-level enable command and a second-level enable command according to the system timing sequence. The command control software sends a third control signal to the beam control unit. The beam control unit processes the received third control signal and then sends a fourth control signal to the power amplifier assembly. The enable commands include power-on commands and power-off commands.

[0030] Upon receiving the enable command, the array power supply starts outputting the corresponding voltage signal to power the beam control unit and power amplifier components. The array power supply must ensure correct voltage setup timing to guarantee the safe and reliable operation of the entire radar system. The voltage signal includes a first-level voltage signal and a second-level voltage signal; the first-level voltage signal includes a first-level positive voltage signal and a first-level negative voltage signal, and the second-level voltage signal is specifically a second-level positive voltage signal. The array power supply sends the first-level positive voltage signal to the beam control unit and sends the first-level positive voltage signal, the negative voltage signal, and the second-level positive voltage signal to the corresponding power amplifier components.

[0031] like Figure 5As shown, the array power supply includes an input timing protection circuit, an output interlock circuit, a first-stage voltage conversion circuit, and a second-stage voltage conversion circuit, all implemented in hardware to prevent damage to subsequent electrical equipment caused by power supply output timing errors when the command control software malfunctions.

[0032] The input timing protection circuit receives a first-level enable command and a second-level enable command sequentially sent by the command control software. After processing the first-level enable command and the second-level enable command, it outputs a first control signal and a second control signal to the first-level voltage conversion circuit and the second-level voltage conversion circuit, respectively. The first-level voltage conversion circuit processes the first control signal and outputs a first-level voltage signal, and the second-level voltage conversion circuit processes the second control signal and outputs a second-level voltage signal. The output interlock circuit receives a first sampled voltage from the first-level voltage conversion circuit, generates a sampled voltage after voltage division by resistors, compares the sampled voltage with the reference voltage, and if the sampled voltage is lower than the reference voltage, it outputs an interlock protection signal to the second-level voltage conversion circuit, and the second-level voltage conversion circuit stops outputting the second-level voltage signal.

[0033] The array power supply provides power to both the beam control unit and the power amplifier assembly. There are usually three types of output voltage. In this embodiment, we take the commonly used +5V, -5V, and +28V as examples. The beam control unit only uses +5V, while the power amplifier assembly uses +5V, -5V, and +28V.

[0034] like Figure 2 As shown, the input timing protection circuit uses a switching transistor circuit connected in series in the positive input circuit to realize the control function of the first-level enable instruction (±5V enable); the second-level enable instruction (+28V enable) is located after the first-level enable control switch transistor, and the input timing control is realized in hardware.

[0035] The implementation method of the input timing protection circuit is as follows: Figure 2 and Figure 3 As shown, the circuit includes a positive input line and an input ground. Resistors R1 and R2 are connected in series between the positive input line and the input ground. A capacitor C1 is connected in parallel across resistor R2. The two ends of capacitor C1 are connected to the switching transistor circuit. Figure 2 Specifically, this refers to the first switching transistor circuit loop; resistors R3 and R4 are also connected in series between the positive input line and the input ground, and the connection point between resistors R3 and R4 is connected to an isolation control device. Figure 2 and Figure 3 The isolation controller uses an optocoupler N1; the isolation controller also receives the second-level enable control command, processes it, and outputs the second control signal; the second-level enable circuit (including resistors R3 and R4 and the isolation controller) is connected in series after the switching transistor circuit.

[0036] The switching transistors in the switching circuit can be power devices such as NMOS and PMOS. For example... Figure 2 and Figure 3 As shown, the switching transistor circuit can be either a first switching transistor circuit or a second switching transistor circuit. The first switching transistor V1 in the first switching transistor circuit is an NMOS transistor. The implementation method is as follows: Figure 2 As shown, the second switch V2 in the second switching transistor circuit is a PMOS implementation method as follows: Figure 3 As shown.

[0037] The specific process of input timing protection is as follows:

[0038] The array power supply receives the input voltage and the first-stage enable command. Figure 2 and Figure 3 After receiving the ±5V enable command, the positive input line charges capacitor C1 through resistor R1, and the switching transistor slowly turns on; once the switching transistor turns on, the first-stage voltage conversion circuit starts, and the first-stage voltage signal (±5V voltage) immediately begins to be converted and output; when the isolation controller N1 receives the second-stage enable command (… Figure 2 and Figure 3 After the +28V enable command is executed, the isolation controller N1 is turned on and sends out the second control signal. Figure 2 and Figure 3 The +28V control signal activates the second-stage voltage conversion circuit, initiating the conversion of the second-stage voltage signal (+28V) to the output. This circuit implements input timing protection in hardware. Even if the upstream software system sends out incorrectly timed voltage signals, the power supply will not execute according to the incorrect timing, ensuring the correct timing of the output circuit.

[0039] like Figure 4 As shown, the output interlock circuit includes resistors R6, R7, and R8. Resistors R6 and R7 are connected in series, with one end grounded and the other end connected to the first sampling voltage A1. The connection point of resistors R6 and R7 is connected to the non-inverting input of comparator N5A. The inverting input of comparator N5A is connected to the reference voltage. The power supply terminal of comparator N5A is connected to voltage VCC. The output terminal of comparator N5A outputs an interlock protection signal. One end of resistor R8 is connected to voltage VCC, and the other end is connected to the output terminal of comparator N5A.

[0040] The output interlock circuit uses a comparator circuit to determine the +5V and -5V output voltage values ​​respectively. It compares the sampled voltage (after resistor division) with the reference voltage. If the sampled voltage is lower than the reference voltage, the comparator flips the output interlock protection signal, immediately shutting down the PWM controller of the second-stage voltage conversion circuit (in this embodiment, a +28V voltage conversion circuit), thus quickly shutting down the output of the second-stage voltage signal. This output interlock circuit can also use an operational amplifier instead of a comparator to achieve the same function.

[0041] According to the system's operating sequence, the ±5V shared by the beam control unit and the power amplifier assembly is set as the first-level voltage signal, which is controlled by the system's first-level enable command; the +28V power supply used by the power amplifier assembly for transmission, i.e., the power supply from the drain of the power amplifier tube, is the second-level voltage signal, which is controlled by the system's second-level enable command.

[0042] The beam control unit receives the third control signal from the command control software. After processing the third control signal, it distributes the fourth control signal, which includes the beam control signal and the timing control signal, to the corresponding power amplifier component, thereby controlling the power amplifier components of the entire radar array to perform transmission and reception according to the command.

[0043] The power requirements of the beam control unit are small, typically requiring only one positive voltage, such as +5V or +3.3V. Its core component is generally a digital control chip such as an FPGA, which contains control software. It takes a certain amount of time for the FPGA chip to start up and for the program to be loaded and ready before it can implement command control on the power amplifier components.

[0044] Power amplifier components typically use three voltage options. Common power amplifier components use +5V (or +3.3V) and -5V (or -3.3V) for receiving operations, and +28V (or +8V) for transmitting operations. Among them, -5V (or -3.3V) supplies power to the gate of the power amplifier chip, and +28V (or +8V) supplies power to the drain of the power amplifier chip, with strict power supply timing requirements.

[0045] The instruction sending sequence of the superior instruction system software is as follows:

[0046] When powering on, first send the first-level power-on command (±5V), then send the second-level power-on command (+28V); when powering off, first send the second-level power-off command (+28V), then send the first-level power-off command (±5V). Software is used to ensure the correct timing of the secondary power supply command inputs.

[0047] The above solutions can ensure the correctness of the radar power supply timing from multiple aspects, such as software command timing, power input timing control, and output voltage interlocking, thus guaranteeing the safe and reliable operation of the system.

[0048] The radar power supply and distribution system based on timing control described in this invention combines array power supply hardware protection circuitry with upper-level command software to prevent system power supply timing errors caused by software faults, effectively ensuring the correct and reliable operation of the power supply and distribution system. The input timing protection circuit of the array power supply uses a switching transistor circuit connected in series in the input line circuit to achieve hardware interlocking between the first-level and second-level enable control, preventing power supply timing errors caused by command software timing errors. The input timing protection circuit has a simple principle and achieves timing protection with a small number of components. The output interlocking circuit of the array power supply also achieves output interlocking between the first-level and second-level voltage signals with only a few components, preventing voltage timing errors caused by array power supply faults. The comprehensive application of multiple timing protection designs eliminates equipment damage caused by timing errors, greatly improving the safety and reliability of the radar system.

[0049] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0050] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0051] In the several embodiments provided in this application, it should be understood that the disclosed systems and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0052] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0053] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0054] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0055] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A radar power supply and distribution system based on timing control, characterized in that, It includes three main hardware components: array power supply, beam control unit, and power amplifier assembly, as well as command control software. The command control software sends an enable command to the array power supply, which is divided into a first-level enable command and a second-level enable command according to the system timing sequence. The command control software sends a third control signal to the beam control unit, and the beam control unit processes the received third control signal and sends a fourth control signal to the power amplifier assembly. After receiving the enable command, the array power supply starts outputting the corresponding voltage signal to power the beam control unit and the power amplifier assembly. The voltage signal includes a first-level voltage signal and a second-level voltage signal; the first-level voltage signal includes a first-level positive voltage signal and a first-level negative voltage signal, and the second-level voltage signal is specifically a second-level positive voltage signal; the array power supply sends the first-level positive voltage signal to the wave control unit, and sends the first-level positive voltage signal, the negative voltage signal and the second-level positive voltage signal to the corresponding power amplifier components; The array power supply includes an input timing protection circuit, an output interlock circuit, a first-stage voltage conversion circuit, and a second-stage voltage conversion circuit. The input timing protection circuit receives the first-level enable command and the second-level enable command sent sequentially by the command control software. After processing the first-level enable command and the second-level enable command, it outputs the first control signal and the second control signal to the first-level voltage conversion circuit and the second-level voltage conversion circuit, respectively. The first-level voltage conversion circuit processes the first control signal and outputs the first-level voltage signal. The second-level voltage conversion circuit processes the second control signal and outputs the second-level voltage signal.

2. The radar power supply and distribution system based on time-series control according to claim 1, characterized in that, The output interlock circuit receives the first sampled voltage from the first-stage voltage conversion circuit, generates a sampled voltage after voltage division by resistors, compares the sampled voltage with the reference voltage, and if the sampled voltage is lower than the reference voltage, it outputs an interlock protection signal to the second-stage voltage conversion circuit, and the second-stage voltage conversion circuit stops outputting the second-stage voltage signal.

3. The radar power supply and distribution system based on time-series control according to claim 2, characterized in that, The input timing protection circuit includes a positive input line and an input ground. Resistors R1 and R2 are connected in series between the positive input line and the input ground. A capacitor C1 is connected in parallel across resistor R2, and the two ends of capacitor C1 are connected to the switching transistor circuit. Resistors R3 and R4 are also connected in series between the positive input line and the input ground. The connection point between resistors R3 and R4 is connected to an isolation controller. The isolation controller simultaneously receives a second-level enable command, processes it, and outputs a second control signal. The second-level enable circuit is connected in series after the switching transistor circuit. The second-level enable circuit includes resistors R3 and R4 and the isolation controller.

4. The radar power supply and distribution system based on time-series control according to claim 3, characterized in that, The isolation control device is specifically an optocoupler.

5. The radar power supply and distribution system based on time-series control according to claim 3, characterized in that, The switching transistor in the switching transistor circuit is an NMOS or a PMOS.

6. The radar power supply and distribution system based on time-series control according to claim 3, characterized in that, The output interlock circuit includes resistors R6, R7, and R8. Resistors R6 and R7 are connected in series, with one end grounded and the other end connected to the first sampling voltage A1. The connection point of resistors R6 and R7 is connected to the non-inverting input of comparator N5A. The inverting input of comparator N5A is connected to the reference voltage. The power supply terminal of comparator N5A is connected to voltage VCC. The output terminal of comparator N5A outputs an interlock protection signal. One end of resistor R8 is connected to voltage VCC, and the other end is connected to the output terminal of comparator N5A.

7. The radar power supply and distribution system based on time-series control according to claim 3, characterized in that, The output interlock circuit includes an operational amplifier.

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