A digital control system for three-level DC converters

Abstract

The present invention discloses a digital control system for a three-level DC converter. The digital control system includes a first subtractor, a second subtractor, a third subtractor, a fourth subtractor, a fifth subtractor, a sixth subtractor, a first adder, a first multiplier, a first PI controller, a second PI controller, a third PI controller, a fourth PI controller, a fifth PI controller, a sixth PI controller, a reverse given absolute value calculation module, a minimum value calculation module, a maximum value calculation module, a PWM generator, and a driver. The present invention implements bidirectional automatic switching control in any constant voltage, constant current, or constant power mode; utilizes the high-speed characteristics and parallel computing advantages of FPGAs to achieve rapid dynamic response; the switching time from positive 90% to negative 90% is shorter than that of conventional control methods, and the forward and reverse switching speeds are fast.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic power conversion, and in particular to a digital control system of a three-level direct current converter. Background Art

[0002] With the advancement of power electronics technology, various industries are demanding DC converters featuring high-voltage output, bidirectional operation, and fast response. Existing DC converters are generally unidirectional, two-level half-bridge or full-bridge bidirectional, or three-level half-bridge bidirectional. Unidirectional DC converters have relatively limited functionality. When outputting high voltage, the two-level structure imposes high voltage tolerances on individual switching devices, resulting in high dv / dt and high withstand voltage requirements. Three-level or cascaded three-level DC converters are more ideal, combining bidirectional and high-voltage output characteristics. The patent "A Three-Level DC Converter and Its Narrow Pulse Width Control Method" (CN 102510215A) proposes a method for handling narrow pulses in three-level control. The patent "A Three-Level Bidirectional DCDC Converter Control Method" (CN 110048612 A) utilizes a three-level I-shaped circuit with a symmetrical primary and secondary sides. Using the dual-side duty cycle plus phase-shift control strategy of the I-shaped three-level circuit, it achieves closed-loop control, bidirectional operation, and buck-boost. The patent "A three-level DC converter and its control system and control method" (CN 113517815 A) proposes a three-level converter with relatively complex structure and control, which realizes soft switching of some devices.

[0003] Traditional control methods for three-level DC converters are unable to meet the requirements of high-speed forward and reverse switching of three-level DC converters. The transient recovery time from sudden loading and unloading is long, making it difficult to meet the needs of test conditions with high dynamic response requirements. Summary of the Invention

[0004] In view of the defects of the prior art, the present invention provides a digital control system and method for a three-level DC converter, which solves the problems of the existing three-level DC converter control method such as the inability to automatically switch between charging and discharging, slow dynamic response and low control accuracy.

[0005] In order to solve the technical problem, the technical solution adopted by the present invention is: a digital control system for a three-level DC converter, comprising a first subtractor, a second subtractor, a third subtractor, a fourth subtractor, a fifth subtractor, a sixth subtractor, a first adder, a first multiplier, a first PI controller, a second PI controller, a third PI controller, a fourth PI controller, a fifth PI controller, a sixth PI controller, a reverse given absolute value calculation module, a minimum value calculation module, a maximum value calculation module, a PWM generator and a driver, the output voltage and the given voltage value of the three-level DC converter are connected to the first PI controller after passing through the first subtractor, the inductor current and the given current value of the three-level DC converter are connected to the second PI controller after passing through the second subtractor, the output voltage and output current of the three-level DC converter are both connected to the first multiplier, the output of the first multiplier and the given power value are connected to the third PI controller after passing through the third subtractor, the first PI controller, the second PI controller The first multiplier and the third PI controller are all connected to the minimum value calculation module; the inductor current and the given current value after the reverse given absolute value calculation module are both connected to the fourth subtractor, the fourth subtractor is connected to the fourth PI controller, the output of the first multiplier and the given power value after the reverse given absolute value calculation module are both connected to the fifth subtractor, the fifth subtractor is connected to the fifth PI controller, the fourth PI controller, the fifth PI controller, and the minimum value calculation module are all connected to the maximum value calculation module, the output of the maximum value calculation module is connected to the input end of the first adder, the other input end of the first adder is connected to the output current of the three-level DC converter, the output of the first adder is connected to an input end of the sixth subtractor, the inductor current of the three-level DC converter is connected to the other input end of the sixth subtractor, the output of the sixth subtractor is connected to the sixth PI controller, the sixth PI controller is connected to the PWM generator, and the PWM generator is connected to the switch tube of the three-level DC converter via the driver.

[0006] Furthermore, the output voltage of the three-level DC converter is connected to the inverting input terminal of the first subtractor, the voltage set value is connected to the positive input terminal of the first subtractor, the inductor current sampling point of the three-level DC converter is connected to the inverting input terminal of the second subtractor, the current set value is connected to the positive input terminal of the second subtractor, the output of the first multiplier is connected to the inverting input terminal of the third subtractor, the power set value is connected to the positive input terminal of the third subtractor, the current set value after the absolute value is inverted is connected to the positive input terminal of the fourth subtractor, the inductor current sampling point of the three-level DC converter is connected to the inverting input terminal of the fourth subtractor, the power set value after the absolute value is inverted is connected to the positive input terminal of the fifth subtractor, the output terminal of the first multiplier is connected to the inverting input terminal of the fifth subtractor, the output terminal of the first adder is connected to the positive input terminal of the sixth subtractor, and the inductor current sampling point is connected to the inverting input terminal of the sixth subtractor.

[0007] Further, the PI calculation result of the sixth PI controller is compared with the triangular waves Uc1 and Uc2 inside the PWM generator to generate waveforms S1, S2, S3, and S4 output to the three-level DC converter. If PI > Uc1, then S1 = 1 and S2 = 0; if PI < Uc1, S1 = 0 and S2 = 1; if PI > Uc2, then S4 = 1 and S3 = 0; if PI < Uc2, S3 = 1 and S4 = 0. Here, PI represents the PI calculation result of the sixth PI controller, that is, the calculated waveform. Uc1 and Uc2 have a phase difference of 180°. The generated waveforms S1 and S2 are complementary, and S3 and S4 are complementary. Then, the waveforms S1, S2, S3, and S4 are sent to the corresponding switching tubes of the three-level DC converter through a driver.

[0008] Further, the magnitude relationship between the output voltage UO of the DC converter and the load battery voltage UBAT determines whether the converter operates in the forward output or reverse feedback mode. Specifically: when the three-level DC converter is working, if the load battery voltage UBAT is less than the output voltage UO of the DC converter, the converter outputs forward; if the load battery voltage UBAT is greater than the output voltage UO of the DC converter, the converter performs reverse feedback.

[0009] Further, five control loops are formed using this system, namely: Voltage control loop: The output voltage, given voltage value, first subtractor, and first PI controller form the voltage control loop; Forward current control loop: The inductor current, given current value, second subtractor, and second PI controller form the forward current control loop; Forward power control loop: The output current, output voltage, first multiplier, given power value, third subtractor, and third PI controller form the forward power control loop; Reverse current control loop: The inductor current, given current value, reverse given absolute value calculation module, fourth subtractor, and fourth PI controller form the reverse current control loop; Reverse power control loop: The output current, output voltage, first multiplier, given power value, reverse given absolute value calculation module, fifth subtractor, and fifth PI controller form the reverse power control loop.

[0010] When the DC converter outputs forward, it is controlled by one of the voltage control loop, forward current control loop, and forward power control loop. That is, the converter operates stably on the control loop that reaches the steady state first. If the voltage control loop reaches the steady state first, the DC converter operates in the forward output constant voltage mode; if the forward current control loop reaches the steady state first, the DC converter operates in the forward output constant current mode; if the forward power control loop reaches the steady state first, the DC converter operates in the forward output constant power mode.

[0011] When the DC converter is in reverse feedback, it is controlled by one of the voltage control loop, reverse current control loop, and reverse power control loop. The DC converter first operates on the reverse current control loop or reverse power control loop that reaches stability first. That is, if the reverse current control loop reaches steady state first, the DC converter operates in reverse feedback constant current mode. If the reverse power control loop reaches steady state first, the DC converter operates in reverse feedback constant power mode. If neither can reach stability, the DC converter is controlled by the voltage control loop and operates in reverse feedback constant voltage state.

[0012] Furthermore, when the DC converter is in forward output, the duty cycle of the switch tube T1 is defined as the object. When the duty cycle D is greater than 0.5, the DC converter is in three-level mode and has four modes. At this time, UO=D*Udc, where UO represents the output voltage of the DC converter, Udc represents the input voltage of the DC converter, and D is the duty cycle.

[0013] When the duty cycle D is less than 0.5, the DC converter is in two-level mode with four modes. At this time, UO=D*Udc, where UO represents the output voltage of the DC converter, Udc represents the input voltage of the DC converter, and D is the duty cycle.

[0014] Furthermore, when the DC converter is in reverse feedback, the duty cycle is defined by the switch tube T2. When the duty cycle D is greater than 0.5, the DC converter is in a two-level mode with four modes. At this time, UO=(1-D)*Udc, where UO represents the output voltage of the DC converter, Udc represents the input voltage of the DC converter, and D is the duty cycle. When the duty cycle D is less than 0.5, the DC converter is in a three-level mode with four modes. At this time, UO=(1-D)*Udc, where UO represents the output voltage of the DC converter, Udc represents the input voltage of the DC converter, and D is the duty cycle.

[0015] Furthermore, this system is implemented based on FPGA.

[0016] The beneficial effects of the present invention are: realizing bidirectional automatic switching control in any constant voltage, constant current and constant power mode; utilizing the high-speed characteristics and parallel computing advantages of FPGA to achieve fast dynamic response; the switching time from positive 90% to negative 90% is shorter than that of conventional control methods, and the forward and reverse switching speed is fast. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 1 is a circuit diagram of an embodiment;

[0018] Figure 2 is the circuit schematic diagram of a three-level DC converter;

[0019] Figure 3 Schematic diagram of the driving waveform generation method;

[0020] Figure 4 The waveform of the DC converter is shown in the following figure when the output is forward and the duty cycle is D>0.5.

[0021] Figure 5 The modal diagram for mode M1 is when the output is positive and the duty cycle D>0.5;

[0022] Figure 6 The modal diagram for mode M2 ​​is shown in the case of forward output and duty cycle D>0.5.

[0023] Figure 7 The modal diagram for mode M3 is shown in the case of forward output and duty cycle D>0.5.

[0024] Figure 8 The modal diagram for mode M4 is shown in the case of forward output and duty cycle D>0.5.

[0025] Figure 9 The equivalent model diagram of the DC converter is shown in the figure below when the output is forward and the duty cycle D>0.5.

[0026] Figure 10 The waveform of the DC converter is shown in the following figure when the output is forward and the duty cycle is D<0.5.

[0027] Figure 11 The modal diagram for mode M1 is when the output is positive and the duty cycle D<0.5;

[0028] Figure 12 The modal diagram for mode M2 ​​is when the output is positive and the duty cycle D<0.5;

[0029] Figure 13 The modal diagram for mode M3 is shown in the case of positive output and duty cycle D<0.5.

[0030] Figure 14 The modal diagram for mode M4 is shown in the case of positive output and duty cycle D<0.5.

[0031] Figure 15 The equivalent model diagram of the DC converter is shown in the figure below when the output is forward and the duty cycle is D<0.5.

[0032] Figure 16 This is the waveform diagram of the DC converter under the condition of reverse feedback and duty cycle D>0.5.

[0033] Figure 17 This is the modal diagram for mode M1 under the condition of reverse feedback and duty cycle D>0.5;

[0034] Figure 18 This is the modal diagram for mode M2 ​​under the condition of reverse feedback and duty cycle D>0.5;

[0035] Figure 19 This is the modal diagram for mode M3 under the condition of reverse feedback and duty cycle D>0.5;

[0036] Figure 20 This is the modal diagram for mode M4 under the condition of reverse feedback and duty cycle D>0.5;

[0037] Figure 21 This is the equivalent model diagram of the DC converter under the condition of reverse feedback and duty cycle D>0.5;

[0038] Figure 22 This is the waveform diagram of the DC converter under the condition of reverse feedback and duty cycle D<0.5.

[0039] Figure 23 This is the modal diagram for mode M1 under the condition of reverse feedback and duty cycle D<0.5;

[0040] Figure 24 This is the modal diagram for mode M2 ​​under the condition of reverse feedback and duty cycle D<0.5;

[0041] Figure 25 This is the modal diagram for mode M3 under the condition of reverse feedback and duty cycle D<0.5;

[0042] Figure 26 This is the modal diagram for mode M4 under the condition of reverse feedback and duty cycle D<0.5;

[0043] Figure 27 This is the equivalent model diagram of the DC converter under the condition of reverse feedback and duty cycle D<0.5;

[0044] In the figure: 1. three-level DC converter, 2. power battery load, 3. first subtractor, 4. second subtractor, 5. third subtractor, 6. fourth subtractor, 7. fifth subtractor, 8. sixth subtractor, 9. first adder, 10. first multiplier, 11. first PI controller, 12. second PI controller, 13. third PI controller, 14. fourth PI controller, 15. fifth PI controller, 16. sixth PI controller, 17. minimum value calculation module, 19. maximum value calculation module, 20. reverse given absolute value calculation module, 21. PWM generation module, 22. driver. DETAILED DESCRIPTION

[0045] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0046] Example 1

[0047] This embodiment discloses a digital control system for a three-level DC converter. Figure 2 As shown, it includes four series-connected switch tubes T1-T4, capacitors C1 and C2 connected to the input end, a capacitor Cout connected to the output end, an inductor L and a power battery load BAT, and the junction between the capacitors C1 and C2 is connected to the zero point between the four series-connected switch tubes.

[0048] like Figure 1 As shown, the digital control system includes a first subtractor 3, a second subtractor 4, a third subtractor 5, a fourth subtractor 6, a fifth subtractor 7, a sixth subtractor 8, a first adder 9, a first multiplier 10, a first PI controller 11, a second PI controller 12, a third PI controller 13, a fourth PI controller 14, a fifth PI controller 15, a sixth PI controller 16, a reverse given absolute value calculation module 20, a minimum value calculation module 17, a maximum value calculation module 19, a PWM generator 21 and a driver 22. The three-level DC converter 1 The output voltage Uo and the given voltage value V_set are connected to the first PI controller 11 after passing through the first subtractor 3. The inductor current IL and the given current value I_set of the three-level DC converter 1 are connected to the second PI controller 12 after passing through the second subtractor 4. The output voltage Uo and the output current Io of the three-level DC converter 1 are both connected to the first multiplier 10. The output of the first multiplier 10 and the given power value P_set are connected to the third PI controller 13 after passing through the third subtractor 5. The first PI controller 11, the second PI controller 12, and the third PI controller The inductor current IL and the given current value -I_set obtained by the reverse given absolute value calculation module are both connected to the fourth subtractor 6, which is connected to the fourth PI controller 14. The output of the first multiplier 10 and the given power value -P_set obtained by the reverse given absolute value calculation module are both connected to the fifth subtractor 7, which is connected to the fifth PI controller 15. The fourth PI controller 14, the fifth PI controller 15, and the minimum value calculation module 17 are all connected to the maximum value calculation module 19. The output of the maximum value calculation module 19 is connected to the input of the first adder 9. The other input of the first adder 9 is connected to the output current Io of the three-level DC converter 1. The output of the first adder 9 is connected to an input of the sixth subtractor 8. The inductor current IL of the three-level DC converter 1 is connected to the other input of the sixth subtractor 8. The output of the sixth subtractor 8 is connected to the sixth PI controller 16. The sixth PI controller 16 is connected to the PWM generator 21. The PWM generator 21 is connected to the switch tube of the three-level DC converter via the driver 22.

[0049] This embodiment uses the set value minus the sampled value. Specifically, the output voltage Uo of the three-level DC converter 1 is connected to the inverting input terminal of the first subtractor 3, the voltage set value V_set is connected to the positive input terminal of the first subtractor 3, the inductor current sampling point of the three-level DC converter 1 is connected to the inverting input terminal of the second subtractor 4, the current set value is connected to the positive input terminal of the second subtractor 4, the output of the first multiplier 10 is connected to the inverting input terminal of the third subtractor 5, the power set value is connected to the positive input terminal of the third subtractor 5, the current set value after the absolute value is inverted is connected to the positive input terminal of the fourth subtractor 6, the inductor current sampling point of the three-level DC converter is connected to the inverting input terminal of the fourth subtractor 6, the power set value after the absolute value is inverted is connected to the positive input terminal of the fifth subtractor 7, the output terminal of the first multiplier 10 is connected to the inverting input terminal of the fifth subtractor 7, the output terminal of the first adder 9 is connected to the positive input terminal of the sixth subtractor 8, and the inductor current sampling point is connected to the inverting input terminal of the sixth subtractor 8.

[0050] In this embodiment, the control system is implemented using FPGA, and the high-speed characteristics and parallel computing advantages of FPGA are utilized to achieve fast dynamic response.

[0051] The process of digital control using this system is as follows:

[0052] S01), sampling the output voltage, output current and inductor current of the three-level DC converter to obtain an output voltage sampling value VO, an output current sampling value IO and an inductor current sampling value IL, and setting a voltage set value V_set, a current set value I_set and a power set value P_set;

[0053] S02), the voltage set value V_set is subtracted from the voltage sampling value VO, the current set value I_set is subtracted from the inductor current sampling value IL, and the power set value P_set is subtracted from the output power sampling value. The output power sampling value is obtained by multiplying the output voltage sampling value VO and the output current sampling value IO. The results of the above subtraction operations are all input into the PI controller for calculation. The PI calculation result is obtained by the minimum value calculation module to obtain the first minimum value;

[0054] S03), the current set value I_set and the power set value P_set are both subjected to an absolute value inversion operation, the inductor current set value I_set after the absolute value inversion is subtracted from the inductor current sampling value IL, and the power set value P_set after the absolute value inversion is subtracted from the output power sampling value. The output power sampling value is obtained by multiplying the output voltage sampling value VO and the output current sampling value IO. The results of the above subtraction operations are all input into the PI controller for calculation;

[0055] S04), obtain the maximum value of the first minimum value and the PI calculation result in step S03, perform an addition operation on this maximum value and the output current sampling value IO, subtract the inductor current sampling value IL from the result of the addition operation, and the result of the subtraction operation enters the PI controller for calculation. The PI calculation result enters the PWM generator;

[0056] S05), compare the PI calculation result in step S04) with the triangular waves Uc1 and Uc2 inside the PWM generator. Uc1 and Uc2 have a phase difference of 180°. As Figure 3 shown, if PI > Uc1, then S1 = 1, S2 = 0; if PI < Uc1, S1 = 0, S2 = 1; if PI > Uc2, then S4 = 1, S3 = 0; if PI < Uc2, TS3 = 1, S4 = 0; S1 and S2 are complementary, and S3 and S4 are complementary;

[0057] S06), send the generated waveforms S1, S2, S3, and S4 to the corresponding switching tubes of the three-level DC converter through the driver.

[0058] Five control loops can be formed using this system, which are respectively:

[0059] Voltage control loop: The output voltage Uo, the given voltage value V_set, the first subtractor 3, and the first PI controller 11 form the voltage control loop.

[0060] Forward current control loop: The inductor current IL, the given current value I_set, the second subtractor 4, and the second PI controller 12 form the forward current control loop.

[0061] Forward power control loop: The output current IO, the output voltage UO, the first multiplier 10, the given power value P_set, the third subtractor 5, and the third PI controller 13 form the forward power control loop.

[0062] Reverse current control loop: The inductor current IL, the given current value I_set, the reverse given absolute value calculation module 20, the fourth subtractor 6, and the fourth PI controller 14 form the reverse current control loop.

[0063] Reverse power control loop: The output current IO, the output voltage UO, the first multiplier 10, the given power value P_set, the reverse given absolute value calculation module 20, the fifth subtractor 7, and the fifth PI controller 15 form the reverse power control loop.

[0064] The relationship between the converter output voltage UO and the load battery voltage UBAT determines whether the converter operates in the forward output or reverse feedback mode. Specifically: when the three-level DC converter is working, when the load battery voltage UBAT is less than the output voltage UO, the converter outputs forward; when the load battery voltage UBAT is greater than the output voltage UO, the converter performs reverse feedback.

[0065] This system controls the drive waveform fed back to the three-level DC converter switch tube through five control loops, that is, changes the output of the three-level DC converter, thereby changing the working mode of the three-level DC converter.

[0066] The reverse current control loop and reverse power control loop automatically fail during the forward output of the converter:

[0067] During forward output, the output current IO and output voltage UO are positive, the power sample output by the first multiplier 10 is positive, and P_set is positive. The given power value from the reverse given absolute value calculation module 20 is negative, and after calculation by the fifth PI controller 15, the output is the minimum value that the FPGA can output. The minimum value calculation module 17 outputs the smallest output result among the voltage control loop, forward current control loop, and forward power control loop. If the given values ​​and sampled values ​​in the voltage control loop, forward current control loop, and forward power control loop are all positive, the minimum value that the FPGA can output will not be output. The minimum value calculation module 17 outputs a non-minimum value, and after passing through the maximum value calculation module 19, the reverse current control loop and the reverse power control loop automatically become invalid. During forward output, one of the voltage control loop, forward current control loop, and forward power control loop actually controls the converter output.

[0068] Voltage control loop, forward current control loop, and forward power control loop selection process:

[0069] When the output sampled value of any of the three control loops is greater than a given value, closed-loop regulation reduces the output, ultimately achieving steady state. When the output sampled value of any of the three control loops is less than a given value, closed-loop regulation increases the output. Ultimately, one control loop reaches steady state first. For the other two control loops that haven't reached steady state, the given value is greater than the sampled value, and the FPGA outputs the maximum value it can. After passing through minimum value calculation module 17, the two control loops that haven't reached steady state automatically become inoperative, and the converter stabilizes on the control loop that reaches steady state first.

[0070] The voltage control loop first reaches a steady-state converter working in the forward output constant voltage mode, the forward current control loop first reaches a steady-state converter working in the forward output constant current mode, and the forward power control loop first reaches a steady-state converter working in the forward output constant power mode.

[0071] The automatic failure process of the forward current control loop and the forward power control loop during reverse feedback of the converter:

[0072] When the load battery voltage UBAT in the DC converter 1 is greater than the output voltage UO, the converter reverses and the voltage control loop output sample value VO exceeds the voltage setpoint U_set, causing the voltage control loop output to approach a smaller value. When the output current IO is negative and the output voltage UO is positive, the power sample output by the first multiplier 10 is negative and the power setpoint P_set is positive, the forward power control loop output, after calculation by the third subtractor 5 and the third PI controller 13, reaches the maximum output value of the FPGA. When the inductor current IL is negative and the current setpoint I_set is positive, the forward current control loop output, after calculation by the second subtractor 4 and the second PI controller 12, reaches the maximum output value of the FPGA. The minimum value calculation module 17 outputs the smallest output of the voltage control loop, the forward current control loop, and the forward power control loop. The outputs of the forward current control loop and the forward power control loop are both the maximum output value of the FPGA and are not output by the minimum value calculation module 17, automatically becoming inoperative. In the reverse feedback state, only the output of the voltage control loop passes through the minimum value calculation module 17.

[0073] The switching process of the voltage control loop, reverse current control loop, and reverse power control loop during reverse feedback of the converter:

[0074] In the reverse current control loop, the given current value I_set is positive and becomes negative after passing through the reverse given absolute value calculation module 20, and the inductor current sampling value IL is negative. After calculation by the fourth subtractor 6 and the fourth PI controller 14, a calculated value is output. In the reverse power control loop, the given current value P_set is positive and becomes negative after passing through the reverse given absolute value calculation module 20, the inductor current sampling value IL is negative, the output voltage sampling value VO is positive, and the power sampling output by the first multiplier 10 is negative. After calculation by the fifth subtractor 7 and the fifth PI controller 15, a calculated value is output. Whichever of the power sampling value and the inductor current sampling value reaches the value obtained by inverting the absolute value of the given value first reaches the steady state first. If neither the reverse current control loop nor the reverse power control loop can reach steady state, then the given value is less than the sampled value, and the minimum value that the FPGA can output will be output. The output of the voltage control loop can pass through the minimum value calculation module 17. At this time, after the output of the voltage control loop passes through the minimum value calculation module 17 and is output, the three are input into the maximum value calculation module 19, and the output of the voltage control loop is output. The reverse current control loop and the reverse power control loop become ineffective, and the converter is controlled and operated by the voltage control loop, operating in a reverse feedback constant voltage state. As previously described, whichever of the power sampled value and the inductor current sampled value reaches the value after the absolute value of the given value is inverted first, will determine which of the reverse current control loop and the reverse power control loop reaches steady state first. If the reverse current control loop reaches steady state first, the controller operates in reverse feedback constant current mode. If the reverse power control loop reaches steady state first, the controller operates in reverse feedback constant power mode.

[0075] The modal analysis of the three-level DC converter is performed below.

[0076] There are two situations (1) and (2) when the DC converter outputs in the forward direction:

[0077] (1) Figures 4 to 9 The waveform diagram, modal diagram and equivalent model diagram of the DC converter are shown in the figure below when the output is forward and the duty cycle is D>0.5; Figure 4 For the waveform diagram at this time, Figures 5 to 8 The modal diagrams for modes M1, M2, M3, and M4 are: Figure 9 This is the equivalent model diagram of the DC converter.

[0078] In the forward output mode, the switch tube T1 is the duty cycle definition object. When the duty cycle D>0.5, it is in the three-level mode with four modes, specifically:

[0079] Mode M1: Switches T1 and T4 are turned on, and the converter outputs forward energy to store inductor energy.

[0080] Mode M2: Switches T1 and T3 are turned on, and the converter's forward output inductor continues to flow.

[0081] Mode M3: Switches T1 and T4 are turned on, and the converter outputs forward energy to the inductor.

[0082] Mode M4: Switches T2 and T4 are turned on, and the converter's forward output inductor continues to flow.

[0083] In the case of forward output and duty cycle D>0.5, the equivalent model of the DC converter is as follows: Figure 8 As shown in the figure, Ton is the on-time of the switch tube T1, Toff is the off-time of the switch tube T1, and T is the carrier period;

[0084] Then the duty cycle D=Ton / T, T=Ton+Toff.

[0085] exist Figure 4 In the equation, according to the volt-second law: (Ton-Toff)*(Udc-UO)= Toff*(UO-0.5Udc)*2;

[0086] From the above three equations, we can get UO=D*Udc.

[0087] (2) Figures 10 to 15 The waveform diagram, modal diagram and equivalent model diagram of the DC converter are shown in the following figure when the output is forward and the duty cycle is D<0.5; Figure 10 For the waveform diagram at this time, Figures 11 to 14 is the modal diagram for M1, M2, M3, and M4, Figure 15 It is the equivalent model diagram of the DC converter.

[0088] In the forward output mode, the switch tube T1 is the duty cycle definition object. When D < 0.5, it is in the two-level mode with four modes, specifically:

[0089] Mode M1: Switches T1 and T3 are turned on, and the converter outputs forward energy to store inductor energy.

[0090] Mode M2: Switches T2 and T3 are turned on, and the converter's forward output inductor continues to flow.

[0091] Mode M3: Switches T2 and T4 are turned on, and the converter outputs forward energy to store inductor energy.

[0092] Mode M4: Switches T2 and T3 are turned on, and the converter's forward output inductor continues to flow.

[0093] In the case of forward output and duty cycle D<0.5, the equivalent model of the DC converter is as follows: Figure 15 As shown in the figure, Ton is the on-time of the switch tube T1, Toff is the off-time of the switch tube T1, and T is the carrier period;

[0094] Then duty cycle D=Ton / T; T=Ton+Toff;

[0095] exist Figure 10 In the equation, according to the volt-second law: 2*Ton*(0.5Udc-UO)=(Toff-Ton)*UO;

[0096] From the above three equations, we can get UO=D*Udc.

[0097] There are two situations (3) and (4) when the DC converter is in reverse feedback:

[0098] (3) Figures 16 to 21 The waveform diagram, modal diagram and equivalent model diagram of the DC converter are shown in the following figure under the condition of reverse feedback and duty cycle D>0.5; Figure 16 For the waveform diagram at this time, Figures 17 to 20 The modal diagrams for modes M1, M2, M3, and M4 are: Figure 21 This is the equivalent model diagram of the DC converter.

[0099] In reverse feedback, the switch tube T2 is the duty cycle definition object. When D>0.5, it is a two-level mode with four modes, specifically:

[0100] Mode M1: Switches T1 and T3 are turned on, and the converter's reverse feedback inductor continues current;

[0101] Mode M2: Switches T2 and T3 are turned on, and the converter reversely feeds back the inductor to store energy;

[0102] Mode M3: Switches T2 and T4 are turned on, and the converter's reverse feedback inductor continues current;

[0103] Mode M4: Switches T2 and T3 are turned on, and the converter reversely feeds back the inductor to store energy.

[0104] In the case of reverse feedback and duty cycle D>0.5, the equivalent model of the DC converter is as follows: Figure 21 As shown in the figure, Ton is the on-time of the switch tube T2, Toff is the off-time of the switch tube T2, and T is the carrier period. Then the duty cycle D=Ton / T; T=Ton+Toff;

[0105] exist Figure 16 In the equation, according to the volt-second law: (Ton-Toff)*UO= Toff*(0.5Udc-UO)*2;

[0106] From the above three equations, we can get UO=(1-D)*Udc.

[0107] (4) Figures 22 to 27 The waveform diagram, modal diagram and equivalent model diagram of the DC converter are shown in the following figure under the condition of reverse feedback and duty cycle D<0.5; Figure 22 For the waveform diagram at this time, Figures 23 to 26 The modal diagrams for modes M1, M2, M3, and M4 are: Figure 27 This is the equivalent model diagram of the DC converter.

[0108] In reverse feedback, the switch tube T2 is the duty cycle definition object. When D < 0.5, it is in three-level mode with four modes, specifically:

[0109] Mode M1: Switches T1 and T4 are turned on, and the converter's reverse feedback inductor continues current;

[0110] Mode M2: Switches T1 and T3 are turned on, and the converter reversely feeds back the inductor to store energy;

[0111] Mode M3: Switches T1 and T4 are turned on, and the converter's reverse feedback inductor continues current;

[0112] Mode M4: Switches T2 and T4 are turned on, and the converter reversely feeds back the inductor to store energy;

[0113] In the case of reverse feedback and duty cycle D<0.5, the equivalent model of the DC converter is as follows: Figure 27 As shown,

[0114] Ton is the on-time of switch T2, Toff is the off-time of switch T2, T is the carrier period, then duty cycle D=Ton / T; T= Ton+Toff;

[0115] exist Figure 22 In the equation, according to the volt-second law: Ton *(UO-0.5Udc)*2=(Toff-Ton)* (Udc- UO);

[0116] From the above three equations, we can get UO=(1-D)*Udc.

[0117] The present invention utilizes output current superposition to make dynamic response faster.

[0118] The output current sampling value IO is superimposed on the output of the maximum value calculation module (19) through the first adder (9).

[0119] From the analysis in Figure 6, we can see that when the converter is outputting in the forward direction, the output current sampling value IO is positive. If the load energy absorption suddenly increases, IO increases, and the PI value output by the sixth PI controller 16 increases after superposition, the forward output duty cycle increases, and the converter output increases, quickly compensating for the output voltage drop caused by the increase in load energy absorption, and quickly recovering from output voltage fluctuations. If the load energy absorption suddenly decreases, IO decreases, and the PI value output by the sixth PI controller 16 decreases after superposition, the forward output duty cycle decreases, and the converter output decreases, quickly alleviating the output voltage overshoot caused by the sudden decrease in load energy absorption, and quickly recovering from output voltage fluctuations.

[0120] When the converter is providing reverse feedback, the output current sampled value IO is negative. If the load output energy suddenly increases, the reverse feedback current increases, and IO decreases. After superposition, the PI value output by the sixth PI controller 16 decreases, the reverse feedback duty cycle increases, and the converter's reverse feedback energy increases, quickly mitigating the output voltage overshoot caused by the increase in load output energy and rapidly recovering from output voltage fluctuations. If the load output energy suddenly decreases, the reverse feedback current decreases, and IO increases. After superposition, the PI value output by the sixth PI controller 1) increases, the reverse feedback duty cycle decreases, and the converter's reverse feedback energy decreases. This quickly mitigates the output voltage drop caused by the sudden decrease in load output energy and rapidly recovers from output voltage fluctuations.

[0121] In addition, all control loops and calculations generated by T1, T2, T3, and T4 are completed by FPGA. FPGA operates in parallel, all calculations are performed synchronously according to the clock, all data are output synchronously, and the control loop runs at a high speed.

[0122] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention fall within the protection scope of the present invention.

Claims

1. A digital control system for a three-level DC converter, characterized in that: The invention comprises a first subtractor (3), a second subtractor (4), a third subtractor (5), a fourth subtractor (6), a fifth subtractor (7), a sixth subtractor (8), a first adder (9), a first multiplier (10), a first PI controller (11), a second PI controller (12), a third PI controller (13), a fourth PI controller (14), a fifth PI controller (15), a sixth PI controller (16), a reverse given absolute value calculation module (20), a minimum value calculation module (17), a maximum value calculation module (19), a PWM generator (21) and a driver ( 22), the output voltage and the given voltage value of the three-level DC converter are connected to the first PI controller (11) after passing through the first subtractor (3), the inductor current and the given current value of the three-level DC converter are connected to the second PI controller (12) after passing through the second subtractor (4), the output voltage and the output current of the three-level DC converter are both connected to the first multiplier (10), the output of the first multiplier (10) and the given power value are connected to the third PI controller (13) after passing through the third subtractor (5), the first PI controller (11), the second PI controller (12), and the third PI controller (13) are all connected. connected to the minimum value calculation module (17); the inductor current and the given current value after the reverse given absolute value calculation module (20) are connected to the fourth subtractor (6), the fourth subtractor (6) is connected to the fourth PI controller (14), the output of the first multiplier (10) and the given power value after the reverse given absolute value calculation module (20) are connected to the fifth subtractor (7), the fifth subtractor (7) is connected to the fifth PI controller (15), the fourth PI controller (14), the fifth PI controller (15), and the minimum value calculation module (17) are all connected to the maximum value calculation module (19), The output of the maximum value calculation module (19) is connected to the input end of the first adder (9), the other input end of the first adder (9) is connected to the output current of the three-level DC converter, the output of the first adder (9) is connected to one input end of the sixth subtractor (8), the inductor current of the three-level DC converter is connected to the other input end of the sixth subtractor (8), the output of the sixth subtractor (8) is connected to the sixth PI controller (16), the sixth PI controller (16) is connected to the PWM generator (21), and the PWM generator (21) is connected to the switch tube of the three-level DC converter via the driver.

2. The digital control system of a three-level DC converter according to claim 1, characterized in that: The output voltage of the three-level DC converter is connected to the inverting input terminal of the first subtractor (3), the voltage set value is connected to the non-inverting input terminal of the first subtractor (3), the inductor current sampling point of the three-level DC converter is connected to the inverting input terminal of the second subtractor (4), the current set value is connected to the non-inverting input terminal of the second subtractor (4), the output of the first multiplier (10) is connected to the inverting input terminal of the third subtractor (5), the power set value is connected to the non-inverting input terminal of the third subtractor (5), the current set value after absolute value inversion is connected to the non-inverting input terminal of the fourth subtractor (6), the inductor current sampling point of the three-level DC converter is connected to the inverting input terminal of the fourth subtractor (6), the power set value after absolute value inversion is connected to the non-inverting input terminal of the fifth subtractor (7), the output terminal of the first multiplier is connected to the inverting input terminal of the fifth subtractor (7), the output terminal of the first adder (9) is connected to the non-inverting input terminal of the sixth subtractor (8), and the inductor current sampling point is connected to the inverting input terminal of the sixth subtractor (8).

3. The digital control system of a three-level DC converter according to claim 1 or 2, characterized in that: The PI calculation result of the sixth PI controller (16) is compared with the triangular waves Uc1 and Uc2 inside the PWM generator to generate waveforms S1, S2, S3, and S4 output to the three-level DC converter. Specifically, if PI > Uc1, then S1 = 1 and S2 = 0; if PI < Uc1, S1 = 0 and S2 = 1; if PI > Uc2, then S4 = 1 and S3 = 0; if PI < Uc2, S3 = 1 and S4 = 0. Here, PI represents the PI calculation result of the sixth PI controller, that is, the calculated waveform. Uc1 and Uc2 have a phase difference of 180°. The generated waveforms S1 and S2 are complementary, and S3 and S4 are complementary. Then, the waveforms S1, S2, S3, and S4 are sent to the corresponding switching tubes of the three-level DC converter through drivers.

4. The digital control system of a three-level DC converter according to claim 1 or 2, characterized in that: The relationship between the output voltage UO of the DC converter and the load battery voltage UBAT determines whether the converter operates in the forward output or reverse feedback mode. Specifically: when the three-level DC converter is working, when the load battery voltage UBAT is less than the output voltage UO of the DC converter, the converter outputs forward; when the load battery voltage UBAT is greater than the output voltage UO of the DC converter, the converter performs reverse feedback.

5. The digital control system for a three-level DC converter according to claim 4, characterized in that: Five control loops are formed using this system, namely: Voltage control loop: The output voltage, given voltage value, first subtraction, and first PI controller constitute the voltage control loop; Forward current control loop: The inductor current, given current value, second subtractor, and second PI controller constitute the forward current control loop; Forward power control loop: The output current, output voltage, first multiplier, given power value, third subtractor, and third PI controller constitute the forward power control loop; Reverse current control loop: The inductor current, given current value, reverse given absolute value calculation module, fourth subtractor, and fourth PI controller constitute the reverse current control loop; Reverse power control loop: The output current, output voltage, first multiplier, given power value, reverse given absolute value calculation module, fifth subtractor, and fifth PI controller constitute the reverse power control loop. When the DC converter is in forward output, it is controlled by one of the voltage control loop, forward current control loop, and forward power control loop. That is, the converter works stably on the control loop that reaches steady state first. If the voltage control loop reaches steady state first, the DC converter works in forward output constant voltage mode. If the forward current control loop reaches stability first, the DC converter works in forward output constant current mode. If the forward power control loop reaches steady state first, the DC converter works in forward output constant power mode. When the DC converter is in reverse feedback, it is controlled by one of the voltage control loop, reverse current control loop, and reverse power control loop. The DC converter first operates on the reverse current control loop or reverse power control loop that reaches stability first. That is, if the reverse current control loop reaches steady state first, the DC converter operates in reverse feedback constant current mode. If the reverse power control loop reaches steady state first, the DC converter operates in reverse feedback constant power mode. If neither can reach stability, the DC converter is controlled by the voltage control loop and operates in reverse feedback constant voltage state.

6. The digital control system of a three-level DC converter according to claim 4, characterized in that: When the DC converter is in forward output, the duty cycle is defined by the switch tube T1. When the duty cycle D is greater than 0.5, the DC converter is in a three-level mode with four modes. At this time, UO=D*Udc, where UO represents the output voltage of the DC converter, Udc represents the input voltage of the DC converter, and D represents the duty cycle. When the duty cycle D is less than 0.5, the DC converter is in a two-level mode with four modes. At this time, UO=D*Udc, where UO represents the output voltage of the DC converter, Udc represents the input voltage of the DC converter, and D represents the duty cycle.

7. The digital control system of a three-level DC converter according to claim 4, characterized in that: When the DC converter is in reverse feedback, the duty cycle of the switch tube T2 is defined. When the duty cycle D is greater than 0.5, the DC converter is in a two-level mode with four modes. At this time, UO=(1-D)*Udc, where UO represents the output voltage of the DC converter, Udc represents the input voltage of the DC converter, and D is the duty cycle. When the duty cycle D is less than 0.5, the DC converter is in three-level mode with four modes. At this time, UO=(1-D)*Udc, where UO represents the output voltage of the DC converter, Udc represents the input voltage of the DC converter, and D is the duty cycle.

8. The digital control system of a three-level DC converter according to claim 1 or 2, characterized in that: This system is implemented based on FPGA.

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