Image sensor using a triple readout method for phase detection autofocus and image sensing pixels

Abstract

The present disclosure relates to an image sensor using a triple readout method for phase detection autofocus and image sensing pixels. An imaging device includes a plurality of photodiodes arranged in a photodiode array to generate charge in response to incident light. The plurality of photodiodes includes first and second photodiodes. A shared floating diffusion region receives charge transferred from the first and second photodiodes. An analog-to-digital converter (ADC) performs a first ADC conversion in response to the charge in the shared floating diffusion region after a reset operation to generate a reference reading. The ADC then performs a second ADC conversion in response to the charge transferred from the first photodiode to the shared floating diffusion region to generate the first half of a phase detection autofocus (PDAF) reading. The ADC then performs a third ADC conversion in response to the combination of the charge transferred from the second photodiode and the charge previously transferred from the first photodiode in the shared floating region to generate a full image reading.

Description

Technical Field

[0001] The present disclosure relates generally to image sensors, and particularly, but not exclusively, to image sensors including phase detection autofocus and image sensing pixels. Background Art

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, and the like) through both device architecture design and image acquisition processing. The technology used to manufacture image sensors continues to advance rapidly. For example, the demand for higher resolution and lower power consumption drives further miniaturization and integration of these devices.

[0003] A typical complementary metal oxide semiconductor (CMOS) image sensor operates in response to image light from an external scene being incident on the image sensor. The image sensor includes a pixel array having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charges after absorbing the image light. The image charges generated by the pixel light can be measured as analog output image signals on column bit lines that vary according to the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, and the image charge is read out from the column bit lines as an analog signal and converted into a digital value to generate a digital image (i.e., image data) representing the external scene. Summary of the invention

[0004] One aspect of the present disclosure relates to an imaging device, comprising: a plurality of photodiodes arranged in a photodiode array to generate charge in response to incident light, wherein the plurality of photodiodes include a first photodiode and a second photodiode; a shared floating diffusion region configured to receive charge transferred from the first and second photodiodes; and an analog-to-digital converter (ADC) configured to perform a first ADC conversion in response to the charge in the shared floating diffusion region after a reset operation to produce a reference reading, wherein the ADC is next configured to perform a second ADC conversion in response to the charge transferred from the first photodiode to the shared floating diffusion region to produce a first half of a phase detection autofocus (PDAF) reading, wherein the ADC is then configured to perform a third ADC conversion in response to the charge transferred from the second photodiode combined with the charge previously transferred from the first photodiode in the shared floating region to produce a full image reading.

[0005] Another aspect of the present disclosure relates to an imaging system including: a plurality of photodiodes arranged in a photodiode array to generate charge in response to incident light, wherein the plurality of photodiodes includes a first photodiode and a second photodiode; a shared floating diffusion region configured to receive charge transferred from the first and second photodiodes; a control circuit coupled to the photodiode array to control the operation of the photodiode array; and a readout circuit coupled to the photodiode array to read out signals from the photodiode array through a plurality of column bit lines, wherein the readout circuit includes an analog-to-digital converter (ADC) configured to perform a first ADC conversion in response to the charge in the shared floating diffusion region after a reset operation to generate a reference reading, wherein the ADC is next configured to perform a second ADC conversion in response to the charge transferred from the first photodiode to the shared floating diffusion region to generate the first half of a phase detection autofocus (PDAF) reading, and wherein the ADC is then configured to perform a third ADC conversion in response to the combination of the charge transferred from the second PDAF photodiode and the charge previously transferred from the first photodiode in the shared floating region to generate a full image reading. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the accompanying drawings, in which like reference numerals refer to like components throughout the various views unless otherwise specified.

[0007] Figure 1 Illustrate an example of an imaging system including a photodiode array in accordance with the teachings of the present invention.

[0008] Figure 2 Illustrate an example of a photodiode array in accordance with the teachings of the present disclosure.

[0009] Figure 3 Illustrate an example schematic diagram of a pixel circuit included in an imaging system having a photodiode array in accordance with the teachings of the present invention.

[0010] Figure 4 Illustrate an example timing diagram in accordance with the teachings of the present invention, which illustrates various signals in a pixel circuit included in an imaging system including a photodiode array, generating signals from the photodiode array and reading out the signals by an analog-to-digital converter.

[0011] Throughout several views of the accompanying drawings, corresponding reference characters indicate corresponding components. Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to assist in improving the understanding of the various embodiments of the present invention. Additionally, common but well-understood elements that are useful or necessary in a commercially viable embodiment are typically not depicted to facilitate a clearer view of these various embodiments of the present invention. Detailed Description

[0012] Examples are described herein that relate to imaging systems including pixel arrays having phase detection autofocus and image sensing photodiodes. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, those skilled in the relevant art will recognize that the techniques described herein may be practiced without one or more of the specific details or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0013] References to "one example" or "one embodiment" throughout this specification mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrases "in one example" or "in one embodiment" throughout this specification are not necessarily all referring to the same example. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0014] For ease of description, spatial relative terms may be used herein, such as "under", "below", "above", "beneath", "over", "upper", "top", "bottom", "left", "right", "center", "middle", etc., to describe the relationship of one element or feature to another (other) element or feature, as illustrated in the figures. It will be understood that, in addition to the orientation depicted in the figures, spatial relative terms are also intended to encompass different orientations of the device during use or operation. For example, if the device in the figures is rotated or flipped, then an element described as "under", "below", or "beneath" other elements or features will be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "beneath" can encompass both the orientation of over and under. The device may be oriented in other ways (rotated ninety degrees or in other orientations) and the spatial relative descriptors used herein interpreted accordingly. Additionally, it will also be understood that when an element is referred to as being "between" two other elements, it may be the only element between the two other elements, or there may also be one or more intervening elements.

[0015] Throughout this specification, a number of technical terms are used. These terms shall have their ordinary meanings within the relevant art, unless explicitly defined herein or the context of their use otherwise clearly indicates. It should be noted that throughout this document, element names and symbols may be used interchangeably (e.g., Si and silicon); however, both have the same meaning.

[0016] As will be discussed, various examples of imaging systems that describe a photodiode array having phase detection autofocus (PDAF) and image sensing photodiodes are presented. In various examples, the imaging system includes an imaging device having a plurality of photodiodes arranged in a photodiode array that generate charge in response to incident light. In various examples, all of the photodiodes in the photodiode array can be used for both phase detection autofocus and image sensing. Thus, all of the photodiodes in the photodiode array can have the same type of microlens and color filter. In various examples, the plurality of photodiodes includes at least a first photodiode and a second photodiode. In one example, the first and second photodiodes are adjacent photodiodes in the photodiode array. A shared floating diffusion region is configured to receive charge transferred from the first and second photodiodes. An analog-to-digital converter (ADC) is configured to perform a first ADC conversion in response to the charge in the shared floating diffusion region after a reset operation to generate a reference reading. The ADC is next configured to perform a second ADC conversion in response to the charge transferred from the first photodiode to the shared floating diffusion region to generate the first half of a PDAF reading. The ADC then is configured to perform a third ADC conversion in response to the combination of the charge transferred from the second photodiode and the charge previously transferred from the first photodiode in the shared floating diffusion region to generate a full image reading.

[0017] As will be shown in various examples, the photodiodes in the photodiode array can be arranged in 2x2 photodiode groupings that include pairs of adjacent photodiodes. In one example, the 2x2 photodiode groupings share the same color filter that provides 4C Bayer merging for the imaging device.

[0018] The imaging device also includes a plurality of transfer transistors, where each of the plurality of transfer transistors is coupled to a corresponding one of the plurality of photodiodes. The plurality of transfer transistors includes a first transfer transistor coupled between the first photodiode and the shared floating diffusion region and a second transfer transistor coupled between the second photodiode and the shared floating diffusion region.

[0019] A reset transistor is coupled between the shared floating diffusion region and a voltage supply. A source follower transistor is also included. The source follower transistor has a gate coupled to the shared floating diffusion region and a source coupled to a column bit line. In one example, the source of the source follower transistor is coupled to the column bit line through a row select transistor.

[0020] In an example, the ADC is configured to perform a first ADC conversion to determine a reference reading by pulsing a reset transistor to reset a shared floating diffusion region while turning off first and second transfer transistors. The ADC is next configured to perform a second ADC conversion to determine the first half of a PDAF reading by pulsing a first transfer transistor while turning off the reset transistor and the second transfer transistor. The ADC is then configured to perform a third ADC conversion to determine a full image reading by pulsing a second transfer transistor while turning off the reset transistor and the first transfer transistor.

[0021] Next, the first half of the PDAF reading may be determined in response to determining a difference between the second ADC conversion and the first ADC conversion. The second half of the PDAF reading may be determined in response to determining a difference between the third ADC conversion and the second ADC conversion. PDAF information may be determined in response to evaluating the first half PDAF and the second half PDAF readings relative to each other. The full image reading may be determined in response to determining a difference between the third ADC conversion and the first ADC conversion. Thus, in accordance with the teachings of the present invention, both a PDAF reading and an image sensing reading may be determined from the photodiodes of an imaging device using three readouts and ADC conversions.

[0022] For illustration, Figure 1 An example of an imaging system 100 including an imaging device having a photodiode array in accordance with the teachings of the present invention is described. Specifically, imaging system 100 includes a photodiode array 102, a control circuit 110, a readout circuit 106, and functional logic circuitry 108. In one example, in accordance with the teachings of the present invention, photodiode array 102 is a two-dimensional (2D) array of photodiodes 104 (e.g., P1, P2, …, Pn) that may be used for both phase detection autofocus and image sensing. As illustrated in the depicted example, photodiodes 104 are arranged in rows (e.g., R1 to Ry) and columns (e.g., C1 to Cx) to acquire image data and / or focus data of a person, place, object, etc., which may then be used to focus, acquire, and display a 2D image of the person, place, object, etc.

[0023] In one example, each photodiode 104 in the photodiode array 102 is configured to photogenerate image charge and / or phase-detection autofocus charge in response to incident light. The image charge and / or phase-detection autofocus charge generated in each photodiode 104 is transferred to a shared floating diffusion region in each pixel circuit, and the image charge and / or phase-detection autofocus charge is converted into an image signal or a phase-detection autofocus signal, which is then read out from each pixel circuit by the readout circuit 106 via a column bit line 112. In various examples, the signal read out from the photodiode array 102 can be amplified, digitized, and then transferred to the functional logic circuit 108. In various examples, the readout circuit 106 includes amplifier circuitry, an analog-to-digital converter (ADC), or other elements. In one example, the readout circuit 106 can read out one row of data at a time along the column bit line 112, as Figure 1 illustrated, or can use a variety of other techniques (not illustrated) to read out the data, such as serial readout or simultaneous full parallel readout of all pixel circuits. The functional logic circuit 108 can store the image data or even manipulate the image data by applying post-image effects (e.g., cropping, rotating, removing red-eye, adjusting brightness, adjusting contrast, or otherwise).

[0024] Figure 2 An example of a photodiode array 202 of photodiodes 204 in accordance with the teachings of the present disclosure is illustrated. Specifically, Figure 2 the example depicted in

[0025] Figure 2 illustrates a photodiode array 202 that includes a plurality of photodiodes 204 arranged in rows and columns in the photodiode array to generate charge in response to incident light. In various examples, the plurality of photodiodes 204 are arranged in at least adjacent pairs in the photodiode array 202. As will be described in more detail, each adjacent photodiode pair includes a first photodiode and a second photodiode.

[0026] In Figure 2In the example depicted, it should be understood that the photodiodes 204 of the photodiode array 202 are combined. Thus, the information generated from each photodiode 204 is added or combined with the information generated from one or more nearby combined photodiodes 204 to generate combined information, and thus the performance of each individual photodiode 204 is added to improve the performance of the photodiode array 202. For example, in various examples, 2x2 photodiode 204 groupings are configured to be combined such that the 4 photodiodes 204 included in each grouping all share the same color. In other words, the photodiodes 204 are arranged in the photodiode array 202 such that each 2x2 image sensing photodiode grouping is red (R), green (G), or blue (B). In one example, the 2x2 combined photodiode 204 groupings are all adjacent photodiodes in the photodiode array 202 and share the same color filter. In that example, Bayer combination is provided for the 2x2 red (R) color filter groupings, 2x2 green (G) color filter groupings, and 2x2 blue (B) color filter groupings disposed over the photodiodes. In one example, it should be understood that microlenses may also be disposed over the photodiodes, but are not shown so as not to obscure the teachings of the present invention.

[0027] In operation, phase detection information is retrieved from the imaging device by comparing or evaluating the signals from one side of the 2x2 photodiode grouping with the signals from the other side of the 2x2 photodiode grouping. For example, in one example, the signals from a horizontally adjacent pair are compared. In other words, the signals from the left photodiode pair (e.g., the left half) of the 2x2 photodiode grouping are compared with the signals from the right photodiode pair (e.g., the right half) of the 2x2 photodiode grouping. In another example, the signals from a vertically adjacent pair are compared. In other words, the signals from the top photodiode pair (e.g., the upper half) of the 2x2 photodiode grouping are compared with the signals from the bottom photodiode pair (e.g., the lower half) of the 2x2 photodiode grouping. In yet another example having 2x1 photodiode groupings ( Figure 2 not shown herein), the signals from the left or top (e.g., the left half or the upper half) photodiodes of the 2x1 photodiode grouping are compared with the signals from the right or bottom (e.g., the right half or the lower half) photodiodes of the 2x1 photodiode grouping.

[0028] As will be described in more detail below, in one example, during operation, all of the pixel circuits of the photodiodes of the photodiode array 202 are reset and then during a first ADC conversion, signals are read out from the pixel circuits and digitized to determine a reference value. Next, during a second ADC conversion, signals from the left two photodiodes of each 2x2 photodiode group are read out and the signals are digitized to determine the first half of the PDAF reading. Then, in accordance with the teachings of the present invention, signals from the right two photodiodes of each 2x2 pixel group are combined with the signals from the left two photodiodes and during a third ADC conversion, the signals are read out and digitized to determine the full image reading. It should be understood that in accordance with the teachings of the present invention, a single reference value determined in response to the first ADC conversion can be utilized to determine the correlated double sampling (CDS) reading of the signals.

[0029] Therefore, it should be understood that signals are read out from the photodiode array 202 without a second reset of the pixel circuits between the readout of the left two photodiodes and the readout of the right two photodiodes of each 2x2 photodiode group. In other words, in accordance with the teachings of the present invention, PDAF data as well as image sensing data can be obtained using three readouts instead of four readouts. It should be understood that in accordance with the teachings of the present invention, by using only three readouts instead of four readouts, the noise performance as well as the frame rate performance are improved.

[0030] For example, if it is assumed that the noise of one CDS readout of a 4C photodiode group is N CDS and if a conventional readout of a 4C photodiode group requires the combination of two CDS readouts, then the noise increases by a factor of √2, or increases to √2*N CDS . In contrast, using the three readout method of the photodiodes in accordance with the teachings of the present invention, only one readout is utilized to determine the reference value, which results in a noise performance that is closer to N CDS rather than Thus, the noise performance is improved because the longer time used to obtain the CDS reading degrades the noise performance.

[0031] Furthermore, if it is assumed that the frame rate of one CDS readout of a 4C PDAF photodiode group is M, and if a conventional readout of a 4C photodiode group requires the combination of two CDS readouts, then the frame rate is reduced by one half, or reduced to In contrast, using the three readout method of the photodiodes in accordance with the teachings of the present invention, only one readout is utilized to determine the reference value, which results in an overall frame rate performance that is approximately .

[0032] Figure 3An example schematic diagram of a pixel circuit 314 included in an imaging system having a photodiode array, in accordance with the teachings of the present invention. It should be understood that Figure 3 the pixel circuit 314 may be an example of one of the pixel circuits coupled to a photodiode 204 included in a photodiode array 202 as shown in Figure 2 or an example of one of the pixel circuits coupled to a photodiode 104 included in a photodiode array 102 as shown in Figure 1 and the similarly named and numbered elements described above are similarly coupled and operative hereinafter.

[0033] In Figure 3 the example depicted, the pixel circuit 314 includes a photodiode 304-0 coupled to a transfer transistor 316-0, a photodiode 304-1 coupled to a transfer transistor 316-1, a photodiode 304-2 coupled to a transfer transistor 316-2, and a photodiode 304-3 coupled to a transfer transistor 316-3. Thus, each of the plurality of transfer transistors 316-0 to 316-3 is coupled to a corresponding one of the plurality of photodiodes 304-0 to 304-3.

[0034] In the example, a shared floating diffusion region 318 is coupled to the transfer transistor 316-0, the transfer transistor 316-1, the transfer transistor 316-2, and the transfer transistor 316-3. Thus, each of the plurality of transfer transistors 316-0 to 316-3 is coupled between a corresponding one of the plurality of photodiodes 304-0 to 304-3 and the shared floating diffusion region 318. As will be discussed in various examples, the floating diffusion region 318 is a shared floating diffusion region configured to receive charge transferred from the plurality of photodiodes 304-0 to 304-3. In one example, a floating diffusion region capacitor 322 is coupled to the shared floating diffusion region 318, as shown.

[0035] In operation, transfer transistor 316-0 is coupled to be controlled in response to transfer control signal TX0, transfer transistor 316-1 is coupled to be controlled in response to transfer control signal TX1, transfer transistor 316-2 is coupled to be controlled in response to transfer control signal TX2, and transfer transistor 316-3 is coupled to be controlled in response to transfer control signal TX3. Thus, the charge photogenerated in photodiode 304-0 in response to incident light is transferred to shared floating diffusion region 318 in response to transfer control signal TX0, the charge photogenerated in photodiode 304-1 in response to incident light is transferred to shared floating diffusion region 318 in response to transfer control signal TX1, the charge photogenerated in photodiode 304-2 in response to incident light is transferred to shared floating diffusion region 318 in response to transfer control signal TX2, and the charge photogenerated in photodiode 304-3 in response to incident light is transferred to shared floating diffusion region 318 in response to transfer control signal TX3.

[0036] In various examples, the incident light directed to photodiodes 304-0 to 304-3 is directed through a color filter of a respective microlens and color filter array (e.g., Figure 2 R, G, B) before reaching photodiodes 304-0 to 304-3. Thus, the incident light can be directed through a red (R) color filter or a green (G) color filter or a blue (B) color filter before reaching photodiodes 304-0 to 304-3.

[0037] Continuing Figure 3 with the example depicted in

[0038] Reset transistor 320 is coupled between a voltage supply (e.g., PIXVDD) and shared floating diffusion region 318. In operation, reset transistor 320 is configured to reset pixel circuit 314, including the charge in shared floating diffusion region 318, in response to reset control signal RST.

[0039] An analog-to-digital converter (ADC) 332 is coupled to column bit lines 312 to perform ADC conversion of an analog signal received from pixel circuit 314 via column bit lines 312. In the depicted example, the digital output of ADC 332 is shown as digital output signal D OUT 336.

[0040] Figure 4 Illustrating an example timing diagram 428 in accordance with the teachings of the present invention, which illustrates various signals in a pixel circuit in an imaging system including a photodiode array, generating signals from the photodiode array and reading out the signals by an analog-to-digital converter. It should be understood that Figure 4 the waveforms illustrated in Figure 3 the pixel circuit 314 and / or Figure 2 the photodiode array 202 and / or Figure 1 the imaging system 100 may be examples of waveforms found therein, and similarly named and numbered elements described above are similarly coupled and operative hereinafter.

[0041] As Figure 4 shown, timing diagram 428 illustrates a reset transistor control signal 420, a row select transistor control signal 426, a transfer transistor control signal TX0 416-0, a transfer transistor control signal TX1 416-1, a transfer transistor control signal TX2 416-2, a transfer transistor control signal TX3 416-3, a bit line signal BL 412, and an analog-to-digital converter (ADC) conversion operation 432.

[0042] At time T1, the reset transistor control signal 420 is asserted or pulsed while the transfer transistor control signals TX0 416-0 to TX3 416-3 remain off. Thus, at time T1, the reset transistor 320 is turned on while the transfer transistors 316-0 to 316-3 are turned off to reset pixel circuit 314 including shared floating diffusion region 318.

[0043] As the shared floating diffusion region 318 is reset with the reset transistor 320 turned on, the row select transistor control signal 426 is then asserted at time T2, which turns on row select transistor 326. With row select transistor 326 turned on at time T2, bit line signal BL 412 begins to charge until time T3, at which time the reset transistor control signal 420 is de-asserted or the pulse in the reset transistor control signal 420 ends, which turns off reset transistor 320 at time T3. Thus, after time T3, bit line signal BL 412 begins to stabilize to a reset level or reference level.

[0044] After the bitline signal BL 412 has stabilized, an ADC conversion operation 432 is performed by the ADC 332 at time T4 to output a first ADC conversion of the bitline signal BL 412, which represents a reference reading at time T4.

[0045] Once the first ADC conversion 432 of the bitline signal BL 412 is complete, the transfer transistor control signals TX0 416-0 and TX1 416-1 are asserted or pulsed at time T5, while the reset transistor control signal 420 and the transfer transistor control signals TX2 416-2 and TX3 416-3 remain in the off state. Thus, the transfer transistors 316-0 and 316-1 are turned on at time T5, while the transfer transistors 316-2 and 316-3 remain off at time T5. Accordingly, the charge photogenerated in the photodiodes 304-0 and 304-1 is transferred to the shared floating diffusion region 318 at time T5.

[0046] It should be understood that in the Figure 3 example depicted, the photodiodes 304-0 and 304-1 represent the "upper half" of a 2x2 photodiode arrangement. In another example, it should be understood that the photodiodes 304-0 and 304-1 may represent the "left half" of a 2x2 photodiode arrangement.

[0047] As the charge is transferred from the "upper half" photodiodes 304-0 and 304-1 to the shared floating diffusion region 318 at time T5, the bitline signal BL 412 begins to drop accordingly at time T5. After the charge has been transferred from the photodiodes 304-0 and 304-1 to the shared floating diffusion region 318, the transfer transistor control signals TX0 416-0 and TX1 416-1 are de-asserted, which turns off the transfer transistors 316-0 and 316-1. After the bitline signal BL 412 has stabilized, a second ADC conversion operation 432 is performed by the ADC 332 at time T6 to output a second ADC conversion of the bitline signal BL 412, which represents a front half (e.g., upper half) PDAF reading at time T6.

[0048] Once the second ADC conversion 432 of the bitline signal BL 412 is complete, the transfer transistor control signals TX0 416-2 and TX1 416-3 are asserted or pulsed at time T7, while the reset transistor control signal 420 and the transfer transistor control signals TX0 416-0 and TX1 416-1 remain in the off state. Thus, the transfer transistors 316-2 and 316-3 are turned on at time T7, while the transfer transistors 316-0 and 316-1 remain off at time T7. Accordingly, the charge photogenerated in the photodiodes 304-2 and 304-3 is transferred to or combined with the charge in the shared floating diffusion region 318 at time T7.

[0049] It should be noted that in accordance with the teachings of the present invention, the charge in the shared floating diffusion region 318 is not reset a second time before the charge is transferred from the photodiodes 304-2 and 304-3. It should also be understood that in the Figure 3 example depicted, the photodiodes 304-2 and 304-3 represent the "lower half" of a 2x2 photodiode arrangement. In another example, it should be understood that the photodiodes 304-2 and 304-2 can represent the "right half" of a 2x2 photodiode arrangement.

[0050] In the case where additional charge is transferred from the "lower half" photodiodes 304-2 and 304-3 to the shared floating diffusion region 318 at time T7, the bitline signal BL 412 begins to drop again accordingly at time T7. After the additional charge has been transferred from the photodiodes 304-2 and 304-3 to the shared floating diffusion region 318, the transfer transistor control signals TX2 416-2 and TX3 416-3 are de-asserted, which turns off the transfer transistors 316-2 and 316-3. After the bitline signal BL 412 has stabilized again, a third ADC conversion operation 432 is performed by the ADC 332 at time T8 to output a third ADC conversion of the bitline signal BL 412, which represents a full (e.g., upper and lower half) image reading at time T8.

[0051] Once the third ADC conversion 432 of the bitline signal BL 412 is complete, the row select transistor control signal 426 is then de-asserted at time T9, which turns off the row select transistor 326, causing the bitline signal BL 412 to return to its idle state value.

[0052] Generally speaking, it should be understood that in accordance with the teachings of the present invention, three ADC conversions 432 are utilized to perform the readout. A first ADC conversion (e.g., D OUT1 ) is used at time T4 to obtain a reference, and a second ADC conversion (e.g., D OUT2) to obtain the first half PDAF readings, and use the third ADC conversion at time T8 (e.g., D OUT3 ) to obtain the full image readings.

[0053] In signal processing, the correlated double sampling (CDS) or the normalized "upper half" PDAF readings can be determined by finding the difference between the second ADC conversion (e.g., D OUT2 ) and the first ADC conversion (e.g., D OUT1 ), or D OUT2 - D OUT1 . The "lower half" (e.g., "second half") PDAF readings can be determined by finding the difference between the third ADC conversion (e.g., D OUT3 ) and the second ADC conversion (e.g., D OUT2 ), or D OUT3 - D OUT2 . The CDS or the normalized version of the full image readings can be determined by finding the difference between the third ADC conversion (e.g., D OUT3 ) and the first ADC conversion (e.g., D OUT1 ), or D OUT3 - D OUT1 .

[0054] The above description of the illustrated examples of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention are described herein for illustrative purposes, as will be recognized by those skilled in the relevant art, various modifications are possible within the scope of the invention.

[0055] In view of the above detailed description, these modifications can be made to the invention. The terms used in the appended claims should not be construed as limiting the invention to the specific examples disclosed in the specification. Instead, the scope of the invention will be determined entirely by the appended claims, which should be interpreted according to the established principles of claim interpretation.

Claims

1. An imaging device, comprising: A plurality of photodiodes arranged in a photodiode array to generate charges in response to incident light, wherein the plurality of photodiodes includes a first photodiode, a second photodiode, a third photodiode, and a fourth photodiode; A shared floating diffusion region configured to receive charges transferred from the first photodiode, the second photodiode, the third photodiode, and the fourth photodiode; A plurality of transfer transistors, wherein each of the plurality of transfer transistors is coupled to a corresponding one of the plurality of photodiodes, and the plurality of transfer transistors includes a first transfer transistor coupled between the first photodiode and the shared floating diffusion region, a second transfer transistor coupled between the second photodiode and the shared floating diffusion region, a third transfer transistor coupled between the third photodiode and the shared floating diffusion region, and a fourth transfer transistor coupled between the fourth photodiode and the shared floating diffusion region; A reset transistor coupled between the shared floating diffusion region and a voltage supplier; A source follower transistor having a gate coupled to the shared floating diffusion region and a source coupled to a column bit line; A row selection transistor coupled to the source follower transistor, wherein the source follower transistor and the row selection transistor are coupled between the voltage supplier and the column bit line; And An analog-to-digital converter ADC coupled to the column bit line, wherein the ADC is configured to perform a first ADC conversion in response to the charges in the shared floating diffusion region after a reset operation to generate a reference reading, wherein the reset operation is configured to be performed by pulsing the reset transistor to reset the shared floating diffusion region while simultaneously turning off the first transfer transistor, the second transfer transistor, the third transfer transistor, and the fourth transfer transistor, wherein the ADC is next configured to perform a second ADC conversion in response to pulsing the first transfer transistor and the third transfer transistor while simultaneously turning off the reset transistor, the second transfer transistor, and the fourth transfer transistor to transfer charges from the first photodiode and the third photodiode to the shared floating diffusion region to generate the first half of a phase detection autofocus PDAF reading, and wherein the ADC is then configured to perform a third ADC conversion in response to pulsing the second transfer transistor and the fourth transfer transistor while simultaneously turning off the reset transistor, the first transfer transistor, and the third transfer transistor to combine the charges previously transferred from the first photodiode and the third photodiode in the shared floating diffusion region with the charges transferred from the second photodiode and the fourth photodiode to generate a full image reading.

2. The imaging device according to claim 1, wherein a second half of a PDAF reading is determined in response to a difference between the third ADC conversion and the second ADC conversion.

3. The imaging device according to claim 2, wherein the first half of the PDAF reading is an upper half of the PDAF reading, and the second half of the PDAF reading is a lower half of the PDAF reading.

4. The imaging device according to claim 2, wherein the first half of the PDAF reading is a left half of the PDAF reading, and the second half of the PDAF reading is a right half of the PDAF reading.

5. The imaging device according to claim 1, wherein the first half of the PDAF reading is determined in response to a difference between the second ADC conversion and the first ADC conversion.

6. The imaging device according to claim 1, wherein a full image reading is determined in response to a difference between the third ADC conversion and the first ADC conversion.

7. An imaging system, comprising: a plurality of photodiodes arranged in a photodiode array to generate charges in response to incident light, wherein the plurality of photodiodes includes a first photodiode, a second photodiode, a third photodiode, and a fourth photodiode; a shared floating diffusion region configured to receive charges transferred from the first photodiode, the second photodiode, the third photodiode, and the fourth photodiode; a plurality of transfer transistors, wherein each of the plurality of transfer transistors is coupled to a corresponding one of the plurality of photodiodes, and the plurality of transfer transistors includes a first transfer transistor coupled between the first photodiode and the shared floating diffusion region, a second transfer transistor coupled between the second photodiode and the shared floating diffusion region, a third transfer transistor coupled between the third photodiode and the shared floating diffusion region, and a fourth transfer transistor coupled between the fourth photodiode and the shared floating diffusion region; a reset transistor coupled between the shared floating diffusion region and a voltage supply; a source follower transistor having a gate coupled to the shared floating diffusion region and a source coupled to one of a plurality of column bit lines; a row selection transistor coupled to the source follower transistor, wherein the source follower transistor and the row selection transistor are coupled between the voltage supply and the one of the plurality of column bit lines; a control circuit coupled to the photodiode array to control an operation of the photodiode array; and a readout circuit coupled to the photodiode array to read out signals from the photodiode array through the plurality of column bit lines, wherein the readout circuit includes an analog-to-digital converter ADC configured to perform a first ADC conversion in response to charges in the shared floating diffusion region after a reset operation to generate a reference reading, The reset operation is configured to be performed by pulsing the reset transistor to reset the shared floating diffusion region while simultaneously turning off the first transfer transistor, the second transfer transistor, the third transfer transistor, and the fourth transfer transistor. The ADC is then configured to perform a second ADC conversion to generate the first half of a phase detection autofocus (PDAF) reading by pulsing the first transfer transistor and the third transfer transistor while simultaneously turning off the reset transistor, the second transfer transistor, and the fourth transfer transistor to transfer charge from the first photodiode and the third photodiode to the shared floating diffusion region. The ADC is then configured to perform a third ADC conversion to generate a full image reading by pulsing the second transfer transistor and the fourth transfer transistor while simultaneously turning off the reset transistor, the first transfer transistor, and the third transfer transistor to combine the charge previously transferred from the first photodiode and the third photodiode in the shared floating diffusion region with charge from the second photodiode and the fourth photodiode.

8. The imaging system according to claim 7, further comprising functional logic circuitry coupled to the readout circuit to store a digital representation of the signals from the photodiode array.

9. The imaging system according to claim 7, wherein the second half of the PDAF reading is determined in response to a difference between the third ADC conversion and the second ADC conversion.

10. The imaging system according to claim 9, wherein the first half of the PDAF reading is the upper half of the PDAF reading, and the second half of the PDAF reading is the lower half of the PDAF reading.

11. The imaging system according to claim 9, wherein the first half of the PDAF reading is the left half of the PDAF reading, and the second half of the PDAF reading is the right half of the PDAF reading.

12. The imaging system according to claim 7, wherein the first half of the PDAF reading is determined in response to a difference between the second ADC conversion and the first ADC conversion.

13. The imaging system according to claim 7, wherein the full image reading is determined in response to a difference between the third ADC conversion and the first ADC conversion.

Images