Vector word operation method based on 1553B bus
By combining read and set or clear operations of dual-port RAM and matching register on the FPGA chip into a single atomic operation in the 1553B bus system, the error problem in vector word operation of remote terminal is solved, and the stability and reliability of the system are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAN YUNWEI ZHILIAN TECH CO LTD
- Filing Date
- 2022-08-19
- Publication Date
- 2026-04-24
AI Technical Summary
In the existing 1553B bus system, remote terminals are prone to setting and clearing vector words when performing vector word operations, especially when the operations of the master and MBI slave are interleaved, which leads to a disorder in the operation sequence and causes errors.
By using an FPGA chip, a dual-port RAM, a vector word register, a vector word set matching register, and a vector word clear matching register are established on a remote terminal. The read and set or clear operations are combined into a single atomic operation through logic units, avoiding repeated operations by different entities.
It effectively solves the error problem of vector word operation in the traditional 1553B bus system, ensures the accuracy and consistency of operation, avoids errors caused by disordered operation sequence, and improves the stability and reliability of the system.
Smart Images
Figure CN115470160B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of aviation bus technology, and relates to vector word operation, specifically to a vector word operation method based on the 1553B bus. Background Technology
[0002] MIL-STS-1553B is a distributed processing, centralized control data bus. To improve the fault tolerance of the bus system in response to potential failures in the physical network, the bus structure adopts a dual-redundancy or multi-redundancy design. In a 1553B bus system, the bus network consists of a bus controller (BC), several remote terminals (RT), a bus monitor (BM), a backup bus controller (BBC), and several cables. The basic topology of the 1553B bus is as follows: Figure 1 As shown.
[0003] 1. Bus Controller (BC)
[0004] In a bus network, the bus controller is primarily responsible for initiating and controlling message transmission on the bus. It manages and schedules system communication by reading the command word list configured by the host computer. Therefore, all command words in the bus system are controlled and sent by the bus controller. Under normal circumstances, a 1553B bus network system will only have one bus controller. However, to further improve the stability, reliability, and fault tolerance of the bus system and prevent the entire system from failing due to a bus controller malfunction, a backup bus controller is designed into the bus system. Furthermore, under any circumstances, only one bus controller (BC) will be in normal working condition in the bus system.
[0005] 2. Remote Terminal (RT)
[0006] In a bus system, a remote terminal (RTP) acts as an interface connecting different airborne equipment subsystems and the bus system communication network. Its main function is to respond to valid command words received from the bus network—by responding with the corresponding status or data word. In a bus system, since the bus controller is responsible for controlling the scheduling and transmission of all command words, RTPs passively reply with corresponding messages. A 1553B bus network can have a maximum of 31 RTPs, each with a unique address.
[0007] 3. Bus Monitor (BM)
[0008] The bus monitor is primarily responsible for listening to and recording command words, data words, and status words transmitted on the bus network. Recording facilitates offline analysis, while listening allows for real-time monitoring of the system's operating status and provides relevant information to the backup bus controller so that it can take over when necessary, thus ensuring the system continues to operate stably.
[0009] 4. Backup Bus Controller (BBC)
[0010] The backup bus controller is primarily responsible for monitoring the operating status of the bus controller. When the bus controller suddenly fails and is unable to properly control the communication scheduling of the bus system, it will automatically switch to the bus controller's operating mode to maintain the normal operation of the bus system.
[0011] In a traditional 1553B bus system, the process by which a remote terminal (RT) sends data to the bus controller (BC) via the 1553B bus is as follows.
[0012] Step 1: Configure Dual-Port RAM (Random Access Memory). Configure a dual-port RAM on the remote terminal, with a space of at least 16 bits x 32KB. Both ends of the dual-port RAM should be accessible by both the remote terminal's host and the MBI slave. Define 16 buffer spaces on the dual-port RAM to store data to be sent to the bus controller. Details are as follows: Figure 2 As shown.
[0013] Step 2: Configure the vector word register. Configure a 16-bit vector word register reg_vector_word[15:0] on the remote terminal. The 16 bits of the vector word correspond to the 16 cache spaces of the dual-port RAM. That is, [0], [1], [2], ...,
[15] of the vector word correspond one-to-one with the cache spaces 0, 1, 2, ..., 15 of the dual-port RAM.
[0014] Step 3: Host writes to RAM. In the remote terminal (RT) system, the host writes the data to be sent into the buffer space of the dual-port RAM. The host write address is host_waddr[15:0], where host_waddr[6:3] = X (0 <= X <= 15), and X is a decimal number.
[0015] Step 4: The host reads the vector word register. In the remote terminal (RT) described in step 3, the host reads the current value of the vector word from the vector word register.
[0016] Step 5: Set the host vector word register. Perform a bitwise OR operation between the vector word value read in Step 4 and a 16-bit constant, where the Xth bit of the constant is 1 and the remaining bits are 0.
[0017] Steps 3 and 5 are as follows: Figure 4As shown.
[0018] Step 6: MBI slave reads RAM. In the remote terminal (RT), the slave reads the data to be sent from the buffer space of the dual-port RAM and sends it to the bus controller (BC) via the 1553B bus. The read address is slave_raddr[15:0], where slave_raddr[6:3] = X (0 <= X <= 15), and X is a decimal number.
[0019] Step 7: MBI slave reads vector word register. In the remote terminal (RT) described in step 6, the MBI slave reads the current value of the vector word from the vector word register.
[0020] Step 8: Clear the vector word register of the MBI slave device. Perform a bitwise AND operation between the vector word value read in Step 7 and a 16-bit constant, where the Xth bit of the constant is 0 and the remaining bits are 1. Specifically... Figure 5 As shown.
[0021] In the aforementioned traditional 1553B bus system, the process of the remote terminal (RT) sending data to the bus controller (BC) via the 1553B bus involves two operations on the vector word: setting the vector word by the host and clearing the vector word by the MBI slave.
[0022] In terms of specific steps, the operation steps for setting the vector word on the host are: host reads the vector word and host sets the vector word; the operation steps for clearing the vector word on the MBI slave are: read the vector word and MBI slave clears the vector word. If these two operations are intertwined, the following two problems will occur.
[0023] Scenario 1: The host reads the vector word, the MBI slave reads the vector word, the host sets the vector word to bit A, and the MBI slave clears the vector word to bit B. In this case, setting the vector word to bit A by the host fails.
[0024] Scenario 2: The MBI slave reads the vector word, the master reads the vector word, the MBI slave clears the B bit of the vector word, and the master sets the A bit of the vector word. In this case, the MBI slave fails to clear the B bit of the vector word. Summary of the Invention
[0025] To address the shortcomings of existing technologies, the present invention aims to provide a vector word operation method based on the 1553B bus, thereby solving the technical problems of setting and clearing vector word errors in traditional 1553B bus remote terminals.
[0026] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:
[0027] A vector word operation method based on the 1553B bus, wherein the processing chip of the remote terminal is an FPGA chip, and the method specifically includes the following steps:
[0028] Step 1: Establish a dual-port RAM, a vector word register, a vector word set match register, and a vector word clear match register on the FPGA chip of the remote terminal.
[0029] Step 2: The host of the remote terminal writes the data to be sent into the dual-port RAM and simultaneously sets the vector word register.
[0030] Step 3: The remote terminal's MBI slave reads the data to be sent from the dual-port RAM and simultaneously clears the vector word register.
[0031] The present invention also has the following technical features:
[0032] Specifically, step 1 includes the following sub-steps:
[0033] Step 1.1: Establish a 16-bit x 32K dual-port RAM on the FPGA of the remote terminal. One end of the RAM is connected to the host and the other end is connected to the MBI slave. Set up 16 buffer spaces on the RAM. The host writes the data to be sent into the 16 buffer spaces, and the slave reads the data to be sent from the 16 buffer spaces.
[0034] Step 1.2: Establish a vector word register reg_vector_word[15:0] for the remote terminal. The host and slave can read the value of the vector word, and the logic can write to the vector word register. That is, the host can set the vector word, and the slave can clear the vector word. The register has 16 bits, and each bit corresponds to a cache space of a dual-port RAM.
[0035] Step 1.3: Establish a vector word set matching register reg_vector_word_match_set[15:0] for the remote terminal. This register is set by the slave device and is used to match the write address of the master device.
[0036] Step 1.4: Establish a vector word clearing and matching register reg_vector_word_match_clear[15:0] for the remote terminal. This register is set by the slave device and is used to match the slave device's read address.
[0037] Specifically, step 2 includes the following sub-steps:
[0038] Step 2.1: Configure the vector word matching register reg_vector_word_match_set[15:0] in the remote terminal on the MBI slave. reg_vector_word_match_set[15:7] determines the location of the cache space in the dual-port RAM. reg_vector_word_match_set[6:0] can be configured to 0.
[0039] Step 2.2: When the host of the remote terminal needs to send data to the bus controller, the host writes the data to be sent into the dual-port RAM cache space;
[0040] Step 2.3: Logic monitors the host write RAM address host_waddr[15:0] in step 2.2. When the host write addresses host_waddr[15:7] and host_waddr[1:0] are equal to the vector word set matching registers reg_vector_word_match_set[15:7] and reg_vector_word_match_set[1:0] respectively, the logic sets the Xth bit of the vector word register to 1, where X is the decimal number of the host write address host_waddr[5:2].
[0041] Specifically, step 3 includes the following sub-steps:
[0042] Step 3.1: Configure the vector word clearing and matching register reg_vector_word_match_clear[15:0] in the remote terminal of the MBI slave. reg_vector_word_match_clear[15:7] determines the location of the cache space in the dual-port RAM. reg_vector_word_match_clear[6:0] can be configured to 0.
[0043] Step 3.2: When the remote terminal's MBI slave needs to send data to the bus controller, the MBI slave reads the data to be sent from the dual-port RAM cache space and sends it to the bus controller through the 1553B bus.
[0044] Step 3.3: The logic monitors the address of the RAM read from the slave machine in step 3.2, slave_raddr[15:0]. When the slave machine read addresses slave_raddr[15:7] and slave_raddr[1:0] are equal to the vector word clearing and matching registers reg_vector_word_match_clear[15:7] and reg_vector_word_match_clear[1:0], respectively, the logic clears the Xth bit of the vector word register, where X is the decimal number of the slave machine read address slave_raddr[5:2].
[0045] Compared with the prior art, the present invention has the following technical effects:
[0046] (I) This invention provides a novel vector word operation solution that solves the problems of setting and clearing vector words when the host and MBI slave access the cache space in the prior art.
[0047] (II) In step 2 of this invention, the logic combines the read vector word and set vector word operations into a single atomic operation, instead of the host performing the read vector word and set vector word operations separately. Furthermore, there will be no slave device inserting a read vector word between the logical read vector word and the logical set vector word operations.
[0048] (III) In step 3 of this invention, the logic combines the two operations of reading the vector word and clearing the vector word into a single atomic operation, instead of having the MBI slave perform the two operations. Furthermore, there will be no instance of the master inserting a read vector word between the logical read vector word and the logical clear vector word operations.
[0049] (IV) In this invention, the reading and setting of the vector word in step 2 and the reading and clearing of the vector word in step 3 are both completed independently by logic, and the two operations are combined into a single atomic operation. This avoids the setting and clearing errors caused by the disordered order of the four operations (two readings, setting, and clearing) of the vector word in the traditional 1553B system, where setting and clearing the vector word are performed by different entities. Attached Figure Description
[0050] Figure 1 This is the basic structure of the 1553B bus.
[0051] Figure 2 This diagram illustrates how a remote terminal sends data to a bus controller.
[0052] Figure 3 This is a schematic diagram showing the correspondence between vector word registers and cache space.
[0053] Figure 4 A schematic diagram for setting up a vector word.
[0054] Figure 5 A diagram illustrating the process of clearing a vector word.
[0055] Figure 6 Set the logical vector word register.
[0056] Figure 7 Clear the vector word register for logic.
[0057] The specific content of the present invention will be further explained in detail below with reference to the embodiments. Detailed Implementation
[0058] It should be noted that, unless otherwise specified, all devices in this invention are those known in the art, such as testing devices.
[0059] It should be noted that in this invention:
[0060] Host: refers to the host computer in a remote terminal system.
[0061] MBI slave: refers to the processor on the board in a remote terminal system.
[0062] Cache space: 16 spaces on the dual-port RAM. When the remote terminal sends data to the bus controller, the host first writes the data to be sent into the cache space, and then the MBI slave reads the data from the cache space and sends it to the 1553B bus.
[0063] Logic: refers to the logic on an FPGA (Field Programmable Gate Array) chip.
[0064] The overall technical concept of this invention is as follows: In order to solve the various drawbacks of traditional 1553B bus vector word operation, this invention has made significant improvements to the vector word operation of the 1553B bus system.
[0065] First, the original method of the host reading and setting vector words was changed to logical passive reading and setting of vector words simultaneously. The main operation was changed from the host to logical passive execution, and the two operations were combined into one.
[0066] Secondly, the original method of reading vector words from the MBI slave and clearing vector words from the MBI slave has been changed to logically passively reading and clearing vector words at the same time. The main operator has changed from the MBI slave to logically passively executing the operation, and the two operations have been combined into one.
[0067] Finally, both the set vector word and the clear vector word are logical, and both are executed sequentially, so there will be no errors in setting or clearing the vector word.
[0068] The following are specific embodiments of the present invention. It should be noted that the present invention is not limited to the following specific embodiments. All equivalent modifications made based on the technical solutions of this application fall within the protection scope of the present invention.
[0069] Example:
[0070] This embodiment provides a vector word operation method based on the 1553B bus. In this method, the processing chip of the remote terminal (RT) is an FPGA chip, and the method specifically includes the following steps:
[0071] Step 1: Create a dual-port RAM, a vector word register, a vector word set match register, and a vector word clear match register on the FPGA chip of the remote terminal (RT).
[0072] Specifically, step 1 includes the following sub-steps:
[0073] Step 1.1: Establish a 16-bit x 32K dual-port RAM on the FPGA of the remote terminal (RT). One end of the RAM is connected to the host and the other end is connected to the MBI slave. Set up 16 buffer spaces on the RAM. The host writes the data to be sent into the 16 buffer spaces, and the slave reads the data to be sent from the 16 buffer spaces.
[0074] Step 1.2: Establish a vector word register reg_vector_word[15:0] for the remote terminal (RT). The list of registers related to the vector word is shown in Table 1. The master and slave devices can read the value of the vector word, and the logic can write to the vector word register, that is, the master can set the vector word, and the slave device can clear the vector word. This register has 16 bits, and each bit corresponds to a cache space of a dual-port RAM, such as... Figure 2 As shown; a schematic diagram of the correspondence between the vector word register and the cache space is as follows. Figure 3 As shown.
[0075] Table 1. List of Vector Word Related Registers
[0076]
[0077] Step 1.3: Establish a vector word set matching register reg_vector_word_match_set[15:0] for the remote terminal (RT). This register is set by the slave device and is used to match the write address of the master device.
[0078] Step 1.4: Create a vector word clearing match register reg_vector_word_match_clear[15:0] for the remote terminal (RT). This register is set by the slave device and is used to match the slave device's read address.
[0079] Step 2: The remote terminal (RT) host writes the data to be sent into the dual-port RAM and simultaneously sets the vector word register (the logic here refers to the logic on the FPGA chip), such as... Figure 4 and Figure 6 As shown.
[0080] Specifically, step 2 includes the following sub-steps:
[0081] Step 2.1: Configure the vector word set matching register reg_vector_word_match_set[15:0] in the remote terminal (RT) of the MBI slave. reg_vector_word_match_set[15:7] determines the location of the cache space in the dual-port RAM. reg_vector_word_match_set[6:0] can be configured to 0.
[0082] Step 2.2: When the host of the remote terminal (RT) needs to send data to the bus controller (BC), the host writes the data to be sent into the dual-port RAM cache space.
[0083] Step 2.3: Logic monitors the host write RAM address host_waddr[15:0] in step 2.2. When the host write addresses host_waddr[15:7] and host_waddr[1:0] are equal to the vector word set matching registers reg_vector_word_match_set[15:7] and reg_vector_word_match_set[1:0] respectively, the logic sets the Xth bit of the vector word register to 1, where X is the decimal number of the host write address host_waddr[5:2].
[0084] Furthermore, in step 2.3, the logic combines the read vector word and set vector word operations into a single atomic operation, instead of having the host perform both operations separately. This also eliminates the possibility of a slave device inserting a read vector word between the logical read vector word and logical set vector word operations. This step is one of the key innovations of this invention.
[0085] The technical effect of step 2: In step 2, the logic combines the read vector word and set vector word operations into a single atomic operation, instead of the host performing two separate operations. Furthermore, there is no possibility of a slave device inserting a read vector word between the logical read vector word and logical set vector word operations. This step is the first innovative point of this invention.
[0086] Step 3: The remote terminal (RT)'s MBI slave reads the data to be sent from the dual-port RAM while simultaneously clearing the vector word register (the logic here refers to the logic on the FPGA chip), such as... Figure 5 and Figure 7 As shown.
[0087] Specifically, step 3 includes the following sub-steps:
[0088] Step 3.1: Configure the vector word clearing and matching register reg_vector_word_match_clear[15:0] in the remote terminal (RT) of the MBI slave. reg_vector_word_match_clear[15:7] determines the location of the buffer space in the dual-port RAM. reg_vector_word_match_clear[6:0] can be configured to 0.
[0089] Step 3.2: When the MBI slave of the remote terminal (RT) needs to send data to the bus controller (BC), the MBI slave reads the data to be sent from the dual-port RAM cache space and sends it to the bus controller (BC) through the 1553B bus.
[0090] Step 3.3: The logic monitors the address of the RAM read from the slave machine in step 3.2, slave_raddr[15:0]. When the slave machine read addresses slave_raddr[15:7] and slave_raddr[1:0] are equal to the vector word clearing and matching registers reg_vector_word_match_clear[15:7] and reg_vector_word_match_clear[1:0], respectively, the logic clears the Xth bit of the vector word register, where X is the decimal number of the slave machine read address slave_raddr[5:2].
[0091] Furthermore, in step 3.3, the logic combines the read vector word and clear vector word operations into a single atomic operation, instead of having the MBI slave perform the read vector word and clear vector word operations separately. There is also no insertion of a read vector word operation by the master between the logical read vector word and logical clear vector word operations. This step is one of the important innovations of this invention.
[0092] The technical effect of step 3: In step 3, the logic combines the two operations of reading and clearing the vector word into a single atomic operation, instead of having the MBI slave perform the two operations separately. Furthermore, there is no insertion of a read vector word operation between the logical read and logical clear vector words. This step is the second innovative point of this invention.
[0093] The technical advantage of consecutive operations in steps 2 and 3: The reading and setting of the vector word in step 2, and the reading and clearing of the vector word in step 3, are both performed independently by the logic, and each operation is combined into a single atomic operation. This avoids the setting and clearing errors caused by the disordered sequence of the four operations (two reads, setting, and clearing) of the vector word in the traditional 1553B system, where setting and clearing are performed by different entities. The consecutive operations in steps 2 and 3 are the third innovation of this invention.
Claims
1. A vector word operation method based on a 1553B bus, characterized in that, In this method, the processing chip of the remote terminal is an FPGA chip, and the method specifically includes the following steps: Step 1: Establish a dual-port RAM, a vector word register, a vector word set match register, and a vector word clear match register on the FPGA chip of the remote terminal. Step 2: The host of the remote terminal writes the data to be sent into the dual-port RAM and simultaneously sets the vector word register. Step 2 specifically includes the following sub-steps: Step 2.1: Configure the vector word matching register reg_vector_word_match_set [15:0] in the remote terminal on the MBI slave. reg_vector_word_match_set [15:7] determines the location of the cache space in the dual-port RAM. reg_vector_word_match_set [6:0] can be configured to 0. Step 2.2: When the host of the remote terminal needs to send data to the bus controller, the host writes the data to be sent into the dual-port RAM cache space; Step 2.3: Logic monitors the host write RAM addresses host_waddr [15:0] in step 2.
2. When the host write addresses host_waddr [15:7] and host_waddr [1:0] are equal to the vector word set matching registers reg_vector_word_match_set [15:7] and reg_vector_word_match_set [1:0] respectively, the logic sets the Xth bit of the vector word register to 1, where X is the decimal number of the host write address host_waddr [5:2]. Step 3: The remote terminal's MBI slave reads the data to be sent from the dual-port RAM and simultaneously clears the vector word register. Step 3 specifically includes the following sub-steps: Step 3.1: Configure the vector word clearing and matching register reg_vector_word_match_clear [15:0] in the remote terminal of the MBI slave. reg_vector_word_match_clear [15:7] determines the location of the cache space in the dual-port RAM. reg_vector_word_match_clear [6:0] can be configured to 0. Step 3.2: When the remote terminal's MBI slave needs to send data to the bus controller, the MBI slave reads the data to be sent from the dual-port RAM cache space and sends it to the bus controller through the 1553B bus. Step 3.3: The logic monitors the address of the RAM read from the slave machine in step 3.2, slave_raddr [15:0]. When the slave machine read addresses slave_raddr [15:7] and slave_raddr [1:0] are equal to the vector word clearing match registers reg_vector_word_match_clear [15:7] and reg_vector_word_match_clear [1:0], respectively, the logic clears the Xth bit of the vector word register, where X is the decimal number of the slave machine read address slave_raddr [5:2].
2. The vector word operation method based on the 1553B bus as described in claim 1, characterized in that, Step 1 specifically includes the following sub-steps: Step 1.1: Create a 16-bit x 32K dual-port RAM on the FPGA of the remote terminal. Connect one end of the RAM to the host and the other end to the MBI slave. Sixteen buffer spaces are set up in RAM. The master writes the data to be sent into the 16 buffer spaces, and the slave reads the data to be sent from the 16 buffer spaces. Step 1.2: Establish a vector word register reg_vector_word [15:0] for the remote terminal. The host and slave can read the value of the vector word, and the logic can write to the vector word register. That is, the host can set the vector word, and the slave can clear the vector word. The register has 16 bits, and each bit corresponds to a cache space of a dual-port RAM. Step 1.3: Establish a vector word set matching register reg_vector_word_match_set [15:0] for the remote terminal. This register is set by the slave device and is used to match the write address of the master device. Step 1.4: Establish a vector word clearing and matching register reg_vector_word_match_clear[15:0] for the remote terminal. This register is set by the slave device and is used to match the slave device's read address.