Processor performance analysis method, apparatus, electronic device, and storage medium

Abstract

This application provides a processor performance analysis method, apparatus, electronic device, and storage medium. This solution is applicable to performance analysis of various processors, including those with CISC instruction sets, RISC reduced instruction sets (especially RISC-V), or VLIM instruction set architectures, such as CPUs, IoT chips, and audio / video chips. The processor performance analysis method includes: acquiring waveform data generated during processor simulation verification; processing the waveform data according to pre-set waveform matching rules to obtain processor event information and processor behavior information; and generating interactive graphs for processor performance analysis based on the processor event information and the processor behavior information. This solution can improve the efficiency of processor performance analysis.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a processor performance analysis method, apparatus, electronic device, and storage medium. Background Technology

[0002] During processor design, it is necessary to analyze the processor's performance in order to optimize it based on the analysis results and obtain a processor that meets the design requirements. When performing processor performance analysis, the first step is to obtain waveform data of the processor through simulation verification methods. This waveform data includes the state of each component in the processor at each moment during the simulation verification process. Then, the processor's performance is analyzed based on this waveform data.

[0003] Currently, when analyzing processor performance, the first step is to identify performance hotspots based on waveform data, and then analyze the waveforms corresponding to each performance hotspot in turn.

[0004] However, analyzing waveforms directly from waveform data requires a considerable amount of time and effort, resulting in low efficiency in processor performance analysis. Summary of the Invention

[0005] In view of this, embodiments of this application provide a processor performance analysis method, apparatus, electronic device, and storage medium to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the embodiments of this application, a processor performance analysis method is provided, comprising: acquiring waveform data generated during the simulation verification of a processor; processing the waveform data according to a pre-set waveform matching rule to obtain processor event information and processor behavior information, wherein the processor event information includes at least one of the number of occurrences of performance-affecting behaviors and the number of executions of target instructions, and the processor behavior information includes descriptive information of performance-affecting behaviors; and generating interactive graphs for performing performance analysis on the processor based on the processor event information and the processor behavior information.

[0007] According to a second aspect of the embodiments of this application, a processor performance analysis apparatus is provided, comprising: an acquisition unit, configured to acquire waveform data generated during the simulation verification of a processor; an extraction unit, configured to process the waveform data according to a pre-set waveform matching rule to obtain processor event information and processor behavior information, wherein the processor event information includes at least one of the number of occurrences of performance-affecting behaviors and the number of executions of target instructions, and the processor behavior information includes descriptive information of performance-affecting behaviors; and a generation unit, configured to generate interactive graphs for performing performance analysis on the processor based on the processor event information and the processor behavior information.

[0008] According to a third aspect of the present application, an electronic device is provided, including: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, which causes the processor to perform the operation corresponding to the processor performance analysis method provided in the first aspect.

[0009] According to a fourth aspect of the embodiments of this application, a computer storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the processor performance analysis method described in the first aspect above.

[0010] According to a fifth aspect of the embodiments of this application, a computer program product is provided, including computer instructions that instruct a computing device to execute the processor performance analysis method described in the first aspect above.

[0011] According to the processor performance analysis scheme provided in this application, after acquiring waveform data generated during processor simulation verification, processor event information and processor behavior information are obtained by processing the waveform data. Then, interactive graphs for processor performance analysis are generated based on the processor event information and processor behavior information. Since processor event information includes the number of occurrences of performance-affecting behaviors and the number of executions of target instructions, while processor behavior information includes descriptive information about performance-affecting behaviors, interactive graphs allow for more targeted processor performance analysis. Compared to aimless waveform analysis, this saves time and effort in performance analysis, thereby improving the efficiency of processor performance analysis. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0013] Figure 1 This is a schematic diagram of an exemplary system applied in one embodiment of this application;

[0014] Figure 2 This is a flowchart of a processor performance analysis method according to an embodiment of this application;

[0015] Figure 3 This is a flowchart of a first interactive graph generation method according to an embodiment of this application;

[0016] Figure 4 This is a schematic diagram of a first interactive diagram according to an embodiment of this application;

[0017] Figure 5 This is a schematic diagram of a first interactive diagram according to another embodiment of this application;

[0018] Figure 6 This is a schematic diagram of a second interactive diagram according to an embodiment of this application;

[0019] Figure 7 This is a schematic diagram of a second interactive diagram according to another embodiment of this application;

[0020] Figure 8 This is a schematic diagram of a processor performance analysis device according to an embodiment of this application;

[0021] Figure 9 This is a schematic diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0022] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the essence of the present application, well-known methods, processes, and flows are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0023] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows.

[0024] Processor simulation verification: During the processor design process, data processing is simulated using intermediate design artifacts to verify the processor's performance. Based on the verification results, the intermediate design artifacts are iteratively optimized to obtain an intermediate design artifact that meets the design requirements. The intermediate design artifact can be the processor's hardware code; the processor can be manufactured based on the completed hardware code.

[0025] Waveform data: Waveforms obtained during the simulation and verification of the processor. The waveform data includes the flipping information of each signal at each moment during the simulation and verification process, which can indicate the state of each component in the processor at each moment.

[0026] Interactive graphs: Data graphs displayed in an interactive interface that can interact with users, such as responding to user operation commands by zooming in or out, scaling the horizontal and vertical axes, switching data sources, etc. The data can be in various forms such as line graphs and bar charts.

[0027] Exemplary System

[0028] Figure 1 An exemplary system for a processor performance analysis method applicable to embodiments of this application is shown. For example... Figure 1 As shown, the system includes a verification server 101, a processor performance analysis device 102, and at least one display terminal 103.

[0029] Verification server 101 can simulate the processor using simulation software or a hardware simulation accelerator, and execute benchmark programs or benchmark program slices through the simulated processor, collecting waveform data generated during the execution of benchmark programs or benchmark program slices. Verification server 101 can obtain intermediate design products for the processor, such as processor hardware code. Based on these intermediate design products, the processor can be simulated using simulation software or a hardware simulation accelerator. After inputting benchmark programs or benchmark program slices into the simulated processor, the simulated processor executes the benchmark programs or benchmark program slices. Verification server 101 can then send the acquired waveform data to processor performance analysis device 102.

[0030] After receiving waveform data, the processor performance analysis device 102 can extract processor event information and processor behavior information from the waveform data, and then generate an interactive graph based on the processor event information and processor behavior information. The interactive graph can display relevant information about events and behaviors that affect processor performance. The processor performance analysis device 102 can send the generated interactive graph to the display terminal 103.

[0031] The display terminal 103 includes a display screen for image display. After receiving an interactive graph from the processor performance analysis device 102, the display terminal 103 displays the interactive graph through an interactive interface. Users can perform operations such as zooming in and out of the interactive graph, scaling the horizontal and vertical axes, and switching data sources through the interactive interface displayed on the display terminal 103 to view processor event information and processor behavior information, thereby enabling processor performance analysis.

[0032] This application focuses on the process of generating an interactive graph by the processor performance analysis device 102. The process of generating the interactive graph will be described in detail later.

[0033] Processor performance analysis methods

[0034] Based on the above system, this application provides a processor performance analysis method, which can be executed by the processor performance analysis device 102 in the above system embodiment. The processor performance analysis method will be described in detail below through multiple embodiments.

[0035] Figure 2This is a flowchart of a processor performance analysis method according to an embodiment of this application. Figure 2 As shown, the processor performance analysis method includes the following steps:

[0036] Step 201: Obtain waveform data generated during the processor's simulation verification process.

[0037] During the simulation and verification of the processor, waveform data is generated. The waveform data includes the toggle information of each signal at each moment during the simulation and verification process. The toggle information indicates whether the signal is binary 1 or 0. Based on the waveform data, the state of each component in the processor at each moment can be determined.

[0038] Step 202: Process the waveform data according to the pre-set waveform matching rules to obtain processor event information and processor behavior information.

[0039] Processor event information includes at least one of the number of times a performance-impacting behavior occurred and the number of times the target instruction was executed. Processor behavior information includes descriptive information about the performance-impacting behavior, which may specifically include the time when the performance-impacting behavior occurred. Performance-impacting behaviors are those that occur during processor operation and affect processor performance.

[0040] Since waveform data can indicate the state of each component in the processor at each moment and includes the toggling information of each signal at each moment, performance-impacting behaviors and the target instructions executed can be identified from the waveform data. This allows for the acquisition of descriptive information about the performance-impacting behaviors, and the counting of occurrences of various performance-impacting behaviors and the number of times the target instructions are executed. This yields processor behavior information including descriptive information about the performance-impacting behaviors, and processor event information including the number of occurrences of the performance-impacting behaviors and the number of times the target instructions are executed.

[0041] The target instruction is a predetermined instruction that can be used to evaluate processor performance. Since the performance impact behavior and the target instruction have corresponding waveform characteristics in the waveform data, waveform matching rules can be pre-defined based on these characteristics. Then, the waveform data can be processed according to these matching rules to obtain processor event information and processor behavior information.

[0042] When processing waveform data according to waveform matching rules, corresponding scripts can be created based on the waveform matching rules. The created scripts can then be used to process the waveform data and extract processor event information and processor behavior information.

[0043] Step 203: Generate interactive graphs for analyzing processor performance based on processor event information and processor behavior information.

[0044] Since processor event information includes the number of occurrences of performance-impacting behaviors and the number of executions of target instructions, both of which are related to processor performance, an interactive graph can be generated based on the processor event information. This interactive graph can then be used to analyze processor performance. The specific occurrence time and percentage of performance-impacting behaviors are also related to processor performance; therefore, an interactive graph can also be generated based on processor behavior information, and this interactive graph can then be used to analyze processor performance.

[0045] When generating interactive graphs based on processor event information and processor behavior information, open-source tools such as Pyecharts and Echarts can be used to generate interactive graphs based on processor event information and processor behavior information.

[0046] It should be understood that the interactive graph generated based on processor event information and the interactive graph generated based on processor behavior information can be different interactive graphs, or they can be different information displayed in the same interactive graph. This application does not limit this.

[0047] In this embodiment, after acquiring waveform data generated during processor simulation verification, processor event information and processor behavior information are obtained through waveform data processing. Then, interactive graphs for analyzing processor performance are generated based on the processor event information and processor behavior information. Since processor event information includes the number of occurrences of performance-influencing behaviors and the number of times target instructions are executed, while processor behavior information includes descriptive information about performance-influencing behaviors, interactive graphs allow for more targeted processor performance analysis. Compared to aimless waveform analysis, this saves time and effort in performance analysis, thereby improving the efficiency of processor performance analysis.

[0048] In one possible implementation, when generating the interactive graph, a first interactive graph can be generated based on processor event information. The first interactive graph is used to indicate at least one of the following two:

[0049] (i) The relationship between the frequency of performance-related behaviors and time.

[0050] (ii) The relationship between the number of times the target instruction is executed and time.

[0051] The relationship between the frequency of performance-impacting behaviors and the frequency of target command executions over time can be displayed in different first interactive graphs or in the same first interactive graph. When displaying the relationship between the frequency of performance-impacting behaviors and the frequency of target command executions over time in the same first interactive graph, the relationship between the frequency of performance-impacting behaviors and the frequency of target command executions over time can be hidden or displayed in the first interactive graph based on user interaction commands.

[0052] When hiding or displaying the change in the frequency of performance-impacting behaviors over time in the first interactive graph, since there may be multiple performance-impacting behaviors, you can either hide or display only the change in the frequency of some performance-impacting behaviors over time, or you can hide or display the change in the frequency of all performance-impacting behaviors over time. Similarly, when hiding or displaying the change in the execution frequency of target instructions over time in the first interactive graph, since there may be multiple types of target instructions, you can either hide or display only the change in the execution frequency of some types of target instructions over time, or you can hide or display the change in the execution frequency of all types of target instructions over time.

[0053] In this embodiment, the distribution of performance-impacting behaviors during processor simulation verification can be determined based on the relationship between the frequency of occurrence of performance-impacting behaviors and time. Similarly, the execution distribution of target instructions during processor simulation verification can be determined based on the relationship between the number of executions of target instructions and time. Since both the frequency of occurrence of performance-impacting behaviors and the number of executions of target instructions are related to processor performance, processor performance can be analyzed based on a first interactive graph that includes the relationship between the frequency of occurrence of performance-impacting behaviors and time, and / or the relationship between the number of executions of target instructions and time.

[0054] Figure 3 This is a flowchart of a first interactive graph generation method according to an embodiment of this application. Figure 3 Therefore, the first interactive graph generation method includes the following steps:

[0055] Step 301: Divide the processor's simulation verification time into at least two consecutive time segments.

[0056] The processor simulation verification is performed continuously over a period of time. After acquiring the waveform data, the processor simulation verification time can be divided into at least two consecutive time segments, such that each time segment includes at least two clock cycles of the processor.

[0057] To facilitate analysis of the frequency of performance-impacting behaviors and the trend of target instruction execution times over time, each segmented time includes the same number of clock cycles, for example, 200 clock cycles per time segment. It should be understood that the length of the time segment can be set based on the waveform data. For example, when the processor simulation verification time is long, each time segment can include a larger number of clock cycles; when the processor simulation verification time is short, each time segment includes a smaller number of clock cycles. This application does not limit the number of clock cycles included in each time segment.

[0058] Each time segment consists of multiple consecutive clock cycles, and the clock cycles in adjacent time segments are consecutive. The sequential combination of the time segments constitutes the duration for the processor to perform simulation verification.

[0059] Step 302: Calculate the total number of times the performance-affecting behavior occurs within each time segment.

[0060] After dividing the simulation verification time into multiple time segments, the total number of occurrences of performance-impacting behaviors within each time segment is calculated. Since there may be multiple types of performance-impacting behaviors, the total number of occurrences of each type of behavior within each time segment can be calculated separately, or the total number of occurrences of all performance-impacting behaviors within each time segment can be calculated.

[0061] For example, there are 5 types of performance-impacting behaviors, and the total number of occurrences of each type of performance-impacting behavior in each time segment is counted.

[0062] Step 303: Calculate the total number of times the target instruction is executed within each time segment.

[0063] After dividing the simulation verification time into multiple time segments, the total number of times the target instruction is executed within each time segment is calculated. Since there may be multiple target instructions, the total number of times each type of target instruction is executed within each time segment can be calculated separately, or the total number of times all target instructions are executed within each time segment can be calculated separately.

[0064] For example, if there are 3 types of target instructions, then the total number of times each type of target instruction is executed in each time segment will be counted.

[0065] Step 304: Generate a first interactive graph with the time segment segmentation point as the x-axis and the total number of occurrences and / or total number of executions as the y-axis.

[0066] After determining the total number of occurrences of performance-impacting behaviors and the total number of executions of target instructions within each time segment, a first interactive graph is generated with the time segment division point as the horizontal axis. The vertical axis of the first interactive graph can be the total number of occurrences of performance-impacting behaviors within each time segment, the total number of executions of target instructions within each time segment, or both the total number of occurrences of performance-impacting behaviors and the total number of executions of target instructions within each time segment.

[0067] When there are multiple performance-impacting behaviors, based on the user's interaction instructions, the total number of occurrences of different performance-impacting behaviors in each time segment can be displayed in the first interactive graph, or only the total number of occurrences of a certain performance-impacting behavior in each time segment can be displayed in the first interactive graph.

[0068] When there are multiple target instructions, depending on the user's interaction instructions, the total number of executions of different target instructions in each time segment can be displayed in the first interactive graph, or only the total number of executions of a certain target instruction in each time segment can be displayed in the first interactive graph.

[0069] Figure 4 This is a schematic diagram of a first interactive diagram according to an embodiment of this application. Figure 4 As shown, the horizontal axis represents the dividing point of a time segment, and the vertical axis represents the number of times the action occurred or the number of times the instruction was executed. The number on the horizontal axis indicates the time segment number; for example, 5 represents the 5th time segment. Each time segment consists of 200 clock cycles. Users can use interactive commands to zoom the horizontal axis to decrease or increase the number of time segments displayed. Figure 4 The vertical coordinate of each inflection point of the curve shown represents the total number of times the corresponding performance-affecting behavior occurs within the time segment corresponding to the horizontal coordinate of that inflection point, or the total number of times the corresponding target instruction is executed within the time segment corresponding to the horizontal coordinate of that inflection point. Figure 4 The curve shown is an example that can represent the total number of times pipeline losses, cache misses, or branch prediction errors occur in each time segment, or it can represent the total number of times arithmetic instructions, memory access instructions, jump instructions, or coprocessor instructions are executed in each time segment.

[0070] Figure 5 This is a schematic diagram of a first interactive diagram according to another embodiment of this application. Figure 4 The first interactive graph shown includes a curve compared to, Figure 5The first interactive graph shown includes two curves, which can represent the total number of occurrences of two performance-impacting behaviors in each time segment, or the total number of occurrences of two target instructions in each time segment, or identify the total number of occurrences of a performance-impacting behavior and a target instruction in each time segment.

[0071] In one example, curve 501 represents the total number of pipeline losses occurring within each time segment, and curve 502 represents the total number of buffer misses occurring within each time segment. In another example, curve 501 represents the total number of pipeline losses occurring within each time segment, and curve 502 represents the total number of jump instructions executed within each time segment.

[0072] When there are multiple performance-impacting behaviors and multiple target instructions, the total number of occurrences of at least one performance-impacting behavior in each time segment and the total number of executions of at least one target instruction in each time segment can be displayed in the first interactive graph based on the user's interaction instructions.

[0073] In this embodiment, by dividing the simulation verification time into multiple consecutive time segments, the total number of occurrences of performance-influencing behaviors and the total number of executions of target instructions within each time segment are calculated. This generates a first interactive graph with the time segment division point as the horizontal axis and the total number of occurrences of performance-influencing behaviors and / or the total number of executions of target instructions as the vertical axis. Based on the first interactive graph, the distribution of each performance-influencing behavior and each target instruction within each time segment can be determined, and the changing trends of each performance-influencing behavior and each target instruction over time can be determined. This allows for the analysis of processor performance from multiple dimensions, ensuring the accuracy and comprehensiveness of the processor performance analysis.

[0074] In one possible implementation, the performance-impacting behavior includes at least one of pipeline loss, cache miss, and branch prediction error, and the target instruction includes at least one of arithmetic instructions, memory access instructions, jump instructions, and coprocessor instructions.

[0075] In this embodiment, since pipeline failures, cache misses, and branch prediction errors all affect processor performance, and the execution of arithmetic instructions, memory access instructions, jump instructions, and coprocessor instructions can also reflect processor performance, pipeline failures, cache misses, and branch prediction errors can be considered as performance-impacting behaviors, and arithmetic instructions, memory access instructions, jump instructions, and coprocessor instructions can be considered as target instructions. Based on each performance-impacting behavior and each target instruction, an interactive graph is generated to analyze processor performance. This allows for the intuitive identification of events causing significant performance loss, the overall pipeline stall time ratio, etc., enabling a direct analysis of performance loss points and further precise waveform analysis to confirm problems, thus improving the efficiency and accuracy of processor performance analysis.

[0076] In one possible implementation, when generating the interactive graph, a second interactive graph can be generated based on processor behavior information, wherein the second interactive graph is used to indicate the behavioral results of performance-influencing behavior at different times.

[0077] Processor behavior information includes descriptive information about performance-impacting behaviors, which includes the occurrence time and outcome of the performance-impacting behaviors. For example, when the performance-impacting behavior includes a cache miss, the generated second interactive graph can indicate whether a cache miss occurs at each time point during the simulation verification process. When the performance-impacting behavior includes a branch prediction error, the generated second interactive graph can indicate whether the prediction result of each branch prediction during the simulation verification process is successful or unsuccessful.

[0078] In this embodiment of the application, the second interactive graph generated based on the processor behavior information can indicate the behavior results of performance-affecting behaviors at different times. Thus, the time of occurrence of each performance-affecting behavior can be determined based on the second interactive graph. Combined with the instructions executed at each time during the processor simulation verification process, the loss points that cause processor performance loss can be intuitively determined. Furthermore, by analyzing the waveform, the problem causing performance loss can be identified, thereby improving the efficiency of processor performance analysis.

[0079] In one possible implementation, when generating the second interactive graph based on processor behavior information, if the performance-impacting behavior includes cache misses, then a second interactive graph is generated with time as the x-axis and memory access address as the y-axis, where cache misses and non-cache misses are plotted with different labels. If the performance-impacting behavior includes branch prediction errors, then a second interactive graph is generated with time as the x-axis and branch instruction pointer as the y-axis, where correctly predicted branches and incorrectly predicted branches are plotted with different labels.

[0080] Figure 6This is a schematic diagram of a second interactive diagram according to an embodiment of this application. Figure 6 As shown, the horizontal axis represents the clock cycle, and the vertical axis represents the branch instruction pointer. Black dots indicate that the branch prediction for the corresponding clock cycle is correct, and black triangles indicate that the branch prediction for the corresponding clock cycle is incorrect.

[0081] In this embodiment, when performance-impacting behaviors include cache misses, a second interactive graph is generated, with time as the horizontal axis and memory access address as the vertical axis. In this second interactive graph, cache misses and non-cache misses are plotted using different markers, and the overall result represents the memory access behavior. This memory access behavior can be compared with the predicted hardware algorithm behavior to quickly determine if the processor has performance issues. Simultaneously, other data such as the cache miss rate can also be obtained for subsequent analysis.

[0082] In this embodiment, when performance-impacting behaviors include branch prediction errors, a second interactive graph is generated with time as the horizontal axis and the branch instruction pointer (branch PC) as the vertical axis. In the second interactive graph, correctly predicted points and incorrectly predicted points are plotted using different markers to obtain branch jump behaviors. Based on the obtained branch jump behaviors, analysis can be performed more intuitively, branch prediction accuracy can be obtained, and comparisons can be made with the performance model.

[0083] In one possible implementation, when generating the second interactive graph based on processor behavior information, a second interactive graph with time as the horizontal axis and instruction pointer as the vertical axis can be generated based on the processor behavior information. Based on this second interactive graph, the program flow can be back-annotated through disassembly to obtain the original program function labels. The original program function labels are used to determine the runtime and instruction count percentages of each original program function.

[0084] Figure 7 This is a schematic diagram of a second interactive diagram according to another embodiment of this application. The horizontal axis represents the clock cycle, and the vertical axis represents the instruction pointer. The black curve in the diagram is composed of multiple superimposed black dots. The vertical coordinate of a black dot represents the memory address accessed by a function in the clock cycle corresponding to the horizontal coordinate of that black dot.

[0085] In this embodiment, a second interactive graph is generated based on processor behavior information, with time as the horizontal axis and instruction pointer (PC) as the vertical axis. At the same time, the program flow can be back-annotated using the original program function labels obtained by disassembly, thereby obtaining the running time percentage and instruction count percentage of each function. This allows for the rapid location of program hotspots, and further analysis of the waveform can identify the problems causing performance loss, thus improving the efficiency of processor performance analysis.

[0086] In one possible implementation, the processor can be simulated using simulation software or a hardware simulation accelerator, and then the processor can be verified by executing a benchmark program or a slice of benchmark program through the simulated processor, thereby obtaining waveform data generated during the processor verification process.

[0087] In this embodiment, the processor can be simulated using simulation software or a hardware simulation accelerator. The simulated processor can execute benchmark programs or benchmark program slices, which can obtain waveform data generated during the processor verification process. The waveform data can then be processed in the manner described in this embodiment to generate an interactive graph. This makes the processor performance analysis method provided in this embodiment applicable to different simulation verification schemes, ensuring the applicability of the processor performance analysis method.

[0088] Processor performance analysis device

[0089] Corresponding to the above method embodiments, Figure 8 A schematic diagram of a processor performance analysis device is shown. Figure 8 As shown, the processor performance analysis device 102 includes:

[0090] Acquisition unit 801 is used to acquire waveform data generated during the simulation verification of the processor;

[0091] The extraction unit 802 is used to process waveform data according to a pre-set waveform matching rule to obtain processor event information and processor behavior information. The processor event information includes at least one of the number of occurrences of performance-affecting behaviors and the number of executions of target instructions. The processor behavior information includes descriptive information of performance-affecting behaviors.

[0092] The generation unit 803 is used to generate interactive graphs for processor performance analysis based on processor event information and processor behavior information.

[0093] In this embodiment, after the acquisition unit 801 acquires the waveform data generated during the simulation verification of the processor, the extraction unit 802 processes the waveform data to obtain processor event information and processor behavior information. The generation unit 803 then generates interactive graphs for analyzing processor performance based on the processor event information and processor behavior information. Since the processor event information includes the number of occurrences of performance-affecting behaviors and the number of times the target instruction is executed, while the processor behavior information includes descriptive information about performance-affecting behaviors, the interactive graphs allow for more targeted analysis of processor performance. Compared to aimless analysis of waveforms, this saves time and effort in performance analysis, thereby improving the efficiency of processor performance analysis.

[0094] It should be noted that the processor performance analysis device in this embodiment is used to implement the corresponding processor performance analysis method in the foregoing method embodiment, and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0095] electronic devices

[0096] Figure 9 This is a schematic block diagram of an electronic device provided in an embodiment of this application. Specific embodiments of this application do not limit the specific implementation of the electronic device. Figure 9 As shown, the electronic device may include: a processor 902, a communications interface 904, a memory 906, and a communications bus 908. Wherein:

[0097] The processor 902, communication interface 904, and memory 906 communicate with each other via communication bus 908.

[0098] Communication interface 904 is used to communicate with other electronic devices or servers.

[0099] The processor 902 is used to execute program 910, which can specifically execute the relevant steps in any of the aforementioned processor performance analysis method embodiments.

[0100] Specifically, program 910 may include program code that includes computer operation instructions.

[0101] The processor 902 may be a CPU, an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application. The smart device includes one or more processors, which may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.

[0102] RISC-V is an open-source instruction set architecture based on the Reduced Instruction Set Computing (RISC) principle. It can be applied to various aspects of microcontrollers and FPGA chips, specifically in areas such as IoT security, industrial control, mobile phones, and personal computers. Because its design considers small size, speed, and low power consumption, it is particularly suitable for modern computing devices such as warehouse-scale cloud computers, high-end mobile phones, and tiny embedded systems. With the rise of AIoT (Artificial Intelligence of Things), the RISC-V instruction set architecture is receiving increasing attention and support and is expected to become the next generation of widely used CPU architecture.

[0103] The computer operation instructions in this application embodiment can be computer operation instructions based on the RISC-V instruction set architecture. Correspondingly, the processor 902 can be designed based on the RISC-V instruction set. Specifically, the processor chip in the electronic device provided in this application embodiment can be a chip designed using the RISC-V instruction set. This chip can execute executable code based on the configured instructions, thereby implementing the processor performance analysis method in the above embodiment.

[0104] Memory 906 is used to store program 910. Memory 906 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0105] Specifically, program 910 can be used to cause processor 902 to execute the processor performance analysis method in any of the foregoing embodiments.

[0106] The specific implementation of each step in program 910 can be found in the corresponding steps and units described in any of the aforementioned processor performance analysis method embodiments, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the devices and modules described above can be referred to the corresponding process descriptions in the aforementioned method embodiments, and will not be repeated here.

[0107] The electronic device of this application, after acquiring waveform data generated during processor simulation verification, processes the waveform data to obtain processor event information and processor behavior information. Based on the processor event information and processor behavior information, interactive graphs for analyzing processor performance are generated. Since processor event information includes the number of occurrences of performance-affecting behaviors and the number of times target instructions are executed, while processor behavior information includes descriptive information about performance-affecting behaviors, interactive graphs allow for more targeted analysis of processor performance. Compared to aimless waveform analysis, this saves time and effort in performance analysis, thereby improving the efficiency of processor performance analysis.

[0108] Computer storage media

[0109] This application also provides a computer-readable storage medium storing instructions for causing a machine to execute the processor performance analysis method as described herein. Specifically, a system or apparatus equipped with a storage medium storing software program code that implements the functions of any of the embodiments described above, and enabling the computer (or CPU or MPU) of the system or apparatus to read and execute the program code stored in the storage medium.

[0110] In this case, the program code read from the storage medium can itself implement the function of any of the above embodiments, and therefore the program code and the storage medium storing the program code constitute part of this application.

[0111] Examples of storage media used to provide program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.

[0112] Computer program products

[0113] This application also provides a computer program product, including computer instructions that instruct a computing device to perform any corresponding operation in the above-described plurality of method embodiments.

[0114] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.

[0115] The methods described in the embodiments of this application can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code downloaded over a network that is originally stored in a remote recording medium or a non-transitory machine-readable medium and will be stored in a local recording medium. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code that, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the methods shown herein.

[0116] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0117] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.

Claims

1. A processor performance analysis method, comprising: Acquire waveform data generated during processor simulation verification; According to the pre-set waveform matching rules, the waveform data is processed to obtain processor event information and processor behavior information. The processor event information includes at least one of the number of occurrences of performance-impacting behaviors and the number of executions of target instructions. The processor behavior information includes descriptive information of performance-impacting behaviors. Based on the processor event information and the processor behavior information, an interactive graph for performance analysis of the processor is generated. The step of processing the waveform data according to a pre-defined waveform matching rule to obtain processor event information and processor behavior information includes: The performance-impacting behaviors and the executed target instructions are identified from the waveform data, thereby obtaining descriptive information of the performance-impacting behaviors. The occurrence frequency of each type of performance-impacting behavior and the execution frequency of the target instructions are counted, thereby obtaining processor behavior information including descriptive information of the performance-impacting behaviors, and processor event information including the occurrence frequency of the performance-impacting behaviors and the execution frequency of the target instructions.

2. The method according to claim 1, wherein, The step of generating an interactive graph for performance analysis of the processor based on the processor event information and the processor behavior information includes: A first interactive graph is generated based on the processor event information, wherein the first interactive graph is used to indicate at least one of the following: the relationship between the number of occurrences of the performance-affecting behavior and time, and the relationship between the number of executions of the target instruction and time.

3. The method according to claim 2, wherein, The step of generating the first interactive graph based on the processor event information includes: The simulation verification time of the processor is divided into at least two consecutive time segments, wherein each time segment includes at least two clock cycles of the processor; Calculate the total number of times the performance-impacting behavior occurs within each of the time segments; Calculate the total number of times the target instruction is executed within each time segment; Generate a first interactive graph with the time segment segmentation point as the horizontal axis and the total number of occurrences and / or the total number of executions as the vertical axis.

4. The method according to claim 3, wherein, The performance impact behaviors include at least one of pipeline loss, cache miss, and branch prediction error; The target instruction includes at least one of arithmetic instructions, memory access instructions, jump instructions, and coprocessor instructions.

5. The method according to claim 1, wherein, The step of generating an interactive graph for performance analysis of the processor based on the processor event information and the processor behavior information includes: A second interactive graph is generated based on the processor behavior information, wherein the second interactive graph is used to indicate the behavioral results of the performance impact behavior at different times.

6. The method according to claim 5, wherein, The step of generating a second interactive graph based on the processor behavior information includes: When the performance-impacting behavior includes cache misses, a second interactive graph is generated based on the processor behavior information, with time as the horizontal axis and memory access address as the vertical axis. In this second interactive graph, cache misses and cache non-misses are drawn with different labels. And / or, When the performance-impacting behavior includes branch prediction errors, a second interactive graph is generated based on the processor behavior information, with time as the horizontal axis and the branch instruction pointer as the vertical axis. Points with correct branch prediction and points with incorrect branch prediction are drawn with different labels in the second interactive graph.

7. The method according to claim 5, wherein, The step of generating an interactive graph for performance analysis of the processor based on the processor event information and the processor behavior information includes: Based on the processor behavior information, a second interactive graph is generated with time as the horizontal axis and instruction pointer as the vertical axis. This second interactive graph is used to back-annotate the program flow through disassembly to obtain original program function labels. The original program function labels are used to determine the percentage of runtime and instruction count for each original program function.

8. The method according to any one of claims 1-7, wherein, The method further includes: The processor is simulated using simulation software or hardware emulation accelerators. The processor is verified by executing benchmark programs or benchmark program slices on a simulated processor.

9. A processor performance analysis device, comprising: The acquisition unit is used to acquire waveform data generated during the simulation and verification of the processor. The extraction unit is used to process the waveform data according to a pre-set waveform matching rule to obtain processor event information and processor behavior information. The processor event information includes at least one of the number of occurrences of performance-impacting behaviors and the number of executions of target instructions. The processor behavior information includes descriptive information of the performance-impacting behaviors. The generation unit is used to generate interactive graphs for performance analysis of the processor based on the processor event information and the processor behavior information, respectively. The extraction unit is further configured to identify performance-impacting behaviors and executed target instructions from the waveform data, thereby obtaining descriptive information of the performance-impacting behaviors, and counting the occurrence times of various performance-impacting behaviors and the execution times of the target instructions, thereby obtaining processor behavior information including descriptive information of the performance-impacting behaviors, and processor event information including the occurrence times of the performance-impacting behaviors and the execution times of the target instructions.

10. An electronic device, comprising: The processor, memory, communication interface, and communication bus communicate with each other through the communication bus. The memory is used to store at least one executable instruction that causes the processor to perform the operation corresponding to the processor performance analysis method as described in any one of claims 1-8.

11. A computer storage medium having a computer program stored thereon, which, when executed by a processor, implements the processor performance analysis method as claimed in any one of claims 1-8.

12. A computer program product comprising computer instructions that instruct a computing device to perform a processor performance analysis method as claimed in any one of claims 1-8.

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