Electronic devices

Abstract

The present disclosure provides an electronic device including a pixel circuit and a protection circuit. The pixel circuit includes a driving transistor. The protection circuit includes a first connection transistor, a first switch transistor and a logic circuit. The first connection transistor is coupled to the driving transistor. The first switch transistor is coupled to the first connection transistor. The logic circuit is coupled to the first switch transistor. The electronic device disclosed in the present disclosure can provide a pixel protection function through the protection circuit coupled to the pixel circuit.

Description

Technical Field

[0001] The present disclosure relates to a device, and more particularly to an electronic device with a component protection function. Background Art

[0002] With the advancement of technology, electronic devices are gradually being designed to be thinner and smaller. As a result, the reliability of components may face greater and greater challenges. If the components of electronic devices are safety-related issues, such as damage caused by continuous high current and high temperature, these problems are unavoidable. Summary of the invention

[0003] The present disclosure is directed to an electronic device that can provide a component protection function through a protection circuit coupled to a pixel circuit.

[0004] According to some embodiments of the present disclosure, the electronic device of the present disclosure includes a pixel circuit and a protection circuit. The pixel circuit includes a driving transistor. The protection circuit includes a first connection transistor, a first switch transistor and a logic circuit. The first connection transistor is coupled to the driving transistor. The first switch transistor is coupled to the first connection transistor. The logic circuit is coupled to the first switch transistor.

[0005] According to some embodiments of the present disclosure, the electronic device of the present disclosure can detect the operating signal of the pixel circuit (such as a scan signal and / or a reset signal) through a protection circuit. When, for example, the operating signal of the pixel circuit is abnormal, the protection circuit can turn off the driving transistor of the pixel circuit of the abnormal pixel, thereby providing a component protection function.

[0006] In order to make the above features and advantages of the present disclosure more obvious and understandable, embodiments are given below with reference to the accompanying drawings for detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of an electronic device according to some embodiments of the present disclosure;

[0008] Figure 2 is another schematic diagram of an electronic device according to some embodiments of the present disclosure;

[0009] Figure 3 is a circuit diagram of an electronic device according to some embodiments of the present disclosure;

[0010] Figure 4 is a signal timing diagram of some embodiments of the present disclosure;

[0011] Figure 5 is a circuit diagram of an electronic device according to some embodiments of the present disclosure;

[0012] Figure 6is a circuit diagram of an electronic device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0014] The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to make it easier for readers to understand and for the simplicity of the drawings, the multiple drawings in the present disclosure only depict a portion of the electronic device, and the specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the figure are only for illustration and are not intended to limit the scope of the present disclosure.

[0015] Certain words are used throughout this disclosure and in the appended claims to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following description and claims, the words "including" and "comprising" are open-ended words and should therefore be interpreted as "including but not limited to..."

[0016] In some embodiments of the present disclosure, terms such as "connection" and "interconnection" may refer to two structures being in direct contact with each other, or may refer to two structures not being in direct contact with each other, with other structures being disposed between the two structures, unless otherwise specified. Such terms may also include situations where both structures are movable or both structures are fixed. In addition, the terms "electrically connected" and "coupled" include any direct and indirect electrical connection means.

[0017] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify the components. They do not imply or represent that the component or components have any previous ordinal numbers, nor do they represent the order of one component and another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make the component with a certain name clearly distinguishable from another component with the same name. The same words may not be used in the claims and the specification. Accordingly, the first component in the specification may be the second component in the claims. It should be noted that the following embodiments can replace, reorganize, and mix the technical features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure.

[0018] It should be noted that the following embodiments may replace, reorganize, or mix features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. Features between embodiments may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0019] In the following embodiments, the electronic device may include a display device, an antenna device, a sensing device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The electronic device includes a diode element, wherein the diode element may or may not emit light. The diode element may, for example, include a PN diode or a PIN diode, but is not limited thereto. The electronic device may, for example, include a liquid crystal (LC), a light-emitting diode, a quantum dot (QD), fluorescence, phosphorescence, other suitable materials, or a combination of the above materials, but the present disclosure is not limited thereto. The light-emitting diode may, for example, include an organic light-emitting diode or an inorganic light-emitting diode. The light-emitting diode may, for example, include an active-matrix organic light-emitting diode (AMOLED), an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro light-emitting diode (micro LED) or a quantum dot light-emitting diode, but the present disclosure is not limited thereto. The antenna device may, for example, be a liquid crystal antenna, but the present disclosure is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but the present disclosure is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the aforementioned, but the present disclosure is not limited thereto.

[0020] In the following embodiments, the first end, the second end and the control end of the transistor may refer to, for example, the source, the gate and the drain of a transistor such as a thin-film transistor (TFT) or a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0021] Figure 1 is a schematic diagram of an electronic device according to some embodiments of the present disclosure. Figure 1, the electronic device 100 includes a pixel circuit 110 and a protection circuit 120. The pixel circuit 110 includes a driving transistor 111, a pixel switch transistor 112, a scanning transistor 113, a reset transistor 114, a diode element 115 and a storage capacitor (Cst) 116. In the present embodiment, a first end of the driving transistor 111 is coupled to a working voltage VDD. A second end of the driving transistor 111 is coupled to a first end of the pixel switch transistor 112. A control end of the driving transistor 111 is coupled to a first end of the driving transistor 111, and is coupled to the scanning transistor 113, the reset transistor 114 and the protection circuit 120 through a circuit node N1. A second end of the pixel switch transistor 112 is coupled to a first end of the diode element 115. The control end of the pixel switch transistor 112 can receive a control signal EM. A first end of the scanning transistor 113 can receive driving data (or display data) Din. A control end of the scanning transistor 113 can receive a scanning signal Sn. A second end of the scanning transistor 113 is coupled to a control end of the driving transistor 111 through a circuit node N1. A first terminal of the reset transistor 114 is coupled to a reset voltage VRST. A second terminal of the reset transistor 114 is coupled to a control terminal of the drive transistor 111 through a circuit node N1. The control terminal of the reset transistor 114 may receive a reset signal RST. A second terminal of the diode element 115 is coupled to a ground voltage VSS. In some embodiments, the diode element 115 may include a light emitting diode 115_1. An anode of the light emitting diode 115_1 is coupled to a second terminal of the pixel switch transistor 112. A cathode of the light emitting diode 115_1 is coupled to a ground voltage VSS. In some embodiments, the diode element 115 may include a plurality of light emitting diodes connected in series. A first terminal of the storage capacitor 116 is coupled to a first terminal of the drive transistor 111, and a second terminal of the storage capacitor 116 is coupled to a control terminal of the drive transistor 111.

[0022] In this embodiment, the driving transistor 111, the pixel switch transistor 112, the scanning transistor 113, and the reset transistor 114 can be P-type thin film transistors or P-type metal oxide semiconductor field effect transistors, but the present disclosure is not limited thereto. In addition, in some embodiments, the pixel circuit 110 can also include other transistors, not limited to Figure 1 The 3T1C pixel circuit architecture shown may be, for example, a circuit architecture composed of seven transistors and two capacitors (7T2C), or may be a circuit architecture composed of eight transistors and two capacitors (8T2C), but the disclosure is not limited thereto. It is worth noting that the protection circuit 120 disclosed herein may be applied in various circuit architectures. In some embodiments, the protection circuit 120 may be on the same substrate as the diode element 115. In some embodiments, the protection circuit 120 may be on a different substrate than the diode element 115.

[0023] In the present embodiment, the pixel circuit 110 can be operated in a reset mode and a driving mode (also referred to as a display mode or a light-emitting mode) during a reset period and a driving period, respectively, according to the driving data, the control signal EM, the scan signal Sn, and the reset signal RST. In the present embodiment, the protection circuit 120 can receive the control signal EM, the scan signal Sn, and the reset signal RST to detect at least one of the scan signal Sn and the reset signal RST. When at least one of the scan signal Sn and the reset signal RST has a signal (voltage) abnormality, the protection circuit 120 can provide a shutdown voltage to the control end of the driving transistor 111 through the circuit node N1 to turn off the driving transistor 111, thereby effectively protecting the diode element 115. In addition, in some embodiments, the protection circuit 120 can also be coupled to other pixel circuits of the electronic device 100.

[0024] Figure 2 is another schematic diagram of an electronic device according to some embodiments of the present disclosure. Figure 2 , the electronic device 200 may include a pixel 210 and a protection circuit 220. The pixel 210 may include a plurality of pixel circuits 210_1 to 210_3, and each of the pixel circuits 210_1 to 210_3 may respectively implement the above-mentioned Figure 1 The pixel circuit 110 of the embodiment, but the number of pixel circuits in the pixel 210 disclosed in the present disclosure is not limited thereto. In some embodiments, the pixel 210 may include one or more pixel circuits. In the present embodiment, the pixel circuits 210_1 to 210_3 may be pixel circuits corresponding to red sub-pixels, green sub-pixels, or blue sub-pixels, for example.

[0025] In this embodiment, the protection circuit 220 includes a logic circuit 221, a switch transistor 222, and connecting transistors 223_1-223_3, wherein the connecting transistors 223_1-223_3 can be respectively coupled to the driving transistors (eg, Figure 1 The logic circuit 221 is coupled to the first terminal of the switch transistor 222. The second terminal of the switch transistor 222 is coupled to the control terminal of the transistors 223_1 to 223_3. The control terminal of the switch transistor 222 can receive the control signal EM. The first terminals of the transistors 223_1 to 223_3 can receive the protection voltage Vp, where the protection voltage Vp can be Figure 1 The second terminals of the transistors 223_1 to 223_3 are respectively coupled to the pixel circuits 210_1 to 210_3. In addition, the logic circuit 221 can receive at least one of the control signal EM and the scan signal and the reset signal (eg, Figure 1The scan signal Sn and the reset signal RST are shown to detect at least one of the scan signal and the reset signal.

[0026] In the present embodiment, the switch transistor 222 and the connection transistors 223_1 to 223_3 may be P-type thin film transistors or P-type metal oxide semiconductor field effect transistors, but the present disclosure is not limited thereto. In the present embodiment, when at least one of the scan signal and the reset signal has a signal (such as a voltage signal) abnormality (such as an abnormality such as a false trigger), the logic circuit 221 can be connected through the switch transistor 222, the connection transistors 223_1 to 223_3 and the circuit nodes (such as Figure 1 The circuit node N1 shown in FIG. 1 provides a shutdown voltage to the control terminal of the driving transistor in the pixel circuits 210_1 to 210_3 to shut down the driving transistor in the pixel circuits 210_1 to 210_3, thereby effectively protecting the diode elements (such as Figure 1 Diode element 115 shown).

[0027] Figure 3 is a circuit diagram of an electronic device according to some embodiments of the present disclosure. Figure 3 , the electronic device 300 may include a pixel 310 and a protection circuit 320. The pixel 310 may include a plurality of pixel circuits 310_1 to 310_3, and each of the pixel circuits 310_1 to 310_3 may implement the above-mentioned Figure 1 The pixel circuit 110 of the embodiment, but the number of pixel circuits in the pixel 310 disclosed in the present invention is not limited thereto. In some embodiments, the pixel 310 may include one or more pixel circuits. In the present embodiment, the pixel circuits 310_1 to 310_3 may be pixel circuits corresponding to red sub-pixels, green sub-pixels, or blue sub-pixels, for example.

[0028] In this embodiment, the protection circuit 320 includes a logic circuit 321, switch transistors 322, 324, connecting transistors 323_1-323_3, and impedance circuits 325, 326, wherein the connecting transistors 323_1-323_3 can be respectively coupled to the driving transistors (eg, Figure 1The logic circuit 321 is coupled to the first end of the switch transistor 324. The second end of the switch transistor 324 is coupled to the first end of the switch transistor 322 and the circuit node N31 between the impedance circuit 325. The second end of the switch transistor 322 is coupled to the control end of the transistors 323_1 to 323_3 and the impedance circuit 326 through the circuit node N32. The control end of the switch transistors 322 and 324 can receive the control signal EM. The first end of the transistors 323_1 to 323_3 can receive the protection voltage Vp, where the protection voltage Vp can be Figure 1 The operating voltage VDD is shown, but the disclosure is not limited thereto. The second terminals of the connecting transistors 323_1 - 323_3 are respectively coupled to the pixel circuits 310_1 - 310_3 .

[0029] In the present embodiment, the impedance circuit 325 may include transistors 325_1 and 325_2. The first terminal of the transistor 325_1 is coupled to the circuit node N31. The second terminal of the transistor 325_1 is coupled to the control terminal of the transistor 325_1 and the first terminal of the transistor 325_2. The second terminal of the transistor 325_2 is coupled to the control terminal of the transistor 325_2 and the ground voltage GND. However, in some embodiments, the impedance circuit 325 may also be other types of impedance circuits, not limited to Figure 3 shown.

[0030] In the present embodiment, the impedance circuit 326 may include a transistor 326_1. A first terminal of the transistor 326_1 may receive a reference voltage V1, wherein the reference voltage V1 is a high level voltage and may be, for example, a protection voltage Vp. A second terminal of the transistor 326_1 is coupled to a control terminal of the transistor 326_1 and a circuit node N32. However, in some embodiments, the impedance circuit 326 may also be other types of impedance circuits, not limited to Figure 3 shown.

[0031] In this embodiment, the logic circuit 321 includes a circuit connection transistor 321_1, a switching circuit 321_2, a circuit switch transistor 321_3, and an impedance circuit 321_4. The circuit connection transistor 321_1 is coupled between the switch transistor 324 and the reference voltage V1. The first end of the circuit connection transistor 321_1 can receive the reference voltage V1. The second end of the circuit connection transistor 321_1 is coupled to the first end of the switch transistor 324. The switching circuit 321_2 is coupled to the control end of the circuit connection transistor 321_1. The circuit switch transistor 321_3 is coupled to the reference voltage V1. The first end of the circuit switch transistor 321_3 can receive the reference voltage V1. The control end of the circuit switch transistor 321_3 can receive the control signal EM. The second end of the circuit switch transistor 321_3 is coupled to the switching circuit 321_2. The switching circuit 321_2 includes a scan transistor 321_21 and a reset transistor 321_22. The first end of the scan transistor 321_21 and the reset transistor 321_22 are coupled to the second end of the circuit switch transistor 321_3. The control end of the scan transistor 321_21 can receive the scan signal Sn. The control end of the reset transistor 321_22 can receive the reset signal RST. The second end of the scan transistor 321_21 and the reset transistor 321_22 are coupled to the impedance circuit 321_4. The impedance circuit 321_4 may include a transistor 321_41. The first end of the transistor 321_41 is coupled to the control end of the transistor 321_41, the control end of the circuit connection transistor 321_1, and the second end of the scan transistor 321_21 and the reset transistor 321_22. The second end of the transistor 321_41 is coupled to the ground voltage GND. However, in some embodiments, the impedance circuit 321_4 may also be other types of impedance circuits, not limited to Figure 3 shown.

[0032] In this embodiment, the circuit connecting transistor 321_1, the connecting transistors 323_1 to 323_3, the scanning transistor 321_21, the reset transistor 321_22, the circuit switching transistor 321_3, the switching transistors 322 and 324, and the transistors 321_41, 325_1, 325_2, and 326_1 may be P-type thin film transistors or P-type metal oxide semiconductor field effect transistors, respectively, but the present disclosure is not limited thereto.

[0033] Also refer to Figure 3 as well as Figure 4 , Figure 4is a signal timing diagram of some embodiments of the present disclosure. In some embodiments of the present disclosure, each of the pixel circuits 310_1 to 310_3 can receive a control signal EM, a reset signal RST, and a scan signal Sn, respectively, so that according to the control signal EM, the reset signal RST, and the scan signal Sn, the operation can be in a setting mode during the setting period P1 between time t0 and time t5, and the operation can be in a driving mode during the driving period P2 between time t5 and time t6. With reference to the following Table 1, during the setting period P1, the control signal EM is a high level voltage to turn off the circuit switch transistor 321_3, the switch transistor 322, the switch transistor 324, and the pixel switch transistors of the pixel circuits 310_1 to 310_3, respectively.

[0034] During the reset period PR from time t1 to time t2, the reset signal RST switches from a high level voltage to a low level voltage to turn on the reset transistors of the pixel circuits 310_1 to 310_3, respectively, and reset the storage capacitors of the pixel circuits 310_1 to 310_3, respectively. During the period PS from time t3 to time t4, the scan signal Sn switches from a high level voltage to a low level voltage to turn on the scan transistors of the pixel circuits 310_1 to 310_3, respectively, and writes the drive data to the storage capacitors of the pixel circuits 310_1 to 310_3, respectively. As shown in the operation states 1 to 3 of Table 1 below, the circuit node N31 maintains a low level voltage, and the circuit node N32 maintains a high level voltage to turn off the connection transistors 323_1 to 323_3.

[0035] In the driving period P2 between time t5 and time t6, the control signal EM is a low level voltage to turn on the circuit switch transistor 321_3, the switch transistor 322, the switch transistor 324 and the pixel switch transistors of the pixel circuits 310_1 to 310_3 respectively. The reset signal RST and the scan signal Sn are high level voltages to turn off the reset transistor and the scan transistor of the pixel circuits 310_1 to 310_3 respectively. As shown in the operation state 4 of Table 1 below, the circuit nodes N31 and N32 are high level voltages to turn off the connection transistors 323_1 to 323_3. It is worth noting that since the scan transistor 321_21 and the reset transistor 321_22 of the switching circuit 321_2 can also receive the reset signal RST and the scan signal Sn, when at least one of the reset signal RST and the scan signal Sn has a signal (voltage) abnormality (false trigger), for example, when at least one of the reset signal RST and the scan signal Sn is converted from a high level voltage to a low level voltage during the driving period P2, at least one of the scan transistor 321_21 and the reset transistor 321_22 is turned on, so that the circuit connection transistor 321_1 is turned on. As shown in the operation states 5 to 7 of the following Table 1, when at least one of the reset signal RST and the scan signal Sn has a signal (voltage) abnormality, the circuit nodes N31 and N32 can be switched to a low level voltage respectively to turn on the connection transistors 323_1 to 323_3. In this regard, the circuit connection transistor 321_1 can provide the reference voltage V1 to the control terminals of the connection transistors 323_1 to 323_3 through the switch transistors 322 and 324 and the circuit nodes N31 and N32 to turn on the connection transistors 323_1 to 323_3. Then, the connection transistors 323_1 to 323_3 can respectively provide the protection voltage Vp to the driving transistors of the pixel circuits 310_1 to 310_3 to turn off the driving transistors. Therefore, the protection circuit 320 can effectively protect the diode elements in the pixel circuits 310_1 to 310_3 of the pixel 310, and can prevent the diode elements in the pixel circuits 310_1 to 310_3 from being damaged when at least one of the reset signal RST and the scan signal Sn has an abnormal voltage signal, thereby realizing the current overload protection function of the pixel 310.

[0036]

[0037] Table 1

[0038] In addition, in some embodiments, the switching circuit 321_2 may also include only one of the scanning transistor 321_21 and the reset transistor 321_22, and when a signal (voltage) abnormality occurs in one of the scanning signal Sn and the reset signal RST, the protection circuit 320 can turn on the connecting transistors 323_1~323_3 to turn off the driving transistors of the pixel circuits 310_1~310_3 respectively, thereby realizing the current overload protection function of the pixel 310.

[0039] Figure 5 is a circuit diagram of an electronic device according to some embodiments of the present disclosure. Figure 5 , the electronic device 500 may include a pixel 510 and a protection circuit 520. The pixel 510 may include a plurality of pixel circuits 510_1 to 510_3, and each of the pixel circuits 510_1 to 510_3 may respectively implement the above-mentioned Figure 1 1 , but the number of pixel circuits in the pixel 510 disclosed herein is not limited thereto. In some embodiments, the pixel 510 may include one or more pixel circuits. In this embodiment, the pixel circuits 510_1 to 510_3 may be pixel circuits corresponding to a red sub-pixel, a green sub-pixel, or a blue sub-pixel, for example.

[0040] In this embodiment, the protection circuit 520 includes a logic circuit 521, switch transistors 522, 524, connecting transistors 523_1-523_3, and impedance circuits 525, 526, wherein the connecting transistors 523_1-523_3 can be respectively coupled to the driving transistors (eg Figure 1 The logic circuit 521 is coupled to the first end of the switch transistor 524 and the first end of the switch transistor 522 through the circuit node N51. The second end of the switch transistor 524 is coupled to the impedance circuit 525. The second end of the switch transistor 522 is coupled to the control end of the transistors 523_1 to 523_3 and the impedance circuit 526 through the circuit node N52. The control end of the switch transistors 522 and 524 can receive the control signal EM. The first end of the transistors 523_1 to 523_3 can receive the protection voltage Vp, where the protection voltage Vp can be Figure 1 The operating voltage VDD is shown, but the disclosure is not limited thereto. The second terminals of the connecting transistors 523_1 - 523_3 are respectively coupled to the pixel circuits 510_1 - 510_3 .

[0041] In this embodiment, the impedance circuit 525 may include transistors 525_1 and 525_2. The first terminal of the transistor 525_1 is coupled to the second terminal of the switch transistor 524. The second terminal of the transistor 525_1 is coupled to the control terminal of the transistor 525_1 and the first terminal of the transistor 525_2. The second terminal of the transistor 525_2 is coupled to the control terminal of the transistor 525_2 and the ground voltage GND. However, in some embodiments, the impedance circuit 525 may also be other types of impedance circuits, not limited to Figure 5 shown.

[0042] In the present embodiment, the impedance circuit 526 may include a transistor 526_1. A first terminal of the transistor 526_1 may receive a reference voltage V1, wherein the reference voltage V1 is a high level voltage and may be, for example, a protection voltage Vp. A second terminal of the transistor 526_1 is coupled to a control terminal of the transistor 526_1 and a circuit node N52. However, in some embodiments, the impedance circuit 526 may also be other types of impedance circuits, not limited to Figure 5 shown.

[0043] In this embodiment, the logic circuit 521 includes a circuit connection transistor 521_1, a switching circuit 521_2, a circuit switch transistor 521_3, and an impedance circuit 521_4. The circuit connection transistor 521_1 is coupled between the circuit node N51 and the reference voltage V1. The first end of the circuit connection transistor 521_1 can receive the reference voltage V1. The second end of the circuit connection transistor 521_1 is coupled to the first end of the switch transistor 524. The switch circuit 521_2 is coupled to the control end of the circuit connection transistor 521_1. The circuit switch transistor 521_3 is coupled to the reference voltage V1. The first end of the circuit switch transistor 521_3 can receive the reference voltage V1. The control end of the circuit switch transistor 521_3 can receive the control signal EM. The second end of the circuit switch transistor 521_3 is coupled to the switching circuit 521_2. The switch circuit 521_2 includes a scan transistor 521_21 and a reset transistor 521_22. The first end of the scan transistor 521_1 and the reset transistor 521_22 are coupled to the second end of the circuit switch transistor 521_3. The control end of the scan transistor 521_21 can receive the scan signal Sn. The control end of the reset transistor 521_22 can receive the reset signal RST. The second ends of the scan transistor 521_21 and the reset transistor 521_22 are coupled to the impedance circuit 521_4. The impedance circuit 521_4 may include a transistor 521_41. The first end of the transistor 521_41 is coupled to the control end of the transistor 521_41, the control end of the circuit connection transistor 521_1, and the second ends of the scan transistor 521_21 and the reset transistor 521_22. The second end of the transistor 521_41 is coupled to the ground voltage GND. However, in some embodiments, the impedance circuit 521_4 may also be other types of impedance circuits, not limited to Figure 5 shown.

[0044] In this embodiment, the circuit connecting transistor 521_1, the connecting transistors 523_1 to 523_3, the scanning transistor 521_21, the reset transistor 521_22, the circuit switching transistor 521_3, the switching transistor 522, the switching transistor 524, and the transistors 521_41, 525_1, 525_2, and 526_1 may be P-type thin film transistors or P-type metal oxide semiconductor field effect transistors, respectively, but the present disclosure is not limited thereto.

[0045] Also refer to Figure 4 as well as Figure 5 , Figure 4 The signal timing can also be applied to Figure 5The electronic device 500. In some embodiments of the present disclosure, each of the pixel circuits 510_1 to 510_3 can receive a control signal EM, a reset signal RST, and a scan signal Sn, respectively, so that the operation can be in a setting mode during a setting period P1 between time t0 and time t5 according to the control signal EM, the reset signal RST, and the scan signal Sn, and can be in a driving mode during a driving period P2 between time t5 and time t6. With reference to the following Table 2, during the setting period P1, the control signal EM is a high level voltage to turn off the circuit switch transistor 521_3, the switch transistor 522, the switch transistor 524, and the pixel switch transistors of the pixel circuits 510_1 to 510_3, respectively.

[0046] During the reset period PR from time t1 to time t2, the reset signal RST switches from a high level voltage to a low level voltage to turn on the reset transistors of the pixel circuits 510_1 to 510_3, respectively, and reset the storage capacitors of the pixel circuits 510_1 to 510_3, respectively. During the period PS from time t3 to time t4, the scan signal Sn switches from a high level voltage to a low level voltage to turn on the scan transistors of the pixel circuits 510_1 to 510_3, respectively, and writes the drive data to the storage capacitors of the pixel circuits 510_1 to 510_3, respectively. As shown in the operation states 1 to 3 of Table 2 below, the circuit nodes N51 and N52 maintain a high level voltage to turn off the connection transistors 523_1 to 523_3.

[0047] In the driving period P2 between time t5 and time t6, the control signal EM is a low level voltage to turn on the circuit switch transistor 521_3, the switch transistor 522, the switch transistor 524 and the pixel switch transistors of the pixel circuits 510_1 to 510_3 respectively. The reset signal RST and the scan signal Sn are high level voltages to turn off the reset transistor and the scan transistor of the pixel circuits 510_1 to 510_3 respectively. As shown in the operation state 4 of Table 2 below, the circuit nodes N51 and N52 are high level voltages to turn off the connection transistors 523_1 to 523_3. It is worth noting that since the scan transistor 521_21 and the reset transistor 521_22 of the switching circuit 521_2 can also receive the reset signal RST and the scan signal Sn, when at least one of the reset signal RST and the scan signal Sn has a signal (voltage) abnormality (false trigger), for example, when the voltage of at least one of the reset signal RST and the scan signal Sn is converted from a high level voltage to a low level voltage during the driving period P2, at least one of the scan transistor 521_21 and the reset transistor 521_22 is turned on, so that the circuit connection transistor 521_1 is turned on. As shown in the operation states 5 to 7 of the following Table 2, when at least one of the reset signal RST and the scan signal Sn has a signal (voltage) abnormality, the circuit nodes N51 and N52 are respectively switched to a low level voltage to turn on the connection transistors 523_1 to 523_3. In this regard, the circuit connection transistor 521_1 can provide the reference voltage V1 to the control end of the connection transistors 523_1 to 523_3 through the switch transistors 522, 524 and the circuit nodes N51, N52 to turn on the connection transistors 523_1 to 523_3. Then, the connection transistors 523_1 to 523_3 can respectively provide the protection voltage Vp to the driving transistors of the pixel circuits 510_1 to 510_3 to turn off the driving transistors. Therefore, the protection circuit 520 can effectively protect the diode elements in the pixel circuits 510_1 to 510_3 of the pixel 510, and can prevent the diode elements in the pixel circuits 510_1 to 510_3 from being damaged when at least one of the reset signal RST and the scan signal Sn has an abnormal voltage signal, thereby realizing the current overload protection function of the pixel 510.

[0048]

[0049] Table 2

[0050] In addition, in some embodiments, the switching circuit 521_2 may also include only one of the scanning transistor 521_21 and the reset transistor 521_22, and when a signal (voltage) abnormality occurs in one of the scanning signal Sn and the reset signal RST, the protection circuit 520 can turn on the connecting transistors 523_1~523_3 to turn off the driving transistors of the pixel circuits 510_1~510_3 respectively, thereby realizing the current overload protection function of the pixel 510.

[0051] Figure 6 is a circuit diagram of an electronic device according to a third embodiment of the present disclosure. Figure 6 , the electronic device 600 may include a pixel 610 and a protection circuit 620. The pixel 610 may include a plurality of pixel circuits 610_1 to 610_3, and each of the pixel circuits 610_1 to 610_3 may respectively implement the above-mentioned Figure 1 1 , but the number of pixel circuits in the pixel 610 disclosed herein is not limited thereto. In some embodiments, the pixel 610 may include one or more pixel circuits. In this embodiment, the pixel circuits 610_1 to 610_3 may be pixel circuits corresponding to a red sub-pixel, a green sub-pixel, or a blue sub-pixel, for example.

[0052] In this embodiment, the protection circuit 620 includes a logic circuit 621, a switch transistor 622, connection transistors 623_1-623_3, and impedance circuits 625 and 626, wherein the connection transistors 623_1-623_3 can be respectively coupled to the driving transistors (eg Figure 1 The logic circuit 621 is coupled to the first end of the switch transistor 622 and the impedance circuit 625 through the circuit node N61. The second end of the switch transistor 622 is coupled to the control end of the transistors 623_1 to 623_3 and the impedance circuit 626 through the circuit node N62. The control end of the switch transistor 622 can receive the control signal EM. The first end of the transistors 623_1 to 623_3 can receive the protection voltage Vp, where the protection voltage Vp can be Figure 1 The operating voltage VDD is shown, but the disclosure is not limited thereto. The second terminals of the connecting transistors 623_1 - 623_3 are respectively coupled to the pixel circuits 610_1 - 610_3 .

[0053] In the present embodiment, the impedance circuit 625 may include transistors 625_1 and 625_2. The first terminal of the transistor 625_1 is coupled to the circuit node N61. The second terminal of the transistor 625_1 is coupled to the control terminal of the transistor 625_1 and the first terminal of the transistor 625_2. The second terminal of the transistor 625_2 is coupled to the control terminal of the transistor 625_2 and the ground voltage GND. However, in some embodiments, the impedance circuit 625 may also be other types of impedance circuits, not limited to Figure 6 shown.

[0054] In the present embodiment, the impedance circuit 626 may include a transistor 626_1. A first terminal of the transistor 626_1 may receive a reference voltage V1, wherein the reference voltage V1 is a high level voltage and may be, for example, a protection voltage Vp. A second terminal of the transistor 626_1 is coupled to a control terminal of the transistor 626_1 and a circuit node N62. However, in some embodiments, the impedance circuit 626 may also be other types of impedance circuits, not limited to Figure 6 shown.

[0055] In this embodiment, the logic circuit 621 includes a circuit connection transistor 621_1, a switching circuit 621_2, a circuit switch transistor 621_3, and an impedance circuit 621_4. The circuit connection transistor 621_1 is coupled between the circuit node N61 and the reference voltage V1. The first end of the circuit connection transistor 621_1 can receive the reference voltage V1. The second end of the circuit connection transistor 621_1 is coupled to the first end of the switch transistor 622. The switch circuit 621_2 is coupled to the control end of the circuit connection transistor 621_1. The circuit switch transistor 621_3 is coupled to the reference voltage V1. The first end of the circuit switch transistor 621_3 can receive the reference voltage V1. The control end of the circuit switch transistor 621_3 can receive the control signal EM. The second end of the circuit switch transistor 621_3 is coupled to the switching circuit 621_2. The switch circuit 621_2 includes a scan transistor 621_21 and a reset transistor 621_22. The first end of the scan transistor 621_1 and the reset transistor 621_22 are coupled to the second end of the circuit switch transistor 621_3. The control end of the scan transistor 621_21 can receive the scan signal Sn. The control end of the reset transistor 621_22 can receive the reset signal RST. The second ends of the scan transistor 621_21 and the reset transistor 621_22 are coupled to the impedance circuit 621_4. The impedance circuit 621_4 may include a transistor 621_41. The first end of the transistor 621_41 is coupled to the control end of the transistor 621_41, the control end of the circuit connection transistor 621_1, and the second ends of the scan transistor 621_21 and the reset transistor 621_22. The second end of the transistor 621_41 is coupled to the ground voltage GND. However, in some embodiments, the impedance circuit 621_4 may also be other types of impedance circuits, not limited to Figure 6 shown.

[0056] In this embodiment, the circuit connecting transistor 621_1, the connecting transistors 623_1 to 623_3, the scanning transistor 621_21, the reset transistor 621_22, the circuit switching transistor 621_3, the switching transistor 622, and the transistors 621_41, 625_1, 625_2, and 626_1 may be P-type thin film transistors or P-type metal oxide semiconductor field effect transistors, respectively, but the present disclosure is not limited thereto.

[0057] Also refer to Figure 4 as well as Figure 6 , Figure 4 The signal timing can also be applied to Figure 6The electronic device 600. In some embodiments of the present disclosure, each of the pixel circuits 610_1 to 610_3 can receive a control signal EM, a reset signal RST, and a scan signal Sn, respectively, so that the operation can be in a setting mode during a setting period P1 between time t0 and time t5 according to the control signal EM, the reset signal RST, and the scan signal Sn, and can be in a driving mode during a driving period P2 between time t5 and time t6. With reference to the following Table 3, during the setting period P1, the control signal EM is a high level voltage to turn off the circuit switch transistor 621_3, the switch transistor 622, and the pixel switch transistors of the pixel circuits 610_1 to 610_3, respectively.

[0058] During the reset period PR from time t1 to time t2, the reset signal RST is switched from a high level voltage to a low level voltage to turn on the reset transistors of the pixel circuits 610_1 to 610_3, respectively, and reset the storage capacitors of the pixel circuits 610_1 to 610_3, respectively. During the period PS from time t3 to time t4, the scan signal Sn is switched from a high level voltage to a low level voltage to turn on the scan transistors of the pixel circuits 610_1 to 610_3, respectively, and write the drive data to the storage capacitors of the pixel circuits 610_1 to 610_3, respectively. As shown in the operation states 1 to 3 of Table 2 below, the circuit node N61 maintains a low level voltage, and the circuit node N62 maintains a high level voltage to turn off the connection transistors 623_1 to 623_3.

[0059] In the driving period P2 between time t5 and time t6, the control signal EM is a low level voltage to turn on the circuit switch transistor 621_3, the switch transistor 622, and the pixel switch transistors of the pixel circuits 610_1 to 610_3, respectively. The reset signal RST and the scan signal Sn are high level voltages to turn off the reset transistor and the scan transistor of the pixel circuits 610_1 to 610_3, respectively. As shown in the operation state 4 of Table 3 below, the circuit nodes N61 and N62 are high level voltages to turn off the connection transistors 623_1 to 623_3. It is worth noting that since the scan transistor 621_21 and the reset transistor 621_22 of the switching circuit 621_2 can also receive the reset signal RST and the scan signal Sn, when at least one of the reset signal RST and the scan signal Sn has a signal (voltage) abnormality (false trigger), for example, when the voltage of at least one of the reset signal RST and the scan signal Sn is converted from a high level voltage to a low level voltage during the driving period P2, at least one of the scan transistor 621_21 and the reset transistor 621_22 is turned on, so that the circuit connection transistor 621_1 is turned on. As shown in the operation states 5 to 7 of the following Table 3, when at least one of the reset signal RST and the scan signal Sn has a signal (voltage) abnormality, the circuit nodes N61 and N62 are respectively switched to a low level voltage to turn on the connection transistors 623_1 to 623_3. In this regard, the circuit connection transistor 621_1 can provide the reference voltage V1 to the control end of the connection transistors 623_1 to 623_3 through the switch transistor 622 and the circuit nodes N61 and N62 to turn on the connection transistors 623_1 to 623_3. Then, the connection transistors 623_1 to 623_3 can respectively provide the protection voltage Vp to the driving transistors of the pixel circuits 610_1 to 610_3 to turn off the driving transistors. Therefore, the protection circuit 620 can effectively protect the diode elements in the pixel circuits 610_1 to 610_3 of the pixel 610, and can prevent the diode elements in the pixel circuits 610_1 to 610_3 from being damaged when at least one of the reset signal RST and the scan signal Sn has an abnormal voltage signal, thereby realizing the current overload protection function of the pixel 610.

[0060]

[0061] Table 3

[0062] In addition, in some embodiments, the switching circuit 621_2 may also include only one of the scanning transistor 621_21 and the reset transistor 621_22, and when a signal (voltage) abnormality occurs in one of the scanning signal Sn and the reset signal RST, the protection circuit 620 can turn on the connecting transistors 623_1~623_3 to turn off the driving transistors of the pixel circuits 610_1~610_3 respectively, thereby realizing the current overload protection function of the pixel 610.

[0063] In summary, the electronic device disclosed herein can self-detect one of the scanning signal and the reset signal of the pixel by coupling the protection circuit of the pixel. When one of the scanning signal and the reset signal of the pixel is abnormal or malfunctions, the protection circuit can turn off the abnormal pixel, thereby reducing problems such as damage to the diode element in the pixel caused by short circuit or high current.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An electronic device, characterized in that: include: a pixel circuit including a drive transistor; as well as Protection circuits, including: A first connecting transistor coupled to the driving transistor; A first switch transistor coupled to the first connection transistor; and a logic circuit coupled to the first terminal of the first switch transistor, The second end of the first switch transistor is coupled to the control end of the first connection transistor, the first end of the first connection transistor receives a protection voltage, and the second end of the first connection transistor is coupled to the driving transistor. The logic circuit receives at least one of a scan signal and a reset signal.

2. The electronic device according to claim 1, characterized in that: The pixel circuit further comprises: A pixel switch transistor coupled to the driving transistor and receiving a control signal; and A diode element coupled to the pixel switch transistor, The first switch transistor receives the control signal.

3. The electronic device according to claim 1, characterized in that: The pixel circuit further comprises: a first scanning transistor coupled to the driving transistor and receiving the scanning signal, The logic circuit receives the scanning signal.

4. The electronic device according to claim 1, characterized in that: The pixel circuit further comprises: a first reset transistor, coupled to the driving transistor and receiving the reset signal, The logic circuit receives the reset signal.

5. The electronic device according to claim 1, characterized in that: The logic circuit comprises: A second connecting transistor coupled between the first switch transistor and a first reference voltage; and The switching circuit is coupled to the second connection transistor and receives at least one of the scan signal and the reset signal.

6. The electronic device according to claim 5, characterized in that: The logic circuit further comprises: a second switch transistor, coupled to the first reference voltage, The switching circuit is coupled between the second switch transistor and the second connection transistor.

7. The electronic device according to claim 6, characterized in that: The switching circuit includes at least one of a second scan transistor and a second reset transistor to receive at least one of the scan signal and the reset signal, and determines whether to provide the first reference voltage to the second connection transistor according to at least one of the scan signal and the reset signal.

8. The electronic device according to claim 5, characterized in that: The protection circuit further comprises: The impedance circuit is coupled to a circuit node between the first switch transistor and the second connection transistor.

9. The electronic device according to claim 8, characterized in that: The protection circuit further comprises: The third switch transistor is coupled between the circuit node and the impedance circuit.

10. The electronic device according to claim 8, characterized in that: The protection circuit further comprises: The third switch transistor is coupled between the circuit node and the second connection transistor.

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