Semiconductor structures for wafer level bonding and bonded semiconductor structures

Abstract

A semiconductor structure for wafer level bonding and a bonded semiconductor structure are disclosed. The semiconductor structure for wafer level bonding includes a bonding dielectric layer disposed on a substrate and a bonding pad disposed in the bonding dielectric layer. The bonding pad includes a top surface, a bottom surface exposed from the bonding dielectric layer and opposite the top surface, and a sidewall between the top surface and the bottom surface, wherein a bottom angle between the sidewall and the bottom surface is less than 90 degrees.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to semiconductor structures for wafer-level bonding and bonding semiconductor structures. Background Technology

[0002] 3D ICs refer to the transformation of traditional two-dimensional chips into three-dimensional stacked chips using wafer-level bonding and through-silicon via (TSV) technologies. Because 3D ICs can effectively utilize space, shorten circuit transmission distances, and provide extremely low-resistance connections, they have gradually become the mainstream technology for components such as power converters, low-noise amplifiers, and radio frequency (RF) or millimeter-wave (MMW) circuits. However, current 3D ICs still have issues that need improvement, such as poor bonding quality between bonding pads leading to abnormal signal transmission. Summary of the Invention

[0003] The present invention aims to provide a semiconductor structure for wafer-level bonding and a bonding semiconductor structure, which includes trapezoidal bonding pads to ensure close contact between two aligned bonding pads and reduce stress on the bonding surface, thereby achieving improved bonding quality.

[0004] One embodiment of the present invention provides a semiconductor structure for wafer-level bonding, including a bonding dielectric layer disposed on a substrate and a bonding pad disposed in the bonding dielectric layer. The bonding pad includes a top surface exposed from the bonding dielectric layer, a bottom surface relative to the top surface, and a sidewall located between the top surface and the bottom surface, wherein a bottom angle between the sidewall and the bottom surface is less than 90 degrees.

[0005] Another embodiment of the present invention provides a bonding semiconductor structure, including a first element wafer and a second element wafer. The first element wafer includes a first substrate, a first bonding dielectric layer disposed on the first substrate, and a first bonding pad disposed in the first bonding dielectric layer, wherein a first apex angle between a first top surface and a first sidewall of the first bonding pad is greater than 90 degrees. The second element wafer includes a second substrate, a second bonding dielectric layer disposed on the second substrate and bonded to the first bonding dielectric layer, and a second bonding pad disposed in the second bonding dielectric layer, wherein a second top surface of the second bonding pad is bonded to the first top surface of the first bonding pad. Attached Figure Description

[0006] Figures 1 to 5 This is a cross-sectional schematic diagram of the steps in the method for fabricating a semiconductor structure according to the first embodiment of the present invention;

[0007] Figure 6This is a cross-sectional schematic diagram of the bonding semiconductor structure according to the second embodiment of the present invention;

[0008] Figure 7 This is a schematic cross-sectional view of the bonding semiconductor structure according to the third embodiment of the present invention;

[0009] Figure 8 This is a cross-sectional schematic diagram of the bonding semiconductor structure according to the fourth embodiment of the present invention;

[0010] Figure 9 This is a cross-sectional schematic diagram of the bonding semiconductor structure according to the fifth embodiment of the present invention;

[0011] Figure 10 This is a cross-sectional schematic diagram of the bonding semiconductor structure according to the sixth embodiment of the present invention.

[0012] Explanation of main component symbols

[0013] 100 First Component Wafer

[0014] 102 base

[0015] 104 Semiconductor Components

[0016] 110 Interconnection Layer

[0017] 112 Dielectric layer

[0018] 112a surface

[0019] 114 Interconnection Structure

[0020] 116 Etching Stop Layer

[0021] 120 bonding dielectric layer

[0022] 122 Opening

[0023] 130 Joint Pad

[0024] 130a Bottom

[0025] 130b Top surface

[0026] 130c sidewall

[0027] 130d top surface

[0028] 140 silicon nitride layer

[0029] 120' silicon oxide layer

[0030] 200 Second Component Wafer

[0031] 202 base

[0032] 204 Semiconductor Components

[0033] 210 Interconnection Layer

[0034] 212 Dielectric Layer

[0035] 214 Interconnection Structure

[0036] 216 Etching Stop Layer

[0037] 220 bonding dielectric layer

[0038] 230 Joint Pad

[0039] 230a Bottom

[0040] 230b Top surface

[0041] 230c sidewall

[0042] 230d top surface

[0043] 240 silicon nitride layer

[0044] 220' silicon oxide layer

[0045] A0 bottom corner

[0046] A1 Bottom Corner

[0047] A2 Vertex

[0048] B2 apex

[0049] B3 apex

[0050] B4 apex

[0051] BS1 contact surface

[0052] BS2 mating surface

[0053] P1 Alignment Manufacturing Process

[0054] P2 Tempering process

[0055] SP gap

[0056] W1 width

[0057] W2 width

[0058] W3 width

[0059] W4 width Detailed Implementation

[0060] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described below in conjunction with the accompanying drawings. The accompanying drawings are schematic diagrams and not drawn to scale, and the same or similar features are generally described using the same reference numerals. The embodiments and drawings described herein are for reference and illustration only and are not intended to limit the present invention. The scope of the present invention is defined by the claims. Anything with the same meaning as the claims of the present invention should also be included within the scope of the present invention.

[0061] The meanings of "on," "above," and "above" in this text should be interpreted in the broadest sense, such that "on" is not limited to referring to "directly on" something, but can also include "on" something with intermediate features or layers. Similarly, "above" or "above" is not limited to referring to "above" or "above" something, but can also include "directly above" or "directly above" something without intermediate features or layers.

[0062] For ease of description, spatial relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship between one device or feature and another (or more) devices or features as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the element in use or operation. The element may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially related descriptive terms used herein may be interpreted accordingly.

[0063] As used herein, the term "substrate" refers to the material on which components are fabricated and / or on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0064] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire underlying or overlying structure, or may have a range smaller than that of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located in a region between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend laterally, vertically, and / or along a tapered surface. A substrate may be a layer, and a substrate may include one or more layers, and / or may have one or more layers on, above, and / or below it. The term "layer" as used herein may include one or more layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0065] Please refer to Figures 1 to 5 The diagram shown is a cross-sectional schematic diagram of the steps in a method for fabricating a semiconductor structure for wafer-level bonding according to a first embodiment of the present invention. Figure 1 As shown, a first element wafer 100 is first provided, which includes a substrate 102, an interconnect layer 110 disposed on the substrate 102, and a bonding dielectric layer 120 disposed on the interconnect layer 110. The substrate 102 is, for example, a silicon substrate, a silicon-on-insulator (SOI) substrate, a silicon-germanium substrate, a group III-V semiconductor substrate, or a substrate made of other suitable materials. Semiconductor elements 104, such as transistors, diodes, capacitors, inductors, resistors, and other active or passive elements, may be formed in the substrate 102, but are not limited thereto. The interconnect layer 110 may include a dielectric layer 112 and interconnect structures 114 formed in the dielectric layer 112. The dielectric layer 112 may include a multilayer structure, and the material may include silicon oxide, silicon nitride, carbon-doped silicon nitride, or a low-k dielectric material, but is not limited thereto. The interconnect structure 114 may include conductive materials, such as copper, aluminum, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, and other metallic materials or metal compounds, but is not limited thereto. Semiconductor element 104 can be electrically connected to interconnect structure 114, and then electrically connected to external circuit elements (not shown) through interconnect structure 114. Interconnect layer 110 may also include other circuit elements, such as capacitors, inductors, resistors, embedded memory, etc., which are not shown for simplicity. Bonding dielectric layer 120 may include a dielectric material, such as silicon oxide, silicon nitride, or other dielectric materials suitable for wafer-level bonding. According to one embodiment of the invention, the material of bonding dielectric layer 120 may include silicon oxide. Interconnect layer 110 may include an etch stop layer 116 between dielectric layer 112 and bonding dielectric layer 120. According to one embodiment of the invention, the material of etch stop layer 116 may include silicon nitride.

[0066] like Figure 2As shown, a patterning process is then performed to form an opening 122 that passes through the etch stop layer 116 of the bonding dielectric layer 120 and the interconnect layer 110 and exposes the surface 112a of the dielectric layer 112. According to an embodiment of the present invention, the patterning process is, for example, a photolithography and etching process. The steps may include first forming a photoresist layer (not shown) on the bonding dielectric layer 120, then etching the bonding dielectric layer 120 using the photoresist layer as an etch mask until the etch stop layer 116 is exposed, and then over-etching is performed to etch through the etch stop layer 116 to expose the surface 112a of the dielectric layer 112, thereby transferring the pattern of the photoresist layer to the bonding dielectric layer 120 and the etch stop layer 116, forming the opening 122. The lateral etch rate can be adjusted by adjusting the fabrication process parameters in the above etching step so that the bottom angle A0 between the sidewall 122a of the opening 122 and the surface 112a of the dielectric layer 112 is less than 90 degrees. According to one embodiment of the present invention, the angle of the base angle 122a may be between 60 degrees and 85 degrees.

[0067] like Figure 3 As shown, a conductive material layer (not shown) is then formed on the dielectric layer 120 and filled into the opening 122. A chemical mechanical polishing (CMP) process is then performed to remove the conductive material layer outside the opening 122 until the surface of the bonding dielectric layer 120 is exposed, thereby obtaining the bonding pad 130 located within the opening 122. The material of the conductive material layer (i.e., the material of the bonding pad 130) may include a metallic material suitable for wafer-level bonding, such as copper (Cu). In some embodiments, the CMP process may include overpolishing to ensure that the conductive material layer on the surface of the bonding dielectric layer 120 is completely removed, such that the top surface 130b of the bonding pad 130 after the CMP process may have a recessed profile lower than the surface of the bonding dielectric layer 120. Figure 3 As shown, the edge of the top surface 130b may be slightly lower than the surface of the bonding dielectric layer 120 to expose the sidewall of the upper part of the opening 122, or in other embodiments the edge of the top surface 130b may be substantially flush with the surface of the bonding dielectric layer 120.

[0068] Please continue to refer to this. Figure 3A semiconductor structure (i.e., a first element wafer 100) for wafer-level bonding according to an embodiment of the present invention includes a substrate 102, on which an interconnect layer 110 and a bonding dielectric layer 120 are disposed. The substrate 102 may include semiconductor elements 104, which are electrically connected to each other and / or to external circuit elements (not shown) via interconnect structures 114 disposed within the interconnect layer 110. Bonding pads 130 are disposed in the bonding dielectric layer 120, including a bottom surface 130a, a top surface 130b opposite to the bottom surface 130a, and a sidewall 130c located between the bottom surface 130a and the top surface 130b. The top surface 130b is exposed from the surface of the bonding dielectric layer 120 for bonding with another element wafer (e.g., a first element wafer 100). Figure 4 and Figure 5 The second component wafer 200 shown is bonded at the wafer level using bonding pads. Bonding pad 130 extends through the bonding dielectric layer 120 and the etch stop layer 116 of the interconnect layer 110, with its bottom surface 130a contacting the dielectric layer 112 of the interconnect layer 110. In some embodiments, the bottom surface 130a of the bonding pad 130 may be electrically connected to an interconnect structure (not shown) in the interconnect layer 110 to transmit signals between the first component wafer 100 and another bonded wafer. In some embodiments, the bonding pad 130 may be a dummy bonding pad without signal transmission function, with its bottom surface 130a not contacting any interconnect structure (not shown). Dummy bonding pads can provide heat dissipation, electronic shielding, and / or enhance wafer-to-wafer bonding. It is worth noting that, from the cross-sectional view, the mating pad 130 may have a trapezoidal cross-sectional shape, with a width W1 of the bottom surface 130a greater than a width W2 of the top surface 130b, and a base angle A1 of less than 90 degrees between the sidewall 130c and the bottom surface 130a. According to one embodiment of the present invention, the width W1 may be between 1.1 and 1.3 times the width W2, and the base angle A1 may be between 60 and 85 degrees, but is not limited thereto.

[0069] like Figure 4 As shown, a second component wafer 200 can then be provided, followed by an alignment fabrication process P1. The second component wafer 200 is positioned on the first component wafer 100 with its bonding dielectric layer 220 facing the bonding dielectric layer 120 of the first component wafer 100 and its bonding pads 230 aligned with a corresponding bonding pad 130 of the first component wafer 100, and in contact with the first component wafer 100 at contact surface BS1. Before performing the alignment fabrication process P1, a surface cleaning step may be included for the bonding dielectric layer 120 of the first component wafer 100 and the bonding dielectric layer 220 of the second component wafer 200.

[0070] In detail, the second element wafer 200 may include a substrate 202, an interconnect layer 210 disposed on the substrate 202, and a bonding dielectric layer 220 disposed on the interconnect layer 210. The substrate 202 may be, for example, a silicon substrate, a silicon-on-insulator (SOI) substrate, a silicon-germanium substrate, a group III-V semiconductor substrate, or a substrate made of other suitable materials. Semiconductor elements 204, such as transistors, diodes, capacitors, inductors, resistors, and other active or passive elements, may be formed within the substrate 202, but are not limited to these. The interconnect layer 210 may include a dielectric layer 212 and interconnect structures 214 formed in the dielectric layer 212. The dielectric layer 212 may include a multilayer structure, and the material may include silicon oxide, silicon nitride, carbon-doped silicon nitride, or a low-k dielectric material, but is not limited to these. The interconnect structure 214 may include conductive materials, such as copper, aluminum, tungsten, titanium, titanium nitride, tantalum, or tantalum nitride and other metallic materials or metal compounds. Semiconductor element 204 can be electrically connected to interconnect structure 214, and then electrically connected to external circuit elements (not shown) through interconnect structure 214. Interconnect layer 210 may also include circuit elements such as capacitors, inductors, resistors, embedded memory, etc., which are not shown for simplicity. Bonding dielectric layer 220 may include a dielectric material, such as silicon oxide, silicon nitride, or other dielectric materials suitable for wafer-level bonding. According to one embodiment of the invention, the material of bonding dielectric layer 220 includes silicon oxide. Interconnect layer 210 may include an etch stop layer 216 between dielectric layer 212 and bonding dielectric layer 220. According to one embodiment of the invention, the material of etch stop layer 216 includes silicon nitride. Bonding pads 230 of second element wafer 200 are disposed in bonding dielectric layer 220 and may have a trapezoidal cross-sectional shape. Bonding pads 230 include a metallic material suitable for bonding with bonding pads 130, for example, copper (Cu). In some embodiments, the top surface 230b of the bonding pad 230 may also have a recessed profile, forming a gap SP between it and the top surface 230a of the bonding pad 130.

[0071] like Figure 5 As shown, a tempering process P2 is then performed to promote material diffusion and bonding between the bonding dielectric layer 120 and the bonding dielectric layer 220. During tempering process P2, the metal material (e.g., copper) of the bonding pads 130 and 230 expands due to heat, filling the gap SP, causing them to contact each other and form a metallic bond. This invention transforms the contact surface BS1 into the bonding surface BS2 through tempering process P2, simultaneously bringing the bonding pads 130 and 230 closer together and forming a metallic bond, thereby obtaining a first element wafer 100 and a second element wafer 200 with hybrid bonding. According to one embodiment of the invention, the temperature of tempering process P2 can be between 40°C and 400°C, for example, between 250°C and 350°C, but is not limited thereto.

[0072] Please continue to refer to this. Figure 5 According to an embodiment of the present invention, a bonding semiconductor structure includes a first element wafer 100 and a second element wafer 200. The first element wafer 100 includes a substrate 102, a bonding dielectric layer 120 disposed on the substrate 102, and a bonding pad 130 disposed in the bonding dielectric layer 120. The second element wafer 200 includes a substrate 202, a bonding dielectric layer 220 disposed on the substrate 202, and a bonding pad 230 disposed in the bonding dielectric layer 220, wherein the second element wafer 200 is disposed on the first element wafer 100 such that the bonding dielectric layer 220 and the bonding dielectric layer 120 are bonded at a bonding surface BS2, and the top surface 230d of the bonding pad 230 is bonded to the top surface 130d of the bonding pad 130. The mating pad 130 also includes a bottom surface 130a relative to the top surface 130d and a sidewall 130c located between the top surface 130d and the bottom surface 130a, wherein a width W1 of the bottom surface 130a is greater than a width W2 of the top surface 130b, for example, W1 may be between 1.1 and 1.3 times W2, and the top surface 130d and the sidewall 130c include a apex angle A2 greater than 90 degrees, for example, between 105 degrees and 120 degrees. Similarly, the bonding pad 230 also includes a bottom surface 230a relative to the top surface 230d and a sidewall 230c located between the top surface 230d and the bottom surface 230a, wherein a width W3 of the bottom surface 230a is greater than a width W4 of the top surface 230b, for example, W3 may be between 1.1 and 1.3 times W4, and a apex angle B2 greater than 90 degrees is included between the top surface 230d and the sidewall 230c, for example, between 105 degrees and 120 degrees. In this embodiment, bonding pads 130 and 230 respectively have a trapezoidal cross-sectional shape, which helps to ensure that the metal material of bonding pads 130 and 230 can completely fill the gap SP after thermal expansion, thereby obtaining a tight contact and better bonding quality. In addition, the trapezoidal cross-sectional shape of bonding pads 130 and 230 of the present invention can reduce the stress acting on the bonding surface BS2 due to thermal expansion during the tempering process P2, which also helps to improve the bonding quality.

[0073] The following description will focus on different embodiments of the present invention. For simplicity, the description will primarily focus on the differences between the embodiments, without repeating the similarities. Identical elements in each embodiment are designated with the same reference numerals to facilitate comparison between embodiments.

[0074] Please refer to Figure 6The diagram shown is a cross-sectional schematic of a bonding semiconductor structure according to a second embodiment of the present invention, including a first element wafer 100 and a second element wafer 200. In this embodiment, the width of the top surface 230d of the bonding pad 230 of the second element wafer 200 is selected to be approximately equal to the width of the bottom surface 230a and greater than the width of the top surface 130d of the first element wafer 100. This ensures that there is still sufficient bonding area between the bonding pad 230 and the bonding pad 130 when alignment misalignment occurs during the alignment fabrication process P1. Therefore, in this embodiment, the apex angle B3 between the top surface 230d and the sidewall 230c of the bonding pad 230 can be approximately equal to 90 degrees, and the bonding pad 230 can have a rectangular cross-sectional shape.

[0075] Please refer to Figure 7 The diagram shown is a cross-sectional schematic of a bonding semiconductor structure according to a third embodiment of the present invention, including a first element wafer 100 and a second element wafer 200. In this embodiment, the width of the top surface 230d of the bonding pad 230 of the second element wafer 200 may be greater than the width of the bottom surface 230a and also greater than the width of the top surface 130d of the first element wafer 100. The apex angle B4 between the top surface 230d and the sidewall 230c of the bonding pad 230 may be less than 90 degrees, and the bonding pad 230 may have a trapezoidal cross-sectional shape.

[0076] Please refer to Figure 8 The diagram illustrates a cross-sectional view of a bonding semiconductor structure according to a fourth embodiment of the present invention, including bonding a first element wafer 100 and a second element wafer 200. In this embodiment, the bonding dielectric layer 120 of the first element wafer 100 may include a silicon oxide layer 120' and a silicon nitride layer 140, and the bonding dielectric layer 220 of the second element wafer 200 may include a silicon oxide layer 220' and a silicon nitride layer 240. The second element wafer 200 is disposed on the first element wafer 100 such that the silicon nitride layer 240 is bonded to the silicon nitride layer 140 at the bonding surface BS2, and the top surface 230d of the bonding pad 230 is bonded to the top surface 130d of the bonding pad 130. When alignment misalignment occurs during the alignment fabrication process P1, the silicon nitride layers 140 and 240 can prevent the metal of the bonding pad 230 and / or the bonding pad 130 from diffusing into the interconnect layer, thereby reducing the chance of defects.

[0077] Please refer to Figure 9 The diagram shown is a cross-sectional schematic of a bonding semiconductor structure according to a fifth embodiment of the present invention. In this embodiment, the bottom surface 130a of bonding pad 130 can contact and be electrically connected to the interconnect structure 114 in the interconnect layer 110, and the bottom surface 230a of bonding pad 230 can contact and be electrically connected to the interconnect structure 214 in the interconnect layer 210. When bonding pad 130 and bonding pad 230 are bonded to each other, signals can be transmitted between the first element wafer 100 and the second element wafer 200.

[0078] Please refer to Figure 10 The diagram shown is a cross-sectional schematic of a bonding semiconductor structure according to a sixth embodiment of the present invention. In this embodiment, the chemical mechanical polishing (CMP) processes used to fabricate bonding pads 130 and 230 can be adjusted to modify the concavity or convexity of the top surfaces of bonding pads 130 and 230, for example, making the top surface of bonding pad 130 more deeply concave to expose opening 122 (see reference). Figure 3 The upper sidewalls are designed to allow the top surface of the bonding pad 230 to be shallowly recessed, or to be approximately flush with or protrude from the surface of the bonding dielectric layer 220 (not shown). This design allows the bonding pad 230 to expand further towards the bonding pad 130 after the tempering process, filling the gaps created by the recess in the bonding dielectric layer 120. For example... Figure 10 As shown, the portion where the bonding pad 230 joins with the bonding pad 130 may include a slightly laterally flared apex 235, and the sidewall of the apex 235 is in direct contact with the bonding dielectric layer 120.

[0079] In summary, the semiconductor structure for wafer-level bonding provided by this invention has a trapezoidal bonding pad design that ensures that two corresponding bonding pads can be in close contact and bonded during wafer-level bonding, and also reduces the stress on the bonding surface, thereby achieving improved bonding quality.

[0080] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor structure for wafer-level bonding, comprising: A bonding dielectric layer is disposed on a substrate; as well as A bonding pad is disposed in the bonding dielectric layer, wherein the bonding pad comprises: The top surface is exposed from the bonding dielectric layer and includes a recessed profile; The bottom surface, relative to the top surface; as well as A sidewall located between the top surface and the bottom surface, wherein the bottom angle between the sidewall and the bottom surface is less than 90 degrees.

2. The semiconductor structure for wafer-level bonding as claimed in claim 1, wherein the bottom angle is between 60 degrees and 85 degrees.

3. The semiconductor structure for wafer-level bonding as claimed in claim 1, wherein the width of the bottom surface is greater than the width of the top surface.

4. The semiconductor structure for wafer-level bonding as claimed in claim 1, wherein the bonding pad is made of copper.

5. The semiconductor structure for wafer-level bonding as claimed in claim 1, wherein the material of the bonding dielectric layer comprises silicon oxide.

6. The semiconductor structure for wafer-level bonding as claimed in claim 1, wherein the bonding dielectric layer comprises a silicon oxide layer and a silicon nitride layer.

7. The semiconductor structure for wafer-level bonding as claimed in claim 1, wherein the substrate includes a plurality of semiconductor elements.

8. The semiconductor structure for wafer-level bonding as claimed in claim 1, further comprising an interconnect layer located between the substrate and the bonding dielectric layer.

9. A junction semiconductor structure, comprising: The first component chip includes: First base; A first bonding dielectric layer is disposed on the first substrate; as well as A first bonding pad is disposed in the first bonding dielectric layer, wherein the first apex angle between the first top surface and the first sidewall of the first bonding pad is greater than 90 degrees, and the first top surface includes a recessed profile. as well as The second component chip includes: Second basement; A second bonding dielectric layer is disposed on the second substrate and bonded to the first bonding dielectric layer; as well as A second bonding pad is disposed in the second bonding dielectric layer, wherein the second top surface of the second bonding pad includes a protruding profile and is bonded to the first top surface of the first bonding pad.

10. The junction semiconductor structure of claim 9, wherein the first vertex angle is between 105 degrees and 120 degrees.

11. The bonding semiconductor structure of claim 9, wherein the first bonding pad further includes a first bottom surface relative to the first top surface, the width of the first bottom surface being greater than the width of the first top surface.

12. The bonding semiconductor structure of claim 9, wherein the materials of the first bonding pad and the second bonding pad respectively comprise copper.

13. The bonding semiconductor structure of claim 9, wherein the materials of the first bonding dielectric layer and the second bonding dielectric layer respectively comprise silicon oxide.

14. The bonding semiconductor structure of claim 9, wherein the first bonding dielectric layer and the second bonding dielectric layer respectively comprise a silicon oxide layer and a silicon nitride layer.

15. The bonding semiconductor structure of claim 9, wherein the first substrate and the second substrate each comprise a plurality of semiconductor elements.

16. The junction semiconductor structure of claim 9, further comprising: A first interconnect layer is located between the first substrate and the first bonding dielectric layer; and The second interconnect layer is located between the second substrate and the second bonding dielectric layer.

17. The bonding semiconductor structure of claim 9, wherein the second apex angle between the first top surface of the second bonding pad and the second sidewall of the second bonding pad is greater than 90 degrees.

Images