Method and device for directional formation of palladium complex center by low temperature oxidation masking PN junction

Abstract

This invention discloses a method and device for the directional formation of palladium recombination centers in a PN junction using low-temperature oxidation masking, belonging to the field of semiconductor device manufacturing. This invention employs LTO (Low Temperature Oxidation) technology, using ultra-high purity oxygen to carry silane in a low-temperature environment within an LTO oxidation furnace to form a dense oxide film on the surface of a conventional PIN diode diffuser wafer with pre-formed trenches. Following photolithography and etching processes, precise directional palladium diffusion is performed. This results in a diffuser substrate with well-concentrated parameters such as Vf (forward voltage drop) and Trr (reverse recovery time), significantly improving chip utilization on the diffuser and substantially enhancing product quality. Compared to using expensive ion implanters, this invention significantly reduces costs while achieving parameter quality comparable to ion implantation.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor device manufacturing, and in particular relates to a method and a device for directional formation of palladium composite centers by low-temperature oxidation masking PN junctions. Background Art

[0002] As we all know, the most important characteristic of a diode is its unidirectional conductivity. In a circuit, current can only flow into the positive pole of a diode and out of the negative pole. There are many types of diodes, among which the fast recovery diode (collectively referred to as FRD) is a semiconductor diode with good switching characteristics and short reverse recovery time. This type of diode is mainly used in high-frequency electronic circuits such as switching power supplies or inverters. Its function is high-frequency rectification, or as a freewheeling diode or damping diode, and can replace Schottky diodes in some fields.

[0003] The internal structure of the fast recovery diode is a typical PIN junction diode, that is, a base region I is added between the P-type silicon material and the N-type silicon material to form a PIN silicon wafer. The fast recovery diode has a short reverse recovery time, a low forward voltage drop, and a high reverse breakdown voltage (withstand voltage value). However, unlike the Schottky diode, the PIN structure fast recovery diode needs to adopt the principle of gold doping to form a recombination center in the manufacturing process to reduce its reverse recovery time, that is, to obtain a higher switching speed.

[0004] Recombination centers refer to certain impurities and defects inside the semiconductor structure, which can promote carrier recombination and play a decisive role in the length of the non-equilibrium carrier lifetime. The impurities and defects that serve as recombination centers generally introduce one or several deep energy levels in the bandgap, which can capture both electrons and holes, thereby promoting the recombination process. Gold and platinum are the most common recombination centers in semiconductor silicon materials. The VF and Trr characteristics of the diodes obtained by gold doping are better than those of platinum doped diodes, but the high-temperature reverse leakage current characteristics are worse than those of platinum doping. If the impurity concentration can be better controlled, palladium can be used, which has a recombination effect between gold and platinum at the recombination center. Adding palladium to the rectifier diode of the ordinary PIN structure can accelerate the recombination of electrons and holes, and the palladium concentration near the PN junction will also directly determine the size of its reverse recovery time.

[0005] Generally speaking, PIN junction rectifier diodes with faster recovery time are collectively referred to as fast recovery diodes (FRD). According to the different recovery times, they can be divided into fast recovery diodes FR, high efficiency rectifier diodes HER, and ultra-fast recovery diodes SF.

[0006] According to the relationship between stored charge and forward voltage:

[0007]

[0008] The reverse recovery time is the time required for the stored charge to be exhausted, so it can be concluded that: Vf / ∝Trr, the forward voltage drop is inversely proportional to the reverse recovery time. As we all know, too high a forward voltage drop will lead to higher power loss in high-frequency circuits, so for fast recovery diode products, it is particularly important to accurately control the range of the reverse recovery time Trr.

[0009] Since the Vf parameter is inaccurate before the chip is packaged, we can only judge in advance whether the product Vf meets the requirements based on the Trr law summarized based on years of experience. The typical distribution of Trr is shown in Table 1 below:

[0010] Table 1: Common typical classification of fast recovery diodes FRD

[0011] model Voltage distribution Trr typical range Ultrafast recovery diode SF Full range 22~35ns High efficiency rectifier diode HER ＜1000V 30~48ns High efficiency rectifier diode HER ＞1000V 48~72ns Fast recovery diode FR ＜500V 75~150ns Fast recovery diode FR 500～1000V 90~250ns Fast recovery diode FR ＞1000V 180~450ns

[0012] From the above classification table, it can be seen that for diode chips with lower Trr, the standard deviation requirement is higher. In other words, the smaller the deviation of palladium impurity concentration inside each silicon wafer, the better.

[0013] The ion implanters used in the manufacture of integrated circuits are extremely expensive, the process is cumbersome, and the production efficiency is low, so they are not used in the diode manufacturing process. The current traditional process mode of diodes is diffusion: after the silicon wafer PN junction is diffused and formed, the source is directly coated and palladium impurities are diffused to introduce the recombination center into the PN junction. The traditional coating source is difficult to ensure the uniformity of the palladium impurity concentration on the surface of the wafer, which leads to the deviation of the final Trr of the product, especially for 5-inch or even 6-inch substrates, the concentration difference between the inner and outer circles can be as high as 50%.

[0014] Therefore, how to ensure the uniformity of palladium impurity concentration when forming recombination centers inside the diode diffuser is a technical problem that needs to be solved urgently. Summary of the invention

[0015] The purpose of the present invention is to solve the problem of uneven palladium impurity concentration when forming a recombination center inside a diode diffusion sheet in the prior art, and to provide a method for directional formation of palladium recombination centers by low-temperature oxidation masking PN junctions.

[0016] The specific technical solutions adopted by the present invention are as follows:

[0017] In a first aspect, the present invention provides a method for directional formation of palladium complex centers by low temperature oxidation masking PN junction, which comprises:

[0018] S1. Using a PIN diode diffusion wafer with a PN junction formed and grooved, firstly using pure oxygen to carry silane to form a first oxidation atmosphere and perform low-temperature oxidation at 500-800°C, then using pure oxygen to form a second oxidation atmosphere and continue to perform dry oxygen oxidation at 500-800°C, thereby forming an oxide film on the surface of the wafer;

[0019] S2, forming a patterned mask on a wafer with an oxide film by photolithography, so that an oxide layer etching window is exposed in the center of each chip table, but a mask surrounding the oxide layer etching window is still retained at the edge positions of the chip table and the grooves between the chip tables; then etching the oxide layer of the wafer to remove the oxide film within the range of each oxide layer etching window, and obtaining a source attachment window for attaching a palladium source;

[0020] S3. Applying the palladium source to the surface of the wafer, and then directional diffusion of palladium is performed through sintering, so that the palladium impurities diffuse into the interior of the wafer to form a recombination center.

[0021] As a preferred embodiment of the first aspect mentioned above, the processing method of the PIN diode diffusion sheet wafer with a PN junction formed and etching and grooving completed is: diffusing impurities on a silicon wafer to form a wafer with a rectifier diode PIN structure, and then subjecting the wafer to photolithography and etching and grooving to obtain a wafer with a chip graphic structure.

[0022] As a preferred embodiment of the first aspect, the first oxidizing atmosphere is obtained by mixing high-purity oxygen and silane in a gas flow ratio of (1-3):1 and continuously passing the mixture into a low-temperature oxidizing environment.

[0023] As a preferred embodiment of the first aspect, in the process of forming an oxide film on the surface of the wafer, the thickness of the oxide film formed by low temperature oxidation in the first oxidizing atmosphere is Above, preferably The above, more preferably Preferably, the thickness of the oxide film formed by dry oxygen oxidation in the second oxidizing atmosphere does not exceed

[0024] As a preferred embodiment of the first aspect, the palladium source is an alcohol solution of palladium chloride, preferably an isopropanol solution of palladium chloride with a mass percentage of 5% to 20%; preferably, after the palladium source is coated on the surface of the wafer, sintering is performed after the isopropanol solvent has evaporated.

[0025] As a preferred embodiment of the first aspect, the low-temperature oxidation and dry oxygen oxidation are carried out in a fully automatic program-controlled furnace; and the directional palladium diffusion is carried out in a fully automatic program-controlled furnace.

[0026] As a preferred embodiment of the first aspect, the sintering temperature for the directional palladium diffusion is 750-1000°C.

[0027] As a preferred embodiment of the first aspect, the method of coating the palladium source on the surface of the wafer is a glue dripping method or a knife scraping method.

[0028] In a second aspect, the present invention provides a diode device obtained by processing a wafer produced by the method described in any one of the schemes in the first aspect.

[0029] As a preferred embodiment of the second aspect, the diode device types include fast recovery diodes FR, ultrafast recovery diodes SF, and high-efficiency rectifier diodes HER.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] The present invention adopts LTO (Low Temperature Oxidation) low temperature oxidation process technology, ultra-high purity oxygen carrying source silane, and forms a dense oxide film on the surface of an ordinary PIN diode diffusion wafer with grooves formed in a low temperature environment in an LTO oxidation furnace. After the photolithography and etching processes, precise directional palladium diffusion is performed. Thereby, a diffusion substrate with good concentration of parameters such as Vf (forward voltage drop) and Trr (reverse recovery time) is obtained, which significantly improves the chip utilization rate on the diffusion sheet and greatly improves the product quality. Compared with the use of expensive ion implanters, the present invention can greatly reduce costs while obtaining parameter quality relatively close to ion implantation. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is an example of a wafer with chip patterns after secondary photolithography and oxide layer etching;

[0033] Figure 2 It is the state when the dilute isopropanol solution of palladium chloride is scraped and infiltrated onto the surface of the chip;

[0034] Figure 3 The Trr distribution range of S42-S59 specification products before the present invention is adopted;

[0035] Figure 4 The Trr distribution range of the S42-S59 specification products after adopting the present invention;

[0036] Figure 5 This is the Trr distribution range of S95-S110 specification products before the present invention is adopted;

[0037] Figure 6 This is the Trr distribution range of products with specifications of S95 to S110 after adopting the present invention. DETAILED DESCRIPTION

[0038] In order to make the above-mentioned purpose, features and advantages of the present invention more obvious and easy to understand, the specific implementation mode of the present invention is described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The technical features in each embodiment of the present invention can be combined accordingly without conflicting with each other.

[0039] In the description of the present invention, it should be understood that the terms "first" and "second" are only used to distinguish the description purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0040] In a preferred embodiment of the present invention, a method for directional formation of palladium recombination centers by low temperature oxidation masking PN junction is provided, which comprises the following steps:

[0041] S1. Using a PIN diode diffusion wafer with a PN junction formed and etched grooves as the material, first use pure oxygen to carry silane to form a first oxidation atmosphere and perform low-temperature oxidation at 500-800°C, then use pure oxygen to form a second oxidation atmosphere and continue to perform dry oxygen oxidation at 500-800°C, thereby forming an oxide film on the surface of the wafer.

[0042] S2. Form a patterned mask on a wafer with an oxide film by photolithography, so that an oxide layer etching window is exposed in the center of each chip table, but the mask surrounding the oxide layer etching window is still retained at the edges of the chip table and in the grooves between the chip tables; then etch the oxide layer of the wafer to remove the oxide film within the range of each oxide layer etching window, and obtain a source attachment window for attaching a palladium source.

[0043] S3. Applying the palladium source to the surface of the wafer, and then directional diffusion of palladium is performed through sintering, so that the palladium impurities diffuse into the interior of the wafer to form a recombination center.

[0044] It should be noted that the above-mentioned method for processing the PIN diode diffusion wafer with a PN junction formed and etched grooves completed is: a silicon wafer is diffused with impurities to form a wafer with a rectifier diode PIN structure, and then subjected to photolithography and etching grooves to obtain a wafer with a chip pattern structure. The impurity diffusion method of the silicon wafer, the photolithography and etching grooves are all prior art.

[0045] As a preferred implementation of the embodiment of the present invention, the first oxidizing atmosphere is obtained by mixing high-purity oxygen and silane at a gas flow ratio of (1 to 3): 1 and continuously passing them into a low-temperature oxidizing environment. In practical applications, in order to facilitate the switching control of the first oxidizing atmosphere and the second oxidizing atmosphere, the high-purity oxygen source and the silane source can be connected to the air intake pipe respectively. When the first oxidizing atmosphere needs to be formed, both gas sources are turned on and their respective flow rates are controlled according to the corresponding flow ratio. When the second oxidizing atmosphere needs to be formed, the silane source can be turned off and only the pure oxygen source can be turned on.

[0046] It should be noted that, in order to avoid the introduction of impurities, the high-purity oxygen used in the present invention is preferably ultra-high-purity oxygen, the purity of which is greater than 99.999%.

[0047] It should be noted that the silane in the present invention is silane SiH4.

[0048] The present invention is different from the conventional process of first diffusing palladium and then etching. Instead, the present invention uses a wafer with a chip pattern after etching and slotting to perform directional palladium diffusion, so as to obtain a wafer with good uniformity and consistency.

[0049] Since the PN junction in the wafer with the chip pattern is exposed after etching, it must be protected before palladium diffusion can be performed. Therefore, an oxidation process is required to form a silicon dioxide film to cover the entire trench, especially the PN junction. The traditional oxidation process is to oxidize at a high temperature of more than 1100°C to form a thick Above, and dense oxide film. However, for the wafer after the PN junction (such as boron phosphorus) diffusion is completed, the high temperature above 1100°C will cause its doping redistribution and reduce the reverse breakdown voltage of the product. Depending on the oxidation time, its voltage attenuation can be as high as 50 to 100V. The above process method of the present invention adopts a low temperature environment of 500 to 800°C for oxidation.

[0050] Generally, the LTO process in the traditional glass packaging GPP process needs to take into account the protection of the glass layer. Its temperature can only be controlled between 250 and 500°C, resulting in a thin oxide layer thickness, generally not exceeding 100°C. The present invention does not perform glass sintering, so there is no concern about glass temperature, and the oxidation process is completed by combining LTO low-temperature oxidation process technology with a process temperature of 500-800° C. This can ensure the thickness of the oxide layer and avoid secondary distribution of boron and phosphorus impurities.

[0051] In addition, if the process of palladium diffusion followed by etching is followed by source oxidation, the palladium source will be precipitated from the vicinity of the PN junction, which will seriously affect the product's Trr parameter and increase it by dozens of times, and will also greatly increase the reverse leakage Ir. The ordinary PIN junction diode in the present invention will not be affected. In the first oxidation atmosphere, low-temperature LTO is combined with a process temperature of 500 to 800°C to form a silicon dioxide oxide film, and then the silane source is turned off, and the surface oxide film is increased in density by a pure oxygen dry oxygen oxidation process in the second oxidation atmosphere. Otherwise, the oxide layer formed by the previous step of low-temperature LTO is not dense enough. In the subsequent process of combining with the palladium composite center, the excess palladium source in the groove enters the vicinity of the PN junction through the non-dense oxide layer at high temperature, which will seriously affect the final reverse leakage IR and high-temperature leakage HTIR of the product, and will eventually directly lead to failure in the high-temperature reverse bias (HTRB) reliability test, and even directly lead to failure of the normal-temperature reverse leakage IR in conventional electrical tests.

[0052] In the present invention, the thickness of the oxide film formed in each of the two stages of oxidation needs to be reasonably controlled. As a preferred implementation of the present invention, in the process of forming an oxide film on the surface of the wafer, the thickness of the oxide film formed by low-temperature oxidation in the first oxidation atmosphere is Above, preferably The above, more preferably even The thickness of the oxide film formed by dry oxygen oxidation in the second oxidizing atmosphere is preferably not more than The goal is to form a dense layer that is sufficient to achieve the protective function.

[0053] After the wafer oxidation in step S1 is completed, the surface of the oxide wafer needs to be subjected to secondary photoresist and secondary lithography in step S2, and the oxide layer is etched to obtain a source window for the palladium source. Figure 1 As shown in the figure, a wafer with chip pattern after secondary photolithography and oxide layer etching is shown. Taking the common S130mil chip as an example, Figure 1 Each square in the figure is a chip table of a chip, where the square area indicated by A is the oxide layer etching window formed by photolithography, and the square ring area indicated by B is the retained silicon dioxide mask, that is, the part outside the window in the black area is masked and protected by the silicon dioxide oxide film. After the oxide layer is etched, the internal oxide layer of the oxide layer etching window indicated by A is removed, exposing the silicon crystal surface, forming a source attachment window for attaching the palladium source. The source attachment window will be filled in the subsequent palladium source solution coating process.

[0054] In the present invention, the specific palladium source used can be selected according to the actual process. As a preferred implementation of the embodiment of the present invention, the palladium source can be selected as an alcohol solution of palladium chloride, preferably an isopropanol solution of palladium chloride with a mass percentage of 5% to 20%. Preferably, when an isopropanol solution of palladium chloride is used as the palladium source, after the palladium source is coated on the surface of the wafer, sintering is performed after the isopropanol solvent has evaporated.

[0055] It should be noted that the oxidation process of S1, the photolithography and oxide layer etching process of S2, and the directional palladium diffusion process of S3 all rely on equipment related to the prior art, which is not the focus of the present invention. In order to facilitate the automation control of the entire process, the low-temperature oxidation and dry oxygen oxidation in S1 can be carried out in a fully automatic program-controlled furnace, and the directional palladium diffusion in S3 can be carried out in a fully automatic program-controlled furnace. Specifically, a fully automatic program-controlled oxidation furnace can be used in S1, and a fully automatic program-controlled diffusion furnace can be used in S3.

[0056] In addition, the specific process of directional palladium diffusion on the wafer can be the same as that in the prior art, and the specific sintering temperature and sintering time can be optimized according to the actual process conditions. As a preferred implementation of the embodiment of the present invention, the sintering temperature used when directional palladium diffusion is performed on the wafer is 750-1000°C.

[0057] In addition, the method of coating the palladium source on the surface of the wafer can be selected according to actual conditions, so as to make the palladium source evenly coated. Generally speaking, there are two optional coating methods, one is to place the silicon wafer on a rotating chuck and perform spin coating by dropper or brush, and the other is to place the silicon wafer under a screen and use a scraper to scrape.

[0058] The advantage of spin coating is its wide range of applications. Low-viscosity solutions can be applied by brushing, and high-concentration solutions can be applied by dropper at high speed. However, its disadvantage is also obvious, that is, its uniformity is difficult to control. Generally, a gradient concentration difference will be formed from the center to the outer circle, and the concentration will be lower as you go to the outer circle. This phenomenon is more obvious when making large-sized diode chips, especially for 5-inch or even 6-inch substrates, where the concentration difference between the inner and outer circles is as high as 50%. This disadvantage is difficult to avoid whether using fully automatic equipment or semi-automatic / manual equipment. Spin coating is usually suitable for occasions where surface coating deviation is not required, such as photolithography glue leveling, laser protective liquid coating, etc.

[0059] The advantage of scraping coating is just the opposite. Since a scraper larger than the diameter of the silicon wafer is used, similar to the principle of screen printing, as long as the height and level of the screen are adjusted, the uniformity of the coating on the silicon wafer surface after scraping can be guaranteed. However, it has strong limitations and is mainly used for some high-viscosity situations with good surface tension, such as scraping glass slurry. The isopropanol solution of palladium chloride is a dilute solution with low viscosity, which makes it impossible to be coated on the silicon wafer surface by a scraper. Therefore, it can only be coated by spin coating under traditional processes.

[0060] However, in the present invention, the oxide film is formed before the palladium source is applied and around the source window in advance, so the unevenness problem in the dilute solution coating process can be solved. Figure 1 As shown in the figure, each black area indicated by A is the source window obtained after etching the oxide layer, and the surrounding white area indicated by B is the thicker oxide layer area. Due to the compactness of the silicon dioxide oxide layer, it has a greater hydrophobicity, so the isopropyl alcohol solution has a very high surface tension on the chip surface. At this time, after the solution is infiltrated into the chip through the grid by scraping, a surface tension like the following will be formed on each black window. Figure 2 The droplets shown can ensure that the isopropanol solution is evenly distributed on each chip surface.

[0061] As a preferred implementation method of the embodiment of the present invention, the scraping equipment adopts conventional equipment used for screen printing, and the solution is scraped back and forth onto the surface of the wafer by a scraper. After ensuring that the machine is level, as long as a uniform isopropanol solution of palladium chloride is used, the palladium source concentration on each chip surface of the wafer can be kept consistent. After scraping, the wafer needs to be placed on a hot plate or oven in time. After the solvent isopropanol evaporates, it can be sintered at a temperature of 750 to 1000°C to complete the palladium impurity diffusion process.

[0062] The methods described in S1 to S3 of the present invention can be used to obtain corresponding silicon core wafers in the process of generating diode devices, and the silicon core wafers can be subjected to post-processing to form silicon diodes. The specific post-processing processes include degumming, sawing, welding, cleaning, table passivation, compression molding, packaging, etc., which can be selected according to the actual diode processing process.

[0063] The present invention is applicable to all diode diffusion sheets that need to form a recombination center by introducing impurity palladium to improve the switching speed, such as a fast recovery diode FR, an ultrafast recovery diode SF, and a high-efficiency rectifier diode HER.

[0064] In order to demonstrate the effects that can be achieved by the methods described in S1 to S3 of the present invention, a specific practical application case is presented below.

[0065] Example

[0066] In this embodiment, the chip manufacturing of two specification ranges (S42-S59 and S95-S130) of ultrafast recovery diode SF chips with the most stringent parameter requirements is taken as an example. This embodiment uses a PIN structure diffusion wafer with a finished voltage range of 600-800V for production, in which the PN junction required for the rectifier diode is formed by impurity diffusion, and the subsequent processing method is as follows:

[0067] First, according to the normal chip circulation procedure, the chips are slotted at the photolithography station and the etching station to form chips with chip graphic structures of corresponding sizes. After the wafer is cleaned again, it is sent to a fully automatic programmable furnace. Ultra-high purity oxygen with a purity greater than 99.999% carries silane into the furnace at a gas flow ratio of 1:1 to form an oxidizing atmosphere. The chip is subjected to LTO low-temperature oxidation at 550°C in the furnace for 80 minutes. The silane gas is then turned off and ultra-high purity oxygen is continued to be introduced as the oxidizing atmosphere. The pure oxygen dry oxygen oxidation is performed for 20 minutes to improve the density of the oxide layer. The oxide layer thickness of the wafer that has been oxidized is measured to be approximately

[0068] Subsequently, the wafer is sent to the photolithography station and etching station again for secondary photolithography and oxide layer etching (same as the conventional chip transfer process) to obtain the palladium diffusion source window (the control source window is located at the center of the chip table and is 20 to 30 mil smaller than the chip table). Figure 1 As shown. After the conventional oxide wafer cleaning process again, the isopropanol solution of palladium chloride with a mass ratio of 1:10 is evenly coated on each chip surface using the knife scraping method in screen printing. After scraping, the wafer needs to be placed on a hot plate or oven in time. After the solvent isopropanol evaporates, the wafer can be sintered for 30 minutes according to the diffusion sintering temperature requirements corresponding to the production process (S45~S59 mil: 800℃, S95~S130 mil: 820℃) to diffuse the palladium impurities into the vicinity of the silicon PN junction to form a composite center. Subsequently, the production and testing of a single chip is completed according to the conventional GPP process.

[0069] The present invention uses a computer to automatically collect online test data of the final product, and compares it after computer fitting. It can be found that after the product uses the process method of the invention, the distribution from the center to the outer circle of the product is obviously converged, the qualified rate is greatly improved, and the economic benefit is significantly improved. The specific results are shown below:

[0070] For small-sized chips, we select the exact center of each chip, the half radius, and the outermost 1-3 mm position. We use a computer to randomly select 10,000 chips from thousands of wafers tested online and collect Trr data for statistics. See Table 1 and Figure 3 and Figure 4As shown, it is obvious that after adopting the present invention, the normal distribution of Trr of the chip is more convergent. At the same time, according to the automatic control requirements, before adopting the present invention, there are 237 chips outside the range of 22-36ns, accounting for 0.79% of the total. After adopting the present invention, all the 30,000 chips sampled are qualified.

[0071] Table 1 Chip Trr distribution of S42-S59 specification products before and after using the present invention (pieces)

[0072]

[0073] *Through the computer in the online test, 10,000 chips are randomly selected from the three areas of the chip data.

[0074] For medium and large size chips, we also select the exact center of each chip, the half radius, and the outermost 1-3 mm position. These three positions are randomly selected by computer from thousands of wafers tested online, and the Trr data of 5,000 chips are collected for statistics. See Table 2 and Figure 5 and Figure 6 As shown, after adopting the present invention, the Trr normal distribution of the chip is more convergent.

[0075] According to the self-control requirements, although the product parameters are qualified for the products before and after the invention, the Trr concentration of the products after the invention is better. From the above-mentioned formula of the relationship between the stored charge and the forward voltage, it can be seen that the Vf forward voltage can be made smaller by improving the process (i.e., accurately controlling the Trr value to a parameter close to the upper limit), which is more conducive to reducing the power consumption in the switching circuit, making the final packaged diode product more efficient and energy-saving.

[0076] Table 2 Chip Trr distribution of S95-S110 specification products before and after using the present invention (pieces)

[0077]

[0078] *5,000 chips are randomly selected from three areas of the chip during online testing by computer

[0079] The above-described embodiment is only a preferred solution of the present invention, but it is not intended to limit the present invention. A person skilled in the relevant technical field may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, any technical solution obtained by equivalent replacement or equivalent transformation falls within the protection scope of the present invention.

Claims

1. A method for directional formation of palladium complex centers by low temperature oxidation masking PN junction, characterized in that: include: S1, using a PIN diode diffusion wafer with a PN junction formed and etched grooves completed as a material, forming a chip pattern structure on the surface of the wafer after the etching and grooving is completed, firstly using pure oxygen to carry silane to form a first oxidation atmosphere and perform low-temperature oxidation at 500-800° C., then using pure oxygen to form a second oxidation atmosphere and continue to perform dry oxygen oxidation at 500-800° C., thereby forming an oxide film on the surface of the wafer; S2. Forming a patterned mask on the wafer with the oxide film by photolithography, so that the center of each chip mesa exposes an oxide layer etching window, but the mask surrounding the oxide layer etching window is still retained at the edge of the chip mesa and in the grooves between the chip mesas; Then, the wafer is etched for oxide layer, and the oxide film within the range of each oxide layer etching window is removed to obtain a source attachment window for attaching a palladium source; S3. Applying the palladium source to the surface of the wafer, and then directional diffusion of palladium is performed through sintering, so that the palladium impurities diffuse into the interior of the wafer to form a recombination center.

2. The method for forming palladium complex centers by low temperature oxidation masking PN junction orientation according to claim 1, characterized in that: The processing method of the PIN diode diffusion wafer with a PN junction formed and etched grooves completed is: a silicon wafer is diffused with impurities to form a wafer with a rectifier diode PIN structure, and then subjected to photolithography and etching grooves to obtain a wafer with a chip pattern structure.

3. The method for forming palladium complex centers by low temperature oxidation masking PN junction orientation according to claim 1, characterized in that: The first oxidizing atmosphere is obtained by mixing high-purity oxygen and silane in a gas flow ratio of (1-3):1 and continuously passing the mixture into a low-temperature oxidizing environment.

4. The method for forming palladium complex centers by low temperature oxidation masking PN junction orientation according to claim 1, characterized in that: In the process of forming an oxide film on the surface of the wafer, the thickness of the oxide film formed by low-temperature oxidation in the first oxidation atmosphere is more than 3000Å; the thickness of the oxide film formed by dry oxygen oxidation in the second oxidation atmosphere does not exceed 500Å.

5. The method for forming palladium complex centers by low temperature oxidation masking PN junction orientation according to claim 4, characterized in that: The thickness of the oxide film formed by low-temperature oxidation in the first oxidizing atmosphere is greater than 5000Å.

6. The method for forming palladium complex centers by low temperature oxidation masking PN junction orientation according to claim 5, characterized in that: The thickness of the oxide film formed by low-temperature oxidation in the first oxidation atmosphere is 6000Å~9000Å.

7. The method for forming palladium complex centers by low temperature oxidation masking PN junction orientation according to claim 1, characterized in that: The palladium source is an alcohol solution of palladium chloride.

8. The method for forming palladium complex centers by low temperature oxidation masking PN junction orientation according to claim 7, characterized in that: The palladium source is an isopropanol solution of palladium chloride with a mass percentage of 5% to 20%.

9. The method for forming palladium complex centers by low temperature oxidation masking PN junction orientation according to claim 7, characterized in that: After the palladium source is coated on the surface of the chip, sintering is performed after the isopropanol solvent evaporates completely.

10. The method for forming palladium complex centers by low temperature oxidation masking PN junction orientation according to claim 1, characterized in that: The low-temperature oxidation and dry oxygen oxidation are carried out in a fully automatic program-controlled furnace; and the directional palladium diffusion is carried out in a fully automatic program-controlled furnace.

11. The method for forming palladium complex centers by low temperature oxidation masking PN junction orientation according to claim 1, characterized in that: The sintering temperature for the directional palladium diffusion is 750-1000°C.

12. The method for forming palladium complex centers by low temperature oxidation masking PN junction orientation according to claim 1, characterized in that: The method of coating the palladium source on the surface of the wafer is a glue dripping method or a knife scraping method.

13. A diode device, characterized in that: The method is obtained by processing a wafer produced by any one of the methods described in claims 1 to 12.

14. The diode device according to claim 13, characterized in that The diode device types include fast recovery diodes FR, ultrafast recovery diodes SF, and high-efficiency rectifier diodes HER.

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