Control circuit for dc-dc power tube

Abstract

The embodiment of the present disclosure provides a control circuit of a DC-DC power tube, and belongs to the technical field of integrated circuits. The circuit comprises: a switching circuit, which generates a first current signal and provides the first current signal to a power tube circuit via a first node in a first working state, and generates a first switch signal and provides the first switch signal to an output circuit via a second node in a second working state; the power tube circuit generates a first mirror signal of the first current signal and provides the first mirror signal to the output circuit via the second node in the first working state, and generates a second switch signal and provides the second switch signal to the output circuit via the second node in the second working state; and the output circuit is configured to perform a pre-charge operation by using the first mirror signal in the first working state, and output the first switch signal and the second switch signal via a signal output end in the second working state, wherein the first switch signal and the second switch signal are synchronous.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of integrated circuit technology, and more specifically to a control circuit for a DC-DC power transistor. Background Technology

[0002] In analog circuit design, there are often constant current applications used for pre-charging, such as Boost DC-DC applications. Sometimes, constant current pre-charging is required to charge the output voltage from the input voltage. The DC-DC circuit only starts to work normally after the output voltage reaches a certain requirement.

[0003] The existing implementation uses a current mirror circuit to clamp the gate-source voltage of the power transistor in the DC-DC converter to achieve constant current charging. However, this implementation has the following drawbacks: Firstly, the current mirror circuit is inaccurate, and during the constant current process, due to the influence of heat power, the threshold voltages of the power transistor and the transistor in the current mirror circuit change inconsistently with temperature, causing a significant current shift over time. Secondly, the power transistor is in a periodic switching state during normal DC-DC operation, but the transistor in the current mirror circuit only operates during the pre-charging phase. This leads to an increasing difference in the threshold voltages of the power transistor and the transistor in the current mirror circuit after prolonged use, causing very large changes in the constant current and resulting in inaccurate constant current during the pre-charging process. Summary of the Invention

[0004] The purpose of this disclosure is to provide a control circuit for a DC-DC power transistor. The transistor in the current mirror circuit that participates in the constant current pre-charging process, together with one of the power transistors in the DC-DC converter, performs periodic switching operations as the switching transistor of the DC-DC converter during normal operation. As a result, after long-term use or after a life aging test, the characteristics of the transistor and the power transistor change in the same way, and the current variation during constant current charging is also smaller.

[0005] To achieve the above objectives, this disclosure provides a control circuit for a DC-DC power transistor, comprising: a switching circuit, a power transistor circuit, and an output circuit. The switching circuit is configured to generate a first current signal and provide it to the power transistor circuit via a first node in a first operating state, and to generate a first switching signal and provide it to the output circuit via a second node in a second operating state. The power transistor circuit is configured to generate a first mirror signal of the first current signal and provide it to the output circuit via a second node in the first operating state, and to generate a second switching signal and provide it to the output circuit via a second node in the second operating state. The output circuit is configured to perform a pre-charge operation using the first mirror signal in the first operating state, and to output the first switching signal and the second switching signal via a signal output terminal in the second operating state, wherein the first switching signal and the second switching signal are synchronized.

[0006] In some embodiments of this disclosure, the power transistor circuit includes: a DC-DC control module, a first power transistor, a second power transistor, and a first inductor. The input terminal of the DC-DC control module is coupled to a pulse width modulation (PWM) signal terminal; the first output terminal of the DC-DC control module is coupled to the control electrode of the first power transistor; the second output terminal of the DC-DC control module is coupled to the control electrode of the second power transistor; the DC-DC control module is configured to drive the first power transistor and the second power transistor according to the PWM signal; the first electrode of the first power transistor is coupled to a second node, and the second electrode of the first power transistor is coupled to the first node; the first electrode of the second power transistor is coupled to the first node, and the second electrode of the second power transistor is coupled to a second voltage terminal; the first terminal of the first inductor is coupled to the first node, and the second terminal of the first inductor is coupled to a first voltage terminal.

[0007] In some embodiments of this disclosure, the switching circuit includes: a first transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a first current source. The control electrode of the first transistor is coupled to the control electrode of the first power transistor; the first electrode of the first transistor is coupled to the second terminal of the second switch and the second terminal of the third switch; the second electrode of the first transistor is coupled to the first terminal of the first switch, the second terminal of the fourth switch, and the first terminal of the fifth switch; the second terminal of the first switch is coupled to the control electrode of the first transistor; the first terminal of the second switch is coupled to the second node; the first terminal of the third switch is coupled to the first node; the first terminal of the fourth switch is coupled to the first node; the second terminal of the fifth switch is coupled to the first terminal of the first current source; and the second terminal of the first current source is coupled to the second voltage terminal.

[0008] In some embodiments of this disclosure, when in the first working state, the first switch, the third switch, and the fifth switch are closed simultaneously, and the second switch and the fourth switch are open simultaneously; when in the second working state, the first switch, the third switch, and the fifth switch are open simultaneously, and the second switch and the fourth switch are closed simultaneously.

[0009] In some embodiments of this disclosure, the output circuit includes a first capacitor. A first terminal of the first capacitor is coupled to the second node and the signal output terminal, and a second terminal of the first capacitor is coupled to a second voltage terminal.

[0010] In some embodiments of this disclosure, the first transistor and the first power transistor are both PMOS transistors, and the second power transistor is an NMOS transistor.

[0011] In some embodiments of this disclosure, the power transistor circuit includes: a DC-DC control module, a first power transistor, and a second power transistor. The input terminal of the DC-DC control module is coupled to a pulse width modulation (PWM) signal terminal; the first output terminal of the DC-DC control module is coupled to the control terminal of the first power transistor; the second output terminal of the DC-DC control module is coupled to the control terminal of the second power transistor; the DC-DC control module is configured to drive the first power transistor and the second power transistor according to the PWM signal; the first terminal of the first power transistor is coupled to the first node; the second terminal of the first power transistor is coupled to the second node; and the second terminal of the second power transistor is coupled to a second voltage terminal.

[0012] In some embodiments of this disclosure, the switching circuit includes: a first transistor, a first switch, a second switch, a third switch, and a first current source. The control electrode of the first transistor is coupled to the control electrode of the first power transistor and the second terminal of the second switch; the first electrode of the first transistor is coupled to the first terminal of the first switch, the first terminal of the second switch, and the second terminal of the third switch; the second electrode of the first transistor is coupled to the second node; the second terminal of the first switch is coupled to the first terminal of the first current source; the first terminal of the third switch is coupled to the first node; and the second terminal of the first current source is coupled to the first node.

[0013] In some embodiments of this disclosure, when in the first working state, the first switch and the second switch are closed simultaneously, and the third switch is open; when in the second working state, the third switch is closed, and the first switch and the second switch are open simultaneously.

[0014] In some embodiments of this disclosure, the output circuit includes a first inductor and a first capacitor. A first terminal of the first inductor is coupled to the second node, and a second terminal of the first inductor is coupled to the signal output terminal; a first terminal of the first capacitor is coupled to the signal output terminal, and a second terminal of the first capacitor is coupled to a second voltage terminal.

[0015] In some embodiments of this disclosure, the first transistor, the first power transistor, and the second power transistor are all NMOS transistors.

[0016] In some embodiments of this disclosure, the first transistor is embedded in the middle of the first power transistor.

[0017] In some embodiments of this disclosure, the first operating state is a constant current pre-charge state, and the second operating state is a DC-DC normal operating state.

[0018] In some embodiments of this disclosure, the DC-DC control module includes: a PWM control module, a first drive module, and a second drive module. The input terminal of the PWM control module is coupled to the input terminal of the DC-DC control module; the first output terminal of the PWM control module is coupled to the input terminal of the first drive module; the second output terminal of the PWM control module is coupled to the input terminal of the second drive module; and the PWM control module is configured to provide the PWM signal. The output terminal of the first drive module is coupled to the first output terminal of the DC-DC control module; and the first drive module is configured to drive the first power transistor according to the PWM signal. The output terminal of the second drive module is coupled to the second output terminal of the DC-DC control module; and the second drive module is configured to drive the second power transistor according to the PWM signal.

[0019] According to the control circuit of the DC-DC power transistor in the embodiments of this disclosure, the current mirror circuit participating in the constant current pre-charging is switched to perform periodic switching operation together with one of the power transistors in the DC-DC as the switching transistor of the DC-DC when the DC-DC is working normally. As a result, after long-term use or after life aging test, the current mirror circuit is consistent with the change of the power transistor characteristics, and the change of constant current charging current is also smaller.

[0020] Other features and advantages of the embodiments disclosed herein will be described in detail in the following detailed description section. Attached Figure Description

[0021] The accompanying drawings are provided to further illustrate embodiments of the present disclosure and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present disclosure, but do not constitute a limitation on the embodiments of the present disclosure. In the drawings:

[0022] Figure 1 This is an exemplary circuit diagram of a constant current pre-charge circuit 100;

[0023] Figure 2 This is a layout example of PMOS transistors MP0 and MP1 in a constant current precharge circuit 100 on a chip layout.

[0024] Figure 3 This is a schematic block diagram of a control circuit 300 for a DC-DC power transistor according to an embodiment of the present disclosure;

[0025] Figure 4 This is an exemplary circuit diagram of a control circuit 300 for a DC-DC power transistor according to an embodiment of the present disclosure;

[0026] Figure 5 This is another exemplary circuit diagram of the control circuit 300 for the DC-DC power transistor according to an embodiment of the present disclosure;

[0027] Figure 6 This is yet another exemplary circuit diagram of the control circuit 300 for the DC-DC power transistor according to an embodiment of the present disclosure;

[0028] Figure 7 This is another exemplary circuit diagram of the control circuit 300 for the DC-DC power transistor according to an embodiment of the present disclosure;

[0029] Figure 8 This is yet another exemplary circuit diagram of a control circuit 300 for a DC-DC power transistor according to an embodiment of the present disclosure;

[0030] Figure 9 This is yet another exemplary circuit diagram of a control circuit 300 for a DC-DC power transistor according to an embodiment of the present disclosure;

[0031] Figure 10 This is an example layout diagram of the first transistor M3 and the first power transistor M1 on a chip layout in the control circuit 300 of the DC-DC power transistor according to an embodiment of the present disclosure.

[0032] The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0034] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0035] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. Furthermore, for the sake of consistency, in this context, the base of a bipolar junction transistor (BJT) is referred to as the control terminal, the emitter of the BJT as the first terminal, and the collector of the BJT as the second terminal. Additionally, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0036] Figure 1 An exemplary circuit diagram of a constant current pre-charge circuit 100 is shown. Figure 1In the example, PMOS transistor MP1 is an upper power transistor in the DC-DC converter, PMOS transistor MP0 is a constant current precharge current mirror transistor, NMOS transistor MN1 is a lower power transistor in the DC-DC converter, DRP is the driver of the upper power transistor in the DC-DC converter, DRN is the driver of the lower power transistor in the DC-DC converter, and PWMControl is the control part of the DC-DC converter.

[0037] During the constant current pre-charge phase, switch S1 is open and switch S2 is closed. At this time, PMOS transistors MP1 and MP0 form a current mirror relationship. The gate-source voltage of PMOS transistor MP1 is clamped by the gate-source voltage of PMOS transistor MP0. The current Ichg flows from VIN through inductor L to the SW pin, and then through PMOS transistor MP1 to VOUT to pre-charge the output capacitor Cout. When the DC-DC converter is operating normally, switch S1 is closed and switch S2 is open. The gates of PMOS transistors MP0 and MP1 are disconnected. At this time, PMOS transistor MP1 operates in a periodic switching state.

[0038] at the same time, Figure 2 This diagram shows an example layout of PMOS transistors MP0 and MP1 on a chip layout, as shown below. Figure 2 As shown, PMOS transistor MP0, as a current mirror, is usually placed near PMOS transistor MP1. At this time, the thermal radiation of PMOS transistor MP1 is mainly in one direction, and the threshold voltage changes of PMOS transistor MP0 and PMOS transistor MP1 due to heat are also different.

[0039] During constant current charging, due to the influence of heat, the threshold voltages of PMOS transistor MP1 and current mirror PMOS transistor MP0 change inconsistently with temperature, causing a significant current deviation over time. Furthermore, while PMOS transistor MP1 operates in a periodic switching state during normal use, current mirror PMOS transistor MP0 only operates during the pre-charging phase. This leads to an increasing difference in threshold voltages between PMOS transistors MP0 and MP1 after prolonged use, resulting in substantial variations in the constant current and ultimately inaccurate constant current charging.

[0040] Embodiments of this disclosure provide a control circuit for a DC-DC power transistor. This control circuit for the DC-DC power transistor can improve the current accuracy of constant current charging. Figure 3 A schematic block diagram of a control circuit 300 for a DC-DC power transistor according to an embodiment of the present disclosure is shown. Figure 3 As shown, the control circuit 300 for the DC-DC power transistor may include: a switching circuit 310, a power transistor circuit 320, and an output circuit 330.

[0041] The switching circuit 310 can be coupled to the power transistor circuit 320 and the output circuit 330. The switching circuit 310 can be configured to generate a first current signal I1 and provide it to the power transistor circuit 320 via a first node N1 in a first operating state, and to generate a first switching signal G1 and provide it to the output circuit 330 via a second node N2 in a second operating state. In this embodiment, the first operating state is a constant current pre-charge state, and the second operating state is a DC-DC normal operating state.

[0042] The power transistor circuit 320 can be coupled to the switching circuit 310, the output circuit 330, the PWM signal terminal, the first voltage terminal V1, and the second voltage terminal V2. The power transistor circuit 320 can be configured to, in the first operating state, generate a first mirror signal I1' of the first current signal I1 and provide the first mirror signal I1' to the output circuit 330 via the second node N2; and in the second operating state, generate a second switching signal G2 and provide the second switching signal G2 to the output circuit 330 via the second node N2. Here, the first mirror signal I1' is a current signal. In some embodiments of this disclosure, since the first mirror signal I1' is a mirror signal of the first current signal I1, the first mirror signal I1' is the same as the first current signal I1.

[0043] The output circuit 330 can be coupled to the switching circuit 310, the power transistor circuit 320, the signal output terminal OUT, and the second voltage terminal V2. The output circuit 330 can be configured to perform a pre-charge operation using the first mirror signal I1' in the first operating state, and to output the first switch signal G1 and the second switch signal G2 via the signal output terminal OUT in the second operating state, wherein the first switch signal G1 and the second switch signal G2 are synchronized.

[0044] According to the control circuit of the DC-DC power transistor in the embodiments of this disclosure, the current mirror circuit participating in the constant current pre-charging is switched to perform periodic switching operation together with one of the power transistors in the DC-DC as the switching transistor of the DC-DC when the DC-DC is working normally. As a result, after long-term use or after life aging test, the current mirror circuit is consistent with the change of the power transistor characteristics, and the change of constant current charging current is also smaller.

[0045] In the embodiments of this disclosure, the control circuit of the DC-DC power transistor has two control modes: one is a control mode in which a PMOS transistor is used as a switch and a current mirror for pre-charging, and the other is a control mode in which an NMOS transistor is used as a switch and a current mirror for pre-charging. Exemplary circuit diagrams of the control circuit 300 of the DC-DC power transistor in the embodiments of this disclosure will be described below under both control modes.

[0046] Figure 4 An exemplary circuit diagram of a control circuit 300 for a DC-DC power transistor according to an embodiment of the present disclosure is shown, which utilizes a PMOS transistor as both a switch and a current mirror for pre-charging control. Figure 4 As shown, the power transistor circuit 320 may include: a DC-DC control module 321, a first power transistor M1, a second power transistor M2, and a first inductor L1. The input terminal of the DC-DC control module 321 is coupled to a PWM signal terminal. The first output terminal of the DC-DC control module 321 is coupled to the control terminal of the first power transistor M1, and the second output terminal of the DC-DC control module 321 is coupled to the control terminal of the second power transistor M2. The DC-DC control module 321 is configured to drive the first power transistor M1 and the second power transistor M2 according to the PWM signal. The first terminal of the first power transistor M1 is coupled to the second node N2, and the second terminal of the first power transistor M1 is coupled to the first node N1 (i.e., the SW pin). The first terminal of the second power transistor M2 is coupled to the first node N1, and the second terminal of the second power transistor M2 is coupled to the second voltage terminal V2. The first terminal of the first inductor L1 is coupled to the first node N1, and the second terminal of the first inductor L1 is coupled to the first voltage terminal V1.

[0047] The DC-DC control module 321 may include a PWM control module 211, a first drive module 212, and a second drive module 213. The input terminal of the PWM control module 211 is coupled to the input terminal of the DC-DC control module 321. The first output terminal of the PWM control module 211 is coupled to the input terminal of the first drive module 212, and the second output terminal of the PWM control module 211 is coupled to the input terminal of the second drive module 213. The PWM control module 211 is configured to provide the PWM signal. The output terminal of the first drive module 212 is coupled to the first output terminal of the DC-DC control module 321, and the first drive module 212 is configured to drive the first power transistor M1 according to the PWM signal. The output terminal of the second drive module 213 is coupled to the second output terminal of the DC-DC control module 321, and the second drive module 213 is configured to drive the second power transistor M2 according to the PWM signal.

[0048] The switching circuit 310 may include: a first transistor M3, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, and a first current source I. A The control electrode of the first transistor M3 is coupled to the control electrode of the first power transistor M1. The first electrode of the first transistor M3 is coupled to the second terminal of the second switch S2 and the second terminal of the third switch S3. The second electrode of the first transistor M3 is coupled to the first terminal of the first switch S1, the second terminal of the fourth switch S4, and the first terminal of the fifth switch S5. The second terminal of the first switch S1 is coupled to the control electrode of the first transistor M3. The first terminal of the second switch S2 is coupled to the second node N2. The first terminal of the third switch S3 is coupled to the first node N1. The first terminal of the fourth switch S4 is coupled to the first node N1. The second terminal of the fifth switch S5 is coupled to the first current source I. A The first end. The first current source I A The second end is coupled to the second voltage terminal V2.

[0049] The output circuit 330 may include a first capacitor C1. A first terminal of the first capacitor C1 is coupled to the second node N2 and the signal output terminal OUT, and a second terminal of the first capacitor C1 is coupled to a second voltage terminal V2.

[0050] exist Figure 4 In the example, a high-voltage signal is input from the first voltage terminal V1, a PWM signal is input from the PWM signal terminal, and the second voltage terminal V2 is grounded. The first power transistor M1 and the first transistor M3 are both PMOS transistors, and the second power transistor M2 is an NMOS transistor. Those skilled in the art will understand that, based on the above inventive concept... Figure 4 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 4 The examples shown have different settings.

[0051] The following is combined with Figure 4 The following example illustrates the operation of a control circuit 300 for a DC-DC power transistor, in which a PMOS transistor acts as both a switch and a current mirror, according to embodiments of the present disclosure.

[0052] In the first operating state, i.e., the constant current pre-charge state, the first switch S1, the third switch S3, and the fifth switch S5 are simultaneously closed, while the second switch S2 and the fourth switch S4 are simultaneously open. Figure 5As shown, the control electrode (gate) and the drain electrode (drain) of the first transistor M3 are connected together to form a diode-like structure. The gate-source voltage of the first transistor M3 depends on the size of the first transistor M3 and the first current signal I1 flowing through the first transistor M3. The source of the first transistor M3 is connected to the first node N1 (i.e., the SW pin). At this time, the first power transistor M1 and the first transistor M3 form a current mirror relationship. The gate-source voltage of the first power transistor M1 is clamped by the gate-source voltage of the first transistor M3. The first mirror signal I1' flows from the first voltage terminal V1 through the first inductor L1 to the first node N1, and then through the first power transistor M1 to the signal output terminal OUT to precharge the first capacitor C1.

[0053] When the constant current pre-charge ends and the system enters the second operating state, i.e., the normal DC-DC operating state, the first switch S1, the third switch S3, and the fifth switch S5 are simultaneously open, while the second switch S2 and the fourth switch S4 are simultaneously closed. Figure 6 As shown. At this time, the connection method of the first transistor M3 is the same as that of the first power transistor M1. The second terminal (i.e., drain) of the first transistor M3 is connected to the second terminal (i.e., drain) of the first power transistor M1, and the first terminal (i.e., source) of the first transistor M3 is connected to the first terminal (i.e. source) of the first power transistor M1. When the first power transistor M1 is working in the periodic switching DC-DC Boost state, the first transistor M3 is also working in the periodic switching DC-DC Boost state. That is to say, the first switching signal G1 generated by the first transistor M3 is synchronized with the second switching signal G2 generated by the first power transistor M1.

[0054] Figure 7 Another exemplary circuit diagram of a control circuit 300 for a DC-DC power transistor according to an embodiment of the present disclosure is shown, which utilizes an NMOS transistor as a switch and current mirror for pre-charging control. Figure 7As shown, the power transistor circuit 320 may include: a DC-DC control module 321, a first power transistor M1, and a second power transistor M2. The input terminal of the DC-DC control module 321 is coupled to a PWM signal terminal. The first output terminal of the DC-DC control module 321 is coupled to the control terminal of the first power transistor M1, and the second output terminal of the DC-DC control module 321 is coupled to the control terminal of the second power transistor M2. The DC-DC control module 321 is configured to drive the first power transistor M1 and the second power transistor M2 according to the PWM signal. The first terminal of the first power transistor M1 is coupled to the first node N1, and the second terminal of the first power transistor M1 is coupled to the second node N2 (i.e., the SW pin). The first terminal of the second power transistor M2 is coupled to the second node N2, and the second terminal of the second power transistor M2 is coupled to a second voltage terminal V2.

[0055] The DC-DC control module 321 may include a PWM control module 211, a first drive module 212, and a second drive module 213. The input terminal of the PWM control module 211 is coupled to the input terminal of the DC-DC control module 321. The first output terminal of the PWM control module 211 is coupled to the input terminal of the first drive module 212, and the second output terminal of the PWM control module 211 is coupled to the input terminal of the second drive module 213. The PWM control module 211 is configured to provide the PWM signal. The output terminal of the first drive module 212 is coupled to the first output terminal of the DC-DC control module 321, and the first drive module 212 is configured to drive the first power transistor M1 according to the PWM signal. The output terminal of the second drive module 213 is coupled to the second output terminal of the DC-DC control module 321, and the second drive module 213 is configured to drive the second power transistor M2 according to the PWM signal.

[0056] The switching circuit 310 may include: a first transistor M3, a first switch S1, a second switch S2, a third switch S3, and a first current source I. A The control electrode of the first transistor M3 is coupled to the control electrode of the first power transistor M1 and the second terminal of the second switch S2. The first electrode of the first transistor M3 is coupled to the first terminal of the first switch S1, the first terminal of the second switch S2, and the second terminal of the third switch S3. The second electrode of the first transistor M3 is coupled to the second node N2. The second terminal of the first switch S1 is coupled to the first current source I. A The first terminal of the third switch S3 is coupled to the first node N1. The first current source I... A The second end is coupled to the first node N1.

[0057] The output circuit 330 may include a first inductor L1 and a first capacitor C1. The first terminal of the first inductor L1 is coupled to the second node N2, and the second terminal of the first inductor L1 is coupled to the signal output terminal OUT. The first terminal of the first capacitor C1 is coupled to the signal output terminal OUT, and the second terminal of the first capacitor C1 is coupled to the second voltage terminal V2.

[0058] exist Figure 7 In the example, a high-voltage signal is input from the first voltage terminal V1, a PWM signal is input from the PWM signal terminal, and the second voltage terminal V2 is grounded. The first power transistor M1, the second power transistor M2, and the first transistor M3 are all NMOS transistors. Those skilled in the art will understand that, based on the above inventive concept... Figure 7 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 7 The examples shown have different settings.

[0059] The following is combined with Figure 7 The following example illustrates the operation of a control circuit 300 for a DC-DC power transistor, in which an NMOS transistor acts as both a switch and a current mirror, according to embodiments of the present disclosure.

[0060] In the first operating state, i.e., the constant current pre-charge state, the first switch S1 and the second switch S2 are simultaneously closed, and the third switch S3 is open, as follows: Figure 8 As shown. At this time, the first power transistor M1 and the first transistor M3 form a current mirror relationship. The first mirror signal I1' flows from the first voltage terminal V1 through the first power transistor M1 to the second node N2, and then through the first inductor L1 to reach the signal output terminal OUT to precharge the first capacitor C1.

[0061] When the constant current pre-charging ends and the system enters the second operating state, i.e., the normal DC-DC operating state, the third switch S3 closes, and the first switch S1 and the second switch S2 simultaneously open. Figure 9 As shown. At this time, the connection method of the first transistor M3 is the same as that of the first power transistor M1. The second terminal (i.e., the source) of the first transistor M3 is connected to the second terminal (i.e., the source) of the first power transistor M1, and the first terminal (i.e., the drain) of the first transistor M3 is connected to the first terminal (i.e., the drain) of the first power transistor M1. When the first power transistor M1 is working in the periodic switching DC-DC Boost state, the first transistor M3 is also working in the periodic switching DC-DC Boost state. That is to say, the first switching signal G1 generated by the first transistor M3 is synchronized with the second switching signal G2 generated by the first power transistor M1.

[0062] In addition, to further reduce the consistency deviation of the threshold voltage between the first power transistor M1 and the first transistor M3, such as Figure 10 As shown, the first transistor M3 is embedded in the middle of the first power transistor M1, so that the first transistor M3 is more uniformly affected by the heat from the first power transistor M1, and the threshold voltage of the two changes more consistently due to heat, thus ensuring that the constant current is more accurate.

[0063] In summary, the control circuit of the DC-DC power transistor according to the embodiments of this disclosure exhibits less change in charging current due to thermal radiation, and the constant current charging current changes less after long-term use or life aging tests.

[0064] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0065] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0066] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0067] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A control circuit for a DC-DC power transistor, characterized in that, include: Switching circuit, power transistor circuit, and output circuit. The switching circuit is configured to generate a first current signal and provide the first current signal to the power transistor circuit via a first node in a first operating state, and to generate a first switching signal and provide the first switching signal to the output circuit via a second node in a second operating state. The power transistor circuit is configured to generate a first mirror signal of the first current signal and provide the first mirror signal to the output circuit via the second node in the first operating state, and to generate a second switching signal and provide the second switching signal to the output circuit via the second node in the second operating state. The output circuit is configured to perform a pre-charge operation using the first mirror signal in the first operating state, and to output the first switch signal and the second switch signal via the signal output terminal in the second operating state, wherein the first switch signal and the second switch signal are synchronized. The switching circuit includes a first transistor, and the power transistor circuit includes a first power transistor. In the first operating state, the first power transistor and the first transistor form a current mirror relationship. In the second operating state, the first switching signal generated by the first transistor and the second switching signal generated by the first power transistor are synchronized.

2. The control circuit for the DC-DC power transistor according to claim 1, characterized in that, The power transistor circuit also includes: a DC-DC control module, a second power transistor, and a first inductor. The DC-DC control module has its input terminal coupled to a pulse width modulation (PWM) signal terminal, its first output terminal coupled to the control electrode of the first power transistor, and its second output terminal coupled to the control electrode of the second power transistor. The DC-DC control module is configured to drive the first power transistor and the second power transistor according to the PWM signal. The first terminal of the first power transistor is coupled to the second node, and the second terminal of the first power transistor is coupled to the first node; The first terminal of the second power transistor is coupled to the first node, and the second terminal of the second power transistor is coupled to the second voltage terminal; The first end of the first inductor is coupled to the first node, and the second end of the first inductor is coupled to the first voltage terminal.

3. The control circuit for the DC-DC power transistor according to claim 2, characterized in that, The switching circuit further includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a first current source. Wherein, the control electrode of the first transistor is coupled to the control electrode of the first power transistor, the first electrode of the first transistor is coupled to the second terminal of the second switch and the second terminal of the third switch, and the second electrode of the first transistor is coupled to the first terminal of the first switch, the second terminal of the fourth switch and the first terminal of the fifth switch; The second terminal of the first switch is coupled to the control electrode of the first transistor; The first terminal of the second switch is coupled to the second node; The first end of the third switch is coupled to the first node; The first end of the fourth switch is coupled to the first node; The second terminal of the fifth switch is coupled to the first terminal of the first current source; The second terminal of the first current source is coupled to the second voltage terminal.

4. The control circuit for the DC-DC power transistor according to claim 3, characterized in that, When in the first working state, the first, third, and fifth switches are closed simultaneously, and the second and fourth switches are open simultaneously; when in the second working state, the first, third, and fifth switches are open simultaneously, and the second and fourth switches are closed simultaneously.

5. The control circuit for the DC-DC power transistor according to claim 2, characterized in that, The output circuit includes: a first capacitor, Wherein, the first end of the first capacitor is coupled to the second node and the signal output terminal, and the second end of the first capacitor is coupled to the second voltage terminal.

6. The control circuit for the DC-DC power transistor according to claim 3, characterized in that, Both the first transistor and the first power transistor are PMOS transistors, and the second power transistor is an NMOS transistor.

7. The control circuit for the DC-DC power transistor according to claim 1, characterized in that, The power transistor circuit also includes: a DC-DC control module and a second power transistor. The DC-DC control module has its input terminal coupled to a pulse width modulation (PWM) signal terminal, its first output terminal coupled to the control electrode of the first power transistor, and its second output terminal coupled to the control electrode of the second power transistor. The DC-DC control module is configured to drive the first power transistor and the second power transistor according to the PWM signal. The first terminal of the first power transistor is coupled to the first node, and the second terminal of the first power transistor is coupled to the second node; The first terminal of the second power transistor is coupled to the second node, and the second terminal of the second power transistor is coupled to the second voltage terminal.

8. The control circuit for the DC-DC power transistor according to claim 7, characterized in that, The switching circuit further includes: a first switch, a second switch, a third switch, and a first current source. The control electrode of the first transistor is coupled to the control electrode of the first power transistor and the second terminal of the second switch; the first electrode of the first transistor is coupled to the first terminal of the first switch, the first terminal of the second switch and the second terminal of the third switch; and the second electrode of the first transistor is coupled to the second node. The second terminal of the first switch is coupled to the first terminal of the first current source; The first end of the third switch is coupled to the first node; The second end of the first current source is coupled to the first node.

9. The control circuit for the DC-DC power transistor according to claim 8, characterized in that, When in the first working state, the first and second switches are closed simultaneously, and the third switch is open; when in the second working state, the third switch is closed, and the first and second switches are open simultaneously.

10. The control circuit for the DC-DC power transistor according to claim 7, characterized in that, The output circuit includes: a first inductor and a first capacitor. Wherein, the first end of the first inductor is coupled to the second node, and the second end of the first inductor is coupled to the signal output terminal; The first end of the first capacitor is coupled to the signal output terminal, and the second end of the first capacitor is coupled to the second voltage terminal.

11. The control circuit for the DC-DC power transistor according to claim 8, characterized in that, The first transistor, the first power transistor, and the second power transistor are all NMOS transistors.

12. The control circuit for the DC-DC power transistor according to any one of claims 1 to 11, characterized in that, The first transistor is embedded in the middle of the first power transistor.

13. The control circuit for the DC-DC power transistor according to any one of claims 1 to 11, characterized in that, The first operating state is a constant current pre-charge state, and the second operating state is a DC-DC normal operating state.

14. The control circuit for the DC-DC power transistor according to claim 2 or 7, characterized in that, The DC-DC control module includes: a PWM control module, a first drive module, and a second drive module. The input terminal of the PWM control module is coupled to the input terminal of the DC-DC control module, the first output terminal of the PWM control module is coupled to the input terminal of the first drive module, the second output terminal of the PWM control module is coupled to the input terminal of the second drive module, and the PWM control module is configured to provide the PWM signal. The output terminal of the first drive module is coupled to the first output terminal of the DC-DC control module, and the first drive module is configured to drive the first power transistor according to the PWM signal. The output terminal of the second drive module is coupled to the second output terminal of the DC-DC control module, and the second drive module is configured to drive the second power transistor according to the PWM signal.

Images