A Fractional Sampling Phase-Locked Loop Based on Multi-Level Quantization Noise Compensation

Abstract

A fractional sampling phase-locked loop based on multi-stage quantization noise compensation provided by the present invention includes: a two-step quantization noise compensation circuit, which uses a combined compensation method of an N1-bit phase interpolator PI and an N2-bit digitally controlled switched capacitor array DCCA to perform two compensations on the quantization noise caused by the quantization error of the DSM in the fractional sampling phase-locked loop; wherein, the compensation of the N1-bit phase interpolator in the first-step quantization noise compensation circuit can reduce the quantization noise by 6*(N1 + 2) dB, and the compensation of the N2-bit capacitor array in the second-step quantization noise compensation circuit can further reduce the quantization noise by 6*N2 dB, greatly reducing the quantization noise and integer boundary spurs of the fractional phase-locked loop.

Description

Technical Field

[0001] The present invention belongs to the field of design of mixed-signal integrated circuits, and particularly relates to a fractional sampling phase-locked loop based on multi-stage quantization noise compensation. Background Art

[0002] For a phase-locked loop system, performance indicators such as phase noise, spurs, power consumption, and area are all crucial. The traditional phase-locked loop is a charge pump phase-locked loop. The charge pump phase-locked loop needs to increase power consumption and the area of the chip to optimize phase noise and clock jitter, so it is limited in practical use.

[0003] The existing sampling phase-locked loop uses a sampling phase detector (SPD) to convert the phase difference between the input reference signal and the feedback signal of the phase-locked loop into a voltage through a sample-and-hold method, and then compares the converted voltage to increase the in-band gain, thereby realizing the optimization of phase noise.

[0004] However, in the fractional mode of the existing sampling phase-locked loop, the linearity of the sampling phase detector SPD is worse than that of the frequency discriminator and phase detector of the traditional charge pump phase-locked loop. As a result, after the quantization noise of the DSM passes through the non-linear system, the high-frequency noise will alias to the low-frequency, resulting in higher integer boundary spurs and in-band phase noise at the output end of the phase-locked loop, reducing the performance of the phase-locked loop system. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a fractional sampling phase-locked loop based on multi-stage quantization noise compensation. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0006] A fractional sampling phase-locked loop based on multi-stage quantization noise compensation provided by the present invention includes a two-step quantization noise compensation circuit.

[0007] The first-step quantization noise compensation circuit is composed of an orthogonal frequency divider QDIV, a multi-stage cascaded frequency divider MMDIV, and an N1-bit phase interpolator PI connected in sequence.

[0008] Wherein, the control end of the multi-stage cascaded frequency divider MMDIV is connected to an interpolative sigma-delta modulator DSM, the control end of the N1-bit phase interpolator PI is connected to an accumulator ACC, the input end of the accumulator ACC is connected to an adder ADD, the input end of the interpolative sigma-delta modulator DSM is connected to the positive input end of the adder ADD, and the output end of the interpolative sigma-delta modulator DSM is connected to the negative input end of the adder ADD.

[0009] The second-step quantization noise compensation circuit is composed of a sampling phase detector SPD, two groups of N2-bit capacitor arrays DCCA, a transconductance amplifier GM, a low-pass filter LPF, and a voltage-controlled oscillator VCO connected in sequence.

[0010] Among them, the first - step quantization noise compensation circuit and the second - step quantization noise compensation circuit form a feedback loop. In the feedback loop, the input end of the sampling phase detector SPD is connected to the output end of the N1 - bit phase interpolator PI, the output end of the voltage - controlled oscillator VCO is connected to the input end of the quadrature frequency divider QDIV, and the control end of the N2 - bit capacitor array DCCA is connected to the output end of the accumulator ACC;

[0011] The first - step quantization noise compensation circuit reduces the quantization noise by reducing the sampling edge range generated by the quadrature frequency divider QDIV and feeds it back to the second - step quantization noise compensation circuit;

[0012] The second - step quantization noise compensation circuit further compensates the quantization noise through two groups of N2 - bit capacitor arrays DCCA.

[0013] Optionally, the first - step quantization noise compensation circuit reduces the quantization noise by reducing the sampling edge range generated by the quadrature frequency divider QDIV and feeds it back to the second - step quantization noise compensation circuit, including:

[0014] The quadrature frequency divider QDIV receives the sine - wave voltage signal input by the voltage - controlled oscillator VCO, performs quadrature frequency division on the sine - wave voltage signal, generates four quadrature frequency - divided voltage signals FQP, FQN, FIP, and FIN, and inputs them to the multi - stage cascaded frequency divider MMDIV;

[0015] The interpolation integral modulator DSM is used to receive the fractional division ratio n and generate a variable integer division ratio N according to the fractional division ratio n for the multi - stage cascaded frequency divider MMDIV;

[0016] The multi - stage cascaded frequency divider MMDIV is used to perform N - division on the four quadrature frequency - divided voltage signals FQP, FQN, FIP, and FIN respectively according to the variable integer division ratio N, and outputs signals F1, F2, F3, and F4 to the N1 - bit phase interpolator PI;

[0017] The N1 - bit phase interpolator PI is used to perform phase interpolation on the input signals F1, F2, F3, and F4 respectively. Under the control of the first N1 + 2 - bit digital code of the N1+N2 + 2 - bit output digital code KA<N1+N2 + 2> of the accumulator ACC, two voltage signals Fdiv1 and Fdiv2 that can generate multiple phases are obtained and fed back to the sampling phase detector SPD;

[0018] Among them, Fdiv1 and Fdiv2 differ by a quarter of the period of the quadrature frequency divider QDIV, and the number of phases of the voltage signal is positively correlated with the equal - division times of the phase interpolation.

[0019] Optionally, the second-step quantization noise compensation circuit further compensates for the quantization noise through two groups of N2-bit capacitor arrays DCCA, including:

[0020] Sampling phase detector SPD, used to obtain the input reference signal F ref The instantaneous phase errors of the voltage signal Fdiv1 and the voltage signal Fdiv2 are converted into voltage signals V1 and V2 with different amplitudes in a sampling and holding manner;

[0021] Two sets of capacitor arrays DCCA are used to output the digital code KA of the accumulator ACC.<N1+N2+2> Under the control of the last N2 bits of the digital code, the voltage signal V1 and the voltage signal V2 are compensated to obtain a stable DC voltage V3;

[0022] The transconductance amplifier GM is used to generate an output current I1 after inputting the DC voltage V3 and the external fixed voltage Vdc, and output it to the low-pass filter LPF to charge and discharge the low-pass filter LPF;

[0023] The low-pass filter LPF is used to filter the self-charged voltage and output the filtered voltage signal to the voltage-controlled oscillator VCO;

[0024] The voltage controlled oscillator VCO is used to control its own operating frequency according to the voltage signal VC, thereby outputting a sinusoidal wave voltage signal FVCO.

[0025] Optionally, each of the two capacitor arrays DCCA includes four capacitors, one end of each capacitor is connected to a power ground, and one end is connected to one end of two switches, wherein the other end of one switch is connected to a stable DC voltage V3, and the other end of the other switch is connected to the input voltage signal V1 or the voltage signal V2;

[0026] The voltage signals input to the two groups of capacitor arrays DCCA are different.

[0027] Beneficial effects of the present invention:

[0028] A fractional sampling phase-locked loop based on multi-stage quantization noise compensation provided by the present invention includes: a two-step quantization noise compensation circuit. The first-step quantization noise compensation circuit and the second-step quantization noise compensation circuit form a feedback loop. The first-step quantization noise compensation circuit reduces the quantization noise by reducing the sampling edge range generated by the quadrature frequency divider (QDIV), and feeds it back to the second-step quantization noise compensation circuit. The second-step quantization noise compensation circuit further compensates the quantization noise through two groups of N2-bit capacitor arrays (DCCA). The present invention uses a combined compensation method of an N1-bit phase interpolator PI and an N2-bit digitally controlled switched capacitor array DCCA to compensate the quantization noise caused by the quantization error of the DSM in the fractional sampling phase-locked loop twice. The compensation of the N1-bit phase interpolator in the first-step quantization noise compensation circuit can reduce the quantization noise by 6*(N1 + 2) dB, and the compensation of the N2-bit capacitor array in the second-step quantization noise compensation circuit can further reduce the quantization noise by 6*N2 dB, greatly reducing the quantization noise and integer boundary spurs of the fractional phase-locked loop.

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Description of the Drawings

[0030] Figure 1 is a schematic structural diagram of a fractional sampling phase-locked loop based on multi-stage quantization noise compensation provided by an embodiment of the present invention;

[0031] Figure 2 is a schematic diagram of input and output signals of an oscillator, a quadrature frequency divider, and a phase interpolator provided by an embodiment of the present invention;

[0032] Figure 3 is a schematic diagram of the compensation process of the first-step quantization noise compensation circuit provided by an embodiment of the present invention;

[0033] Figure 4 is a schematic structural diagram of two groups of N2-bit capacitor arrays (DCCA) provided by an embodiment of the present invention;

[0034] Figure 5 is a schematic diagram of the compensation process of the second-step quantization noise compensation circuit provided by an embodiment of the present invention.

[0035] Figure 6 is a schematic diagram of the compensation process of a fractional sampling phase-locked loop based on multi-stage quantization noise compensation provided by an embodiment of the present invention. Detailed Embodiments

[0036] The present invention will be further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0037] As Figure 1As shown in the figure, a fractional sampling phase-locked loop based on multi-stage quantization noise compensation provided by the present invention includes: a two-step quantization noise compensation circuit,

[0038] The first-step quantization noise compensation circuit is composed of a quadrature frequency divider QDIV, a multi-stage cascaded frequency divider MMDIV, and an N1-bit phase interpolator PI connected in sequence;

[0039] Among them, the control terminal of the multi-stage cascaded frequency divider MMDIV is connected to an interpolation integral modulator DSM; among them, the control terminal of the N1-bit phase interpolator PI is connected to an accumulator ACC, the input terminal of the accumulator ACC is connected to an adder ADD, the input terminal of the interpolation integral modulator DSM is connected to the positive input terminal of the adder ADD, and the output terminal of the interpolation integral modulator DSM is connected to the negative input terminal of the adder ADD;

[0040] The second-step quantization noise compensation circuit is composed of a sampling phase detector SPD, two groups of N2-bit capacitor arrays DCCA, a transconductance amplifier GM, a low-pass filter LPF, and a voltage-controlled oscillator VCO connected in sequence;

[0041] Among them, the first-step quantization noise compensation circuit and the second-step quantization noise compensation circuit form a feedback loop. In the feedback loop, the input terminal of the sampling phase detector SPD is connected to the output terminal of the N1-bit phase interpolator PI, and the output terminal of the voltage-controlled oscillator VCO is connected to the input terminal of the quadrature frequency divider QDIV; the control terminals of the two groups of N2-bit capacitor arrays DCCA are connected to the output terminal of the accumulator ACC;

[0042] The first-step quantization noise compensation circuit reduces the quantization noise by reducing the sampling edge range generated by the quadrature frequency divider QDIV, and feeds it back to the second-step quantization noise compensation circuit;

[0043] The first-step quantization noise compensation circuit reduces the quantization noise by reducing the sampling edge range generated by the quadrature frequency divider QDIV, and feeding it back to the second-step quantization noise compensation circuit includes:

[0044] The quadrature frequency divider QDIV receives the sine wave voltage signal input by the voltage-controlled oscillator VCO, performs quadrature frequency division on the sine wave voltage signal, and generates four orthogonal frequency-divided voltage signals FQP, FQN, FIP, and FIN and inputs them to the multi-stage cascaded frequency divider MMDIV;

[0045] The interpolation integral modulator DSM is used to receive the fractional division ratio n and generate a variable integer division ratio N to the multi-stage cascaded frequency divider MMDIV according to the fractional division ratio n;

[0046] Among them, the input end of the interpolation accumulator ACC is connected to an adder ADD, and the output end is connected to an N1-bit phase interpolator PI and two groups of N2-bit capacitor arrays DCCA;

[0047] The adder ADD is used to calculate the difference between the fractional division ratio n of the input signal of the DSM and the integer division ratio N of the output signal to obtain the quantization error M.

[0048] The accumulator ACC is used to accumulate the quantization error M generated by the adder ADD and output an N1+N2+2-bit digital control code KA<N1+N2+2>. Among them, the first N1+2-bit digital control code is used to control the phase output by the N1-bit phase interpolator PI, and the last N2-bit digital control code is used to control the opening or closing of the switches in the N2-bit capacitor array DCCA;

[0049] It should be noted that: the interpolation integral modulator DSM controls the division ratio N of the multi-stage cascaded frequency divider MMDIV to be converted into different integer values in different reference clock cycles, and realizes the fractional division function by taking the average value of different integer division ratios N in multiple reference clock cycles.

[0050] The multi-stage cascaded frequency divider MMDIV is used to perform N-division on four orthogonal two-frequency voltage signals FQP, FQN, FIP, and FIN respectively according to the changing integer division ratio N, and output signals F1, F2, F3, and F4 to the N1-bit phase interpolator PI;

[0051] The N1-bit phase interpolator PI is used to perform phase interpolation on the input signals F1, F2, F3, and F4 respectively to obtain two voltage signals Fdiv1 and Fdiv2 that can generate multiple phases and feedback them to the sampling phase detector SPD;

[0052] Among them, Fdiv1 and Fdiv2 differ by a quarter of the period of the quadrature frequency divider QDIV, and the number of phases of the voltage signal is positively correlated with the equal division times of the phase interpolation.

[0053] Exemplarily: the quadrature frequency divider QDIV performs quadrature processing on the signal output by the oscillator to obtain signals of 0°, 90°, 180°, and 270°. Then the phase interpolator PI performs phase interpolation on one of the four groups of 0° and 90°, 90° and 180°, 180° and 270°, 270° and 0°, so that the output signal can arbitrarily output a certain phase between the pair of input signals.

[0054] Such as Figure 2The figure shows a schematic diagram of the input and output signals of an oscillator, a quadrature frequency divider, and a phase interpolator. The quadrature frequency divider performs quadrature processing on the oscillator signal to obtain signals at 0°, 90°, 180°, and 270°; the phase interpolator performs phase interpolation on the 0° and 90° signals according to the binary control code to obtain five phase signals at 0°, 22.5°, 45°, 67.5°, and 90°. Refer to Figure 3 , the quadrature frequency divider QDIV and the N1-bit phase interpolator are used to convert a voltage-controlled oscillator period T VCO to T VCO / 2 N1+2 , and the output of the PI is used as the sampling signal of the sampling phase detector SPD to sample the input reference signal F ref , so as to sample the feedback signal F div1 , F div2 and the input reference signal F ref to compensate for the instantaneous phase error between them, thereby realizing the compensation of quantization noise, and the quantization noise is reduced by 6*(N1 + 2) dB.

[0055] In the second step, the quantization noise compensation circuit further compensates the quantization noise through two groups of N2-bit capacitor arrays DCCA.

[0056] The second-step quantization noise compensation circuit further compensating the quantization noise through two groups of N2-bit capacitor arrays DCCA includes:

[0057] A sampling phase detector SPD, which is used to separately obtain the instantaneous phase errors between the input reference signal F ref and the voltage signals Fdiv1 and Fdiv2, and convert the two obtained instantaneous phase errors into voltage signals V1 and V2 with different amplitudes in a sample-and-hold manner;

[0058] It should be noted that: due to the different division ratios N within different reference clock cycles, there is a continuously changing instantaneous phase error between the signals Fdiv1, Fdiv2 and the input reference signal Fref, which is equivalent to the quantization error generated by the quantizer, and quantization noise is introduced at the output end of the multi-stage cascaded frequency divider MMDIV.

[0059] Two groups of capacitor arrays DCCA, which are used to perform voltage compensation on the voltage signals V1 and V2 under the control of the last N2-bit digital codes of the output digital code KA<N1 + N2 + 2> of the accumulator ACC to obtain a relatively stable DC voltage V3;

[0060] A transconductance amplifier GM, which is used to generate an output current I1 and output it to the low-pass filter LPF after inputting the DC voltage V3 and the external fixed voltage Vdc, so as to charge and discharge the low-pass filter LPF;

[0061] A low-pass filter LPF is used to filter the voltage for self-charging and output the filtered voltage signal to a voltage-controlled oscillator VCO.

[0062] A voltage-controlled oscillator VCO is used to control its own operating frequency according to the voltage signal VC, so as to output a sine wave voltage signal FVCO.

[0063] It should be noted that: the phase-locked loop of the present invention works in a cycle according to the process of the two-step quantization noise compensation circuit through negative feedback until the phase of the output voltage FVCO of the voltage-controlled oscillator VCO is equal to the phase of the input reference signal Fref, and the function of phase locking of the phase-locked loop is completed.

[0064] Reference Figure 4 , each of the two capacitor arrays DCCA in the present invention includes four capacitors. One end of each capacitor is grounded, and the other end is connected to one end of two switches. One of the switches has the other end tending to a stable DC voltage V3, and the other switch has the other end connected to the input voltage signal V1 or the voltage signal V2;

[0065] Among them, the voltage signals input by the two capacitor arrays DCCA are different.

[0066] The two capacitor arrays DCCA of the present invention are numerically controlled switched-capacitor arrays DCCA capacitors, and the compensation principle is as follows:

[0067] Exemplarily, taking a 3-bit numerically controlled switched-capacitor array DCCA as an example, where the capacitance C of DCCA1 A0 : C A1 : C A2 : C A3 = 1:1:2:4; and the capacitance C of DCCA2 B0 : C B1 : C B2 : C B3 = 1:1:2:4.

[0068] (1) In the initial sampling stage, the sampling phase detector transmits the two collected voltages V1 and V2 to DCCA1 and DCCA2;

[0069] (2) In the compensation output stage, DCCA1 and DCCA2 open and close KA<0:3> and KB<0:3> according to the binary code output by the DSM to obtain the voltage V3;

[0070] In the initial stage, the numerically controlled switched-capacitor arrays DCCA1 and DCCA2 are charged to V1 and V2 respectively; the voltages of the capacitors C A0 , C A1 , C A2 , C A3 are V1; at this time, the voltage of the capacitor CB0 , C B1 , C B2 , C B3 has a voltage of V2.

[0071] Compensation stage:

[0072] When the binary code is 000, KB<0>, KB<1>, KB<2>, KB<3> are open; KA<0>, KA<1>, KA<2>, KA<3> are closed. The new capacitor array formed by combining two numerically controlled switched-capacitor arrays DCCA has a voltage magnitude of V3 = (0*V1 + 8*V2) / 8;

[0073] When the binary code is 001, KB<0>, KB<2>, KB<3> are open, KB<1> is closed; KA<0>, KA<2>, KA<3> are closed, KA<1> is open. The new capacitor array formed by combining two numerically controlled switched-capacitor arrays DCCA has a voltage magnitude of V3 = (1*V1 + 7*V2) / 8;

[0074] When the binary code is 010, KB<0>, KB<1>, KB<3> are open, KB<2> is closed; KA<0>, KA<1>, KA<3> are closed, KA<2> is open. The new capacitor array formed by combining two numerically controlled switched-capacitor arrays DCCA has a voltage magnitude of V3 = (2*V1 + 6*V2) / 8;

[0075] When the binary code is 011, KB<0>, KB<3> are open, KB<1>, KB<2> are closed; KA<0>, KA<3> are closed, KA<1>, KA<2> are open. The new capacitor array formed by combining two numerically controlled switched-capacitor arrays DCCA has a voltage magnitude of V3 = (3*V1 + 5*V2) / 8;

[0076] When the binary code is 111, KB<0> is open, KB<1>, KB<2>, KB<3> are closed; KA<0> is closed, KA<1>, KA<2>, KA<3> are open. The new capacitor array formed by combining two numerically controlled switched-capacitor arrays DCCA has a voltage magnitude of V3 = (7*V1 + 1*V2) / 8;

[0077] Reference Figure 5 , the N2-bit numerically controlled switched-capacitor array DCCA adjusts the change in the output voltage of the sampler by adjusting charge sharing, so as to realize the conversion of the output T of the N1-bit phase interpolator PI VCO / 2 N1+2 to T VCO / 2 N1+N2+2, and compensate for the instantaneous phase error, thereby realizing the compensation of quantization noise, and the quantization noise is further reduced by 6*N2 dB.

[0078] Reference Figure 6 , the present invention adopts a method combining an orthogonal frequency divider QDIV, a phase interpolator PI and a digitally controlled switched capacitor array DCCA capacitor compensation to reduce quantization noise in two steps. In the first step, by using the orthogonal frequency divider QDIV and the N1-bit phase interpolator PI, the sampling edge range generated by the frequency divider is reduced from Tvco to Tvco / 2 N1+2 , thereby theoretically reducing the quantization noise by 6*(N1 + 2) dB. In the second step, through the N2-bit digitally controlled switched capacitor array, the quantization noise is further compensated, and the quantization noise is reduced by 6*N2 dB. By the method of two-step quantization compensation, the quantization noise generated by the DSM is greatly reduced, thereby obtaining very small integer boundary spurs.

[0079] A fractional sampling phase-locked loop based on multi-stage quantization noise compensation provided by the present invention includes: a two-step quantization noise compensation circuit, the first-step quantization noise compensation circuit and the second-step quantization noise compensation circuit form a feedback loop, and the first-step quantization noise compensation circuit reduces the quantization noise by reducing the sampling edge range generated by the orthogonal frequency divider QDIV and feeds it back to the second-step quantization noise compensation circuit. The second-step quantization noise compensation circuit further compensates the quantization noise through two groups of n-bit capacitor arrays DCCA. The present invention uses the combined compensation method of the N1-bit phase interpolator PI and the N2-bit digitally controlled switched capacitor array DCCA to compensate the quantization noise caused by the quantization error of the DSM in the fractional sampling phase-locked loop twice; the N1-bit phase interpolator compensation of the first-step quantization noise compensation circuit can reduce the quantization noise by 6*(N1 + 2) dB, and the N2-bit capacitor array compensation of the second-step quantization noise compensation circuit can further reduce the quantization noise by 6*N2 dB, greatly reducing the quantization noise and integer boundary spurs of the fractional phase-locked loop.

[0080] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0081] Although the present application has been described in connection with various embodiments, those skilled in the art will understand and realize other variations of the disclosed embodiments by viewing the accompanying drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and the indefinite article "a" or "an" does not exclude a plurality.

[0082] The above is a further detailed description of the present invention in connection with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A fractional sampling phase-locked loop based on multi-level quantization noise compensation, characterized in that Including: A two-step quantization noise compensation circuit The first-step quantization noise compensation circuit is composed of a quadrature divider (QDIV), a multi-stage cascaded divider (MMDIV), and an N1-bit phase interpolator (PI) connected in sequence Among them, the control terminal of the multi-stage cascaded divider (MMDIV) is connected to an interpolative sigma-delta modulator (DSM), the control terminal of the N1-bit phase interpolator (PI) is connected to an accumulator (ACC), the input terminal of the accumulator (ACC) is connected to an adder (ADD), the input terminal of the interpolative sigma-delta modulator (DSM) is connected to the positive input terminal of the adder (ADD), and the output terminal of the interpolative sigma-delta modulator (DSM) is connected to the negative input terminal of the adder (ADD); The second-step quantization noise compensation circuit is composed of a sampling phase detector (SPD), two groups of N2-bit capacitor arrays (DCCA), a transconductance amplifier (GM), a low-pass filter (LPF), and a voltage-controlled oscillator (VCO) connected in sequence Among them, the first-step quantization noise compensation circuit and the second-step quantization noise compensation circuit form a feedback loop. In the feedback loop, the input terminal of the sampling phase detector (SPD) is connected to the output terminal of the N1-bit phase interpolator (PI), the output terminal of the voltage-controlled oscillator (VCO) is connected to the input terminal of the quadrature divider (QDIV), and the control terminal of the N2-bit capacitor array (DCCA) is connected to the output terminal of the accumulator (ACC); The first-step quantization noise compensation circuit reduces the quantization noise by reducing the sampling edge range generated by the quadrature divider (QDIV), and feeds it back to the second-step quantization noise compensation circuit The second-step quantization noise compensation circuit further compensates the quantization noise through two groups of N2-bit capacitor arrays (DCCA); The first-step quantization noise compensation circuit reduces the quantization noise by reducing the sampling edge range generated by the quadrature divider (QDIV), and feeding it back to the second-step quantization noise compensation circuit includes: The quadrature divider (QDIV) receives the sine wave voltage signal input by the voltage-controlled oscillator (VCO), performs quadrature division by two on the sine wave voltage signal, and generates four orthogonal division-by-two voltage signals FQP, FQN, FIP, and FIN and inputs them to the multi-stage cascaded divider (MMDIV); The interpolative sigma-delta modulator (DSM) is used to receive the fractional division ratio n and generate a variable integer division ratio N for the multi-stage cascaded divider (MMDIV) according to the fractional division ratio n; The multi-stage cascaded divider (MMDIV) is used to perform N division on the four orthogonal division-by-two voltage signals FQP, FQN, FIP, and FIN respectively according to the variable integer division ratio N, and obtain signals F1, F2, F3, and F4 and output them to the N1-bit phase interpolator (PI); The N1-bit phase interpolator (PI) is used to perform phase interpolation on the input signals F1, F2, F3, and F4 respectively. Under the control of the first N1+2 bits of the output digital code KA<N1+N2+2> with N1+N2+2 bits of the accumulator (ACC), two voltage signals Fdiv1 and Fdiv2 capable of generating multiple phases are obtained and fed back to the sampling phase detector (SPD); Among them, Fdiv1 and Fdiv2 differ by a quarter of the period of the quadrature divider (QDIV), and the number of phases of the voltage signal is positively correlated with the equal division times of the phase interpolation.

2. The fractional sampling phase-locked loop based on multi-stage quantization noise compensation according to claim 1, wherein The second-step quantization noise compensation circuit further compensates the quantization noise through two groups of N2-bit capacitor arrays (DCCA), including: The sampling phase detector (SPD) is used to separately obtain the instantaneous phase errors between the input reference signal F ref and the voltage signals Fdiv1 and Fdiv2, and convert the two obtained instantaneous phase errors into voltage signals V1 and V2 with different amplitudes in a sample-and-hold manner; The two groups of capacitor arrays (DCCA) are used to perform voltage compensation on the voltage signals V1 and V2 under the control of the last N2 bits of the output digital code KA<N1+N2+2> of the accumulator (ACC), and a stable DC voltage V3 is obtained; The transconductance amplifier (GM) is used to generate an output current I1 and output it to the low-pass filter (LPF) after receiving the input DC voltage V3 and the external fixed voltage Vdc, so as to charge and discharge the low-pass filter (LPF); The low-pass filter (LPF) is used to filter the voltage of its own charge and output the filtered voltage signal to the voltage-controlled oscillator (VCO); The voltage-controlled oscillator (VCO) is used to control its own operating frequency according to the voltage signal VC, and thus output a sine wave voltage signal FVCO.

3. The fractional sampling phase-locked loop based on multi-stage quantization noise compensation according to claim 2, wherein, Each of the two groups of capacitor arrays (DCCA) includes four capacitors. One end of each capacitor is connected to the power ground, and the other end is connected to one end of two switches. One of the switches has the other end connected to the stable DC voltage V3, and the other switch has the other end connected to the input voltage signal V1 or the voltage signal V2; Among them, the voltage signals input by the two groups of capacitor arrays (DCCA) are different.

Images