Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: performing modification treatment on the surface of the covering layer to form a modified layer; forming a first opening and a second opening, wherein the first opening is located in the second dielectric layer, the second etch stop layer, the first dielectric layer and the first etch stop layer, and the first opening exposes the modified layer, and the second opening is located in the second dielectric layer and the second etch stop layer, and the second opening exposes the top surface of the conductive structure, so that the growth rate of the material of the first conductive layer on the surface of the modified layer is higher than the growth rate of the material of the first conductive layer on the surface of the covering layer, thereby reducing the situation where the first opening on the modified layer is closed in advance before being filled with the material of the first conductive layer, thereby improving the performance of the formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] As the integration density of semiconductor integrated circuits continues to increase and the feature size of semiconductor devices continues to shrink, various practical and fundamental limitations and technical challenges begin to emerge, and further reduction of device size is becoming increasingly difficult.

[0003] The rapid development of integrated circuit technology has put forward higher requirements for metal interconnection technology. Traditional aluminum metal interconnection technology can no longer meet the needs of the development of modern interconnection technology. Damascus structure copper metal interconnection technology has become one of the key development directions of interconnection technology. However, after the characteristic line width of integrated circuits has been reduced to a few nanometers, copper interconnection technology is also facing huge challenges. With the increasing number of metal wiring layers, the resistance of metal wires and the parasitic capacitance between them are increasingly becoming the limiting factors affecting the speed of devices.

[0004] Therefore, the existing metal interconnection process needs to be further improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a base, a gate structure located on the substrate and an interlayer dielectric layer located on the substrate, the interlayer dielectric layer is also located on the sidewall of the gate structure and exposes the top surface of the gate structure, the covering layer is located on the top surface of the gate structure; a covering layer located on the top surface of the gate structure, the material of the covering layer comprises metal; a modified layer located on the surface of the covering layer; a first etch stop layer located on the surface of the substrate and the modified layer; a first dielectric layer located on the surface of the first etch stop layer; a conductive structure located in the first dielectric layer, the first etch stop layer and the interlayer dielectric layer, The top surface of the conductive structure is flush with the top surface of the first dielectric layer; a second etch stop layer located on the first dielectric layer and the surface of the conductive structure; a second dielectric layer located on the second etch stop layer; a first opening located in the second dielectric layer, the second etch stop layer, the first dielectric layer and the first etch stop layer, and the first opening exposes the modified layer, a second opening located in the second dielectric layer and the second etch stop layer, and the second opening exposes the top surface of the conductive structure; a first conductive layer located in the first opening, a second conductive layer located in the second opening, and the top surfaces of the first conductive layer and the second conductive layer are flush with the top surface of the second dielectric layer.

[0007] Optionally, the substrate further includes a source-drain layer located in the substrate on both sides of the gate structure, and the conductive structure is located on the surface of the source-drain layer.

[0008] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a base, a gate structure located on the substrate and an interlayer dielectric layer located on the substrate, the interlayer dielectric layer is also located on the sidewall of the gate structure and exposes the top surface of the gate structure, the covering layer is located on the top surface of the gate structure; forming a covering layer on the top surface of the gate structure, the material of the covering layer comprising metal; modifying the surface of the covering layer to form a modified layer; forming a first etch stop layer on the surface of the substrate and the modified layer; forming a first dielectric layer on the surface of the first etch stop layer; forming a conductive structure in the first dielectric layer, the first etch stop layer and the interlayer dielectric layer, the top surface of the conductive structure is flush with the top surface of the first dielectric layer; A second etch stop layer is formed on the surface of the first dielectric layer and the conductive structure; a second dielectric layer is formed on the surface of the second etch stop layer; a first opening and a second opening are formed, the first opening is located in the second dielectric layer, the second etch stop layer, the first dielectric layer and the first etch stop layer, and the first opening exposes the modified layer, the second opening is located in the second dielectric layer and the second etch stop layer, and the second opening exposes the top surface of the conductive structure; a first conductive layer is formed in the first opening, and a second conductive layer is formed in the second opening, and the top surfaces of the first conductive layer and the second conductive layer are flush with the top surface of the second dielectric layer, and the growth rate of the material of the first conductive layer on the surface of the modified layer is higher than the growth rate of the material of the first conductive layer on the surface of the covering layer.

[0009] Optionally, the substrate further includes a source-drain layer located in the base at both sides of the gate structure; and the conductive structure is located on the surface of the source-drain layer.

[0010] Optionally, the method further includes: after forming the first opening and before forming the first conductive layer, performing surface treatment on the modified layer exposed by the first opening so that the surface of the modified layer has second ions.

[0011] Optionally, before forming the modified layer, the covering layer contains a first ion, the material of the covering layer includes a metal ion, a first chemical bond is formed between the first ion and the metal ion; a second chemical bond is formed between the second ion and the metal ion, and the bond energy of the second chemical bond is lower than the bond energy of the first chemical bond.

[0012] Optionally, the first ions include chloride ions; and the second ions include fluoride ions.

[0013] Optionally, the process parameters of the surface treatment include: using fluorine-containing gas and a treatment temperature range of 300 degrees Celsius to 400 degrees Celsius.

[0014] Optionally, the fluorine-containing gas includes a combination of one or more of fluorine gas, hydrogen fluoride, and tungsten hexafluoride.

[0015] Optionally, the modification process includes a plasma treatment process; the process parameters of the plasma treatment process include: the reaction gas includes hydrogen.

[0016] Optionally, the process for forming the covering layer includes a selective atomic layer deposition process.

[0017] Optionally, the process parameters of the atomic layer deposition process include: the reaction gas includes tungsten chloride and hydrogen, and the reaction temperature ranges from 400 degrees Celsius to 500 degrees Celsius.

[0018] Optionally, the formation process of the first conductive layer and the second conductive layer includes a selective deposition process.

[0019] Optionally, process parameters of the selective deposition process include: the reaction gas includes tungsten hexafluoride and hydrogen, and the reaction temperature ranges from 300 degrees Celsius to 400 degrees Celsius.

[0020] Optionally, the method for forming the first conductive layer and the second conductive layer includes: depositing a conductive material layer in the first opening and the second opening until the first opening and the second opening are filled; planarizing the conductive material layer until the second dielectric layer is exposed; and a growth rate of the conductive material layer in the first opening is higher than a growth rate in the second opening.

[0021] Optionally, the conductive material layer includes tungsten.

[0022] Optionally, the material of the conductive structure includes cobalt.

[0023] Optionally, the metal includes tungsten.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the surface of the covering layer is modified to form a modified layer, a first conductive layer is formed in the first opening, and a second conductive layer is formed in the second opening, and the growth rate of the material of the first conductive layer on the surface of the modified layer is higher than the growth rate of the material of the first conductive layer on the surface of the covering layer, so as to reduce the difference between the growth rate of the material of the first conductive layer in the first opening on the surface of the modified layer and the growth rate of the material of the second conductive layer in the second opening on the surface of the conductive structure, thereby reducing the situation where the first opening on the modified layer is closed prematurely before being filled, thereby improving the performance of the formed semiconductor structure.

[0026] Furthermore, before forming the modified layer, the covering layer has a first ion, the material of the covering layer includes a metal ion, a first chemical bond is formed between the first ion and the metal ion; a second chemical bond is formed between the second ion and the metal ion, the bond energy of the second chemical bond is lower than the bond energy of the first chemical bond, and the second chemical bond is easier to break than the first chemical bond, thereby increasing the reaction rate of forming a first conductive layer on the surface of the modified layer.

[0027] Furthermore, the material of the covering layer includes tungsten, and the surface treatment is used to form a tungsten-fluorine bond in the modified layer. The existence of the tungsten-fluorine bond provides preparation for the formation of tungsten material, shortens the time for adsorbing tungsten hexafluoride gas during the formation process of the first conductive layer, and improves the growth rate of tungsten material formed on the surface of the modified layer, thereby reducing the situation where the first opening on the modified layer is prematurely closed before being filled with tungsten material, thereby improving the performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 5 It is a cross-sectional schematic diagram of the formation process of a semiconductor structure;

[0029] Figures 6 to 12 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0030] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0031] As described in the background art, the performance of semiconductor structures formed by the existing metal interconnection process needs to be improved. Now, a method for forming a semiconductor structure is described and analyzed.

[0032] Figures 1 to 5 It is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0033] Please refer to Figure 1 A substrate 101 is provided, and a gate structure is provided on the substrate 101, wherein the gate structure includes a metal gate 101 and a gate dielectric layer 102, and sidewalls 103 are provided on the sidewalls of the gate structure, and source and drain regions 104 are provided in the substrate 101 on both sides of the sidewalls 103, and an interlayer dielectric layer 105 is provided on the substrate 100, and the interlayer dielectric layer 105 is located on the sidewalls of the sidewalls 103 and exposes the top surface of the gate structure.

[0034] Please refer to Figure 2, forming a capping layer 106 on the surface of the metal gate 101; forming a first etch stop layer 108 on the interlayer dielectric layer 105, the surface of the gate structure and the top of the sidewall 103; and forming a first dielectric layer 107 on the surface of the first etch stop layer 108.

[0035] Please refer to Figure 3 A first opening (not shown in the figure) is formed in the first dielectric layer 107, the first etch stop layer 108 and the interlayer dielectric layer 105, wherein the first opening exposes the source and drain regions 104; and a conductive structure 109 is formed in the first opening.

[0036] Please refer to Figure 4 , forming a second etch stop layer 110 on the surface of the conductive structure 109 and the first dielectric layer 107; forming a second dielectric layer 111 on the surface of the second etch stop layer 110; forming a second opening 112 in the second dielectric layer 111, the second etch stop layer 110, the first dielectric layer 107 and the first etch stop layer 108, the second opening 112 exposing the top surface of the covering layer 106; forming a third opening 113 in the second dielectric layer 111 and the second etch stop layer 110, the third opening 113 exposing the top surface of the conductive structure 109.

[0037] Please refer to Figure 5 , a metal layer 114 is formed in the second opening 112 and the third opening 113 .

[0038] The above method is used in the metal interconnection process. The material of the capping layer 106 is tungsten, which is formed by an atomic layer deposition (ALD) process. The formed metal tungsten has good selectivity on the surface of the metal gate 101 and is conducive to forming a uniform and dense capping layer 106. The formation process of the atomic layer deposition process does not contain fluorine ions, avoiding the adverse effects of fluorine ions on the work function layer of the gate structure, but the deposition rate is slow. The material of the conductive structure 109 is cobalt. The material of the metal layer 114 is also tungsten. Since the chemical vapor deposition (CVD) process has a good step coverage rate and is relatively time-consuming compared to the atomic layer deposition process, the metal layer 114 is formed by a chemical vapor deposition process.

[0039] However, since the atomic layer deposition process uses tungsten chloride (such as WCl3) and hydrogen to react, a large number of tungsten-chlorine bonds are formed in the covering layer 106. In the atomic layer deposition process, the reaction temperature of the reaction of tungsten chloride and hydrogen is 460 degrees Celsius. In the process of forming the metal layer 114 using the chemical vapor deposition process, the metal tungsten selectively grows on the surface of the metal material, the reaction gas includes tungsten hexafluoride and hydrogen, and the reaction temperature is lower than 400 degrees Celsius. Under the condition of less than 400 degrees Celsius, the large number of tungsten-chlorine bonds in the covering layer 106 are more stable than the tungsten-fluorine bonds in the reaction gas tungsten hexafluoride. The presence of tungsten-chlorine bonds makes it difficult to form a tungsten material film in the chemical vapor deposition process, resulting in the growth rate of the tungsten material on the surface of the covering layer 106 being much lower than the growth rate of the tungsten material on the surface of the conductive structure 109. In addition, the depth of the second opening 112 is greater than the depth of the third opening 113, which makes it more likely that after the three openings 113 are filled with tungsten material, the second opening 112 is not yet filled with tungsten material. After filling the third opening 113, the tungsten material continues to grow and may cover the surface of the second opening 112, causing the second opening 112 to be closed prematurely, thereby causing defects such as holes in the metal layer 114 formed in the second opening 112, affecting the conductive properties of the metal layer 114 and reducing the performance of the formed semiconductor structure.

[0040] In order to solve the above problems, in a method for forming a semiconductor structure provided by the present invention, the surface of the covering layer is modified to form a modified layer, a first conductive layer is formed in the first opening, and a second conductive layer is formed in the second opening, and the growth rate of the material of the first conductive layer on the surface of the modified layer is higher than the growth rate of the material of the first conductive layer on the surface of the covering layer, so as to reduce the difference between the growth rate of the material of the first conductive layer in the first opening on the surface of the modified layer and the growth rate of the material of the second conductive layer in the second opening on the surface of the conductive structure, thereby reducing the situation where the first opening on the modified layer is closed prematurely before being filled, thereby improving the performance of the formed semiconductor structure.

[0041] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figures 6 to 12 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0043] Please refer to Figure 6, providing a substrate, the substrate comprising a base 201, a gate structure located on the base 201 and an interlayer dielectric layer 202 located on the base 201, the interlayer dielectric layer 202 is also located on the sidewall of the gate structure and exposes the top surface of the gate structure.

[0044] The gate structure includes a gate layer 203 and a sidewall spacer 204 located on a sidewall of the gate layer 203 .

[0045] The material of the gate layer 203 includes metal. In this embodiment, the material of the metal is aluminum.

[0046] The method for forming the gate structure includes: forming a dummy gate (not marked in the figure) on the substrate 201; forming the sidewall 204 on the sidewall of the dummy gate; forming an interlayer dielectric layer 202 on the surface of the substrate 201, wherein the interlayer dielectric layer 202 exposes the top surface of the dummy gate; etching and removing the dummy gate, forming a groove (not marked in the figure) in the interlayer dielectric layer 202; and forming the gate layer 203 in the groove.

[0047] In this embodiment, after the groove is formed and before the gate layer 203 is formed, a gate dielectric layer 205 is formed on the sidewall and bottom of the groove. The material of the gate dielectric layer 205 includes a high-K dielectric material.

[0048] In this embodiment, the gate structure further includes a work function layer (not marked in the figure) located between the gate dielectric layer 205 and the gate layer 203 .

[0049] In this embodiment, the substrate 200 further includes a source-drain layer 206 located in the base 201 on both sides of the gate structure.

[0050] Please refer to Figure 7 , forming a covering layer 207 on the top surface of the gate structure, wherein the material of the covering layer 207 includes metal; and performing modification treatment on the surface of the covering layer 207 to form a modified layer 208.

[0051] In this embodiment, specifically, the capping layer 207 is located on the top surface of the gate layer 203. The capping layer 207 is used to block ions from diffusing into the gate layer 203, so as to maintain the performance of the formed device, such as the threshold voltage.

[0052] The metal includes tungsten. In this embodiment, the metal is tungsten.

[0053] The formation process of the capping layer 207 includes a selective atomic layer deposition process.

[0054] In this embodiment, the process parameters of the atomic layer deposition process include: the reaction gas includes tungsten chloride and hydrogen, and the reaction temperature ranges from 400 degrees Celsius to 500 degrees Celsius. Tungsten chloride and hydrogen react to form tungsten. The selective atomic layer deposition process enables the tungsten material to have good selectivity on the surface of the gate layer 203, and is conducive to forming a uniform and dense material film. The formation process of the capping layer 207 does not contain fluorine ions, avoiding the adverse effects of fluorine ions on the work function layer of the gate structure, but is limited by the atomic layer deposition process, and the deposition rate is slow.

[0055] Before forming the modified layer 208 , the cover layer 207 has first ions in it, the material of the cover layer 207 includes metal ions, and a first chemical bond is formed between the first ions and the metal ions.

[0056] The first ion includes a chloride ion. In this embodiment, the cover layer 207 is formed by reacting tungsten chloride and hydrogen, and chloride ions are inevitably introduced into the cover layer 207, and the first ion is a chloride ion. In addition, the material of the cover layer 207 is tungsten ions, and the first chemical bond formed between the chloride ions and the tungsten ions is a tungsten-chlorine bond. The tungsten-chlorine bond is not easy to break compared to the tungsten-fluorine bond, so that when tungsten hexafluoride and hydrogen are reacted to form a tungsten material on the surface of the cover layer 207, the growth of the tungsten material becomes difficult due to the presence of the tungsten-chlorine bond.

[0057] The modification process includes a plasma treatment process; the process parameters of the plasma treatment process include: the reaction gas includes hydrogen. The modification process is used to remove the first ions.

[0058] Subsequently, a first conductive layer is formed in the first opening, and the modification treatment is used to make the growth rate of the material of the first conductive layer on the surface of the modified layer higher than the growth rate of the material of the first conductive layer on the surface of the covering layer, so as to reduce the difference between the growth rate of the material of the first conductive layer in the first opening on the surface of the modified layer and the growth rate of the material of the second conductive layer in the second opening on the surface of the conductive structure, thereby reducing the situation where the first opening on the modified layer is closed in advance before being filled, thereby improving the performance of the formed semiconductor structure. Specifically, in this embodiment, the modification treatment process is used to remove chloride ions in the material of the covering layer 207, that is, to remove tungsten-chlorine bonds. The modification treatment process makes it relatively easy to grow tungsten material on the surface of the covering layer 207 later.

[0059] Please refer to Figure 8 , forming a first etch stop layer 209 on the surface of the substrate and the modified layer 208 ; and forming a first dielectric layer 210 on the surface of the first etch stop layer 209 .

[0060] The material of the first dielectric layer 210 is a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0061] When the first opening is subsequently formed, the first etch stop layer 209 is used to reduce etching damage to the modified layer 208 .

[0062] Please refer to Fig. 9 A conductive structure 211 is formed in the first dielectric layer 210 , the first etch stop layer 209 and the interlayer dielectric layer 202 , and a top surface of the conductive structure 211 is flush with a top surface of the first dielectric layer 210 .

[0063] In this embodiment, the conductive structure 211 is located on the surface of the source / drain layer 206 .

[0064] The method for forming the conductive structure 211 includes: forming a first patterned layer (not marked in the figure) on the surface of the first dielectric layer 210, wherein the first patterned layer exposes a portion of the first dielectric layer 210; using the first patterned layer as a mask, etching the first dielectric layer 210, the first etch stop layer 209, and the interlayer dielectric layer 202 until the surface of the source / drain layer 206 is exposed; forming a third opening (not marked in the figure) in the first dielectric layer, the first etch stop layer 209, and the interlayer dielectric layer 202; forming a metal material film in the third opening and on the surface of the first dielectric layer 210; and planarizing the metal material film until the surface of the first dielectric layer 210 is exposed to form the conductive structure 211.

[0065] The material of the conductive structure 211 includes cobalt. As a conductive wire material, cobalt material has good filling capacity and conductivity, so that the formed device has strong conductivity and lower power consumption.

[0066] Please refer to Fig.10 , forming a second etch stop layer 212 on the surface of the first dielectric layer 210 and the conductive structure 211 ; and forming a second dielectric layer 213 on the surface of the second etch stop layer 212 .

[0067] The material of the second dielectric layer 213 is a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0068] When the second opening is subsequently formed, the second etch stop layer 212 is used to reduce etching damage to the conductive structure 211 .

[0069] Please refer to Fig.11, forming a first opening 214 and a second opening 215, wherein the first opening 214 is located in the second dielectric layer 213, the second etch stop layer 212, the first dielectric layer 210 and the first etch stop layer 209, and the first opening 214 exposes the modified layer 208, and the second opening 215 is located in the second dielectric layer 213 and the second etch stop layer 212, and the second opening 215 exposes the top surface of the conductive structure 211.

[0070] The formation process of the first opening 214 includes a dry etching process, and the formation process of the second opening 215 includes a dry etching process. The dry etching process is conducive to forming an opening with a better morphology.

[0071] In this embodiment, the method for forming the second opening 215 includes: forming a second patterned layer on the surface of the second dielectric layer 213, wherein the second patterned layer exposes a portion of the second dielectric layer 213 on the conductive structure 211; and etching the second dielectric layer 213 using the second patterned layer as a mask until the conductive structure 211 is exposed.

[0072] In this embodiment, the method for forming the first opening 214 includes: forming a third patterned layer on the surface of the second dielectric layer 213 and in the second opening 215, wherein the third patterned layer exposes a portion of the second dielectric layer 213 on the modified layer 208; using the third patterned layer as a mask, etching the second dielectric layer 213 and the first dielectric layer 210 until the modified layer 208 is exposed; after forming the modified layer 208, removing the third patterned layer. In this embodiment, the first opening 214 is formed after the second opening 215. In other embodiments, there is no requirement for the order of forming the first opening 214 and the second opening 215.

[0073] In this embodiment, after forming the first opening 214 and before forming the first conductive layer, the modified layer 208 exposed by the first opening 214 is surface treated so that the surface of the modified layer has second ions.

[0074] A second chemical bond is formed between the second ion and the metal ion, and the bond energy of the second chemical bond is lower than the bond energy of the first chemical bond.

[0075] The second ion includes a fluoride ion. In this embodiment, the second ion is a fluoride ion, and the second chemical bond formed between the fluoride ion and the tungsten ion is a tungsten-fluoride ion. Specifically, the bond energy of the tungsten-fluoride bond is lower than the bond energy of the chlorine-tungsten bond.

[0076] In this embodiment, the surface treatment is used to form a tungsten-fluorine bond in the modified layer. The existence of the tungsten-fluorine bond provides preparation for the formation of tungsten material, shortening the preparation time for adsorbing tungsten hexafluoride gas in the subsequent first conductive layer formation process, so that the growth rate of tungsten material formed on the surface of the modified layer 208 is higher than the growth rate of tungsten material formed on the top surface of the conductive structure 211, thereby reducing the situation where the first opening 214 on the modified layer 208 is closed prematurely before being filled with tungsten material, thereby improving the performance of the formed semiconductor structure.

[0077] The process parameters of the surface treatment include: using fluorine-containing gas and a treatment temperature range of 300 degrees Celsius to 400 degrees Celsius.

[0078] The fluorine-containing gas includes one or more of fluorine gas, hydrogen fluoride, and tungsten hexafluoride. In this embodiment, the fluorine-containing gas is fluorine gas.

[0079] Please refer to Fig.12 A first conductive layer 216 is formed in the first opening 214, and a second conductive layer 217 is formed in the second opening 215, and the top surfaces of the first conductive layer 216 and the second conductive layer 217 are flush with the top surface of the second dielectric layer 213, and the growth rate of the material of the first conductive layer 216 on the surface of the modified layer 208 is higher than the growth rate of the material of the first conductive layer 216 on the surface of the covering layer 207.

[0080] The method for forming the first conductive layer 216 and the second conductive layer 217 includes: depositing a conductive material layer in the first opening 214 and the second opening 215 until the first opening 214 and the second opening 215 are filled; and planarizing the conductive material layer until the second dielectric layer 213 is exposed. The first conductive layer 216 and the second conductive layer 217 are formed by depositing the same metal material in the same process, which is conducive to reducing production costs.

[0081] The conductive material layer includes tungsten.

[0082] The formation process of the first conductive layer 216 and the second conductive layer 217 includes a selective deposition process. Specifically, the formation process of the first conductive layer 216 and the second conductive layer 217 is a chemical vapor deposition process. The chemical vapor deposition process has a good step coverage rate and is short in time and low in cost compared to the atomic layer deposition process.

[0083] The process parameters of the selective deposition process include: the reaction gas includes tungsten hexafluoride and hydrogen, and the reaction temperature ranges from 300 degrees Celsius to 400 degrees Celsius.

[0084] Since the depth of the first opening 214 is higher than the depth of the second opening 215, it is easy to cause the first opening 214 to be not filled yet and the second opening 215 to be filled, and further deposition causes the material of the second conductive layer in the second opening 215 to continue to grow, so as to cover the first opening 214, resulting in premature closure of the first opening 214. In this embodiment, through the modification treatment and the surface treatment of the modified layer, the growth rate of the tungsten material in the first opening 214 is higher than the growth rate in the second opening 215, thereby reducing the situation where the first opening 214 is closed prematurely before being filled with the tungsten material, thereby improving the performance of the formed semiconductor structure.

[0085] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Fig.12 , comprising: a substrate, the substrate comprising a base 201, a gate structure located on the base 201 and an interlayer dielectric layer 202 (such as Figure 8 The interlayer dielectric layer 202 is also located on the sidewall of the gate structure and exposes the top surface of the gate structure; the capping layer 207 is located on the top surface of the gate structure; the capping layer 207 is located on the top surface of the gate structure, and the material of the capping layer 207 includes metal; the modified layer 208 is located on the surface of the capping layer 207; the first etch stop layer 209 is located on the surface of the substrate and the modified layer 208; the first dielectric layer 210 is located on the surface of the first etch stop layer 209; 0, the first etch stop layer 209 and the conductive structure 211 in the interlayer dielectric layer 202, the top surface of the conductive structure 211 is flush with the top surface of the first dielectric layer 210; a second etch stop layer 212 located on the surface of the first dielectric layer 210 and the conductive structure 211; a second dielectric layer 213 located on the second etch stop layer 212; a first opening 214 (such as Fig.11 As shown), the first opening 214 exposes the modified layer 208, and the second opening 215 (as shown) located in the second dielectric layer 213 and the second etch stop layer 212 Fig.11 As shown), and the second opening 215 exposes the top surface of the conductive structure 211; the first conductive layer 216 is located in the first opening 214, and the second conductive layer 217 is located in the second opening 215, and the top surfaces of the first conductive layer 216 and the second conductive layer 217 are flush with the top surface of the second dielectric layer 213.

[0086] In this embodiment, the substrate further includes a source-drain layer 206 located in the substrate on both sides of the gate structure, and the conductive structure 211 is located on the surface of the source-drain layer 206 .

[0087] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a base, a gate structure located on the base, and an interlayer dielectric layer located on the base, wherein the interlayer dielectric layer is also located on a sidewall of the gate structure and exposes a top surface of the gate structure; A covering layer located on the top surface of the gate structure, wherein the material of the covering layer comprises metal; a modified layer located on the surface of the covering layer; A first etch stop layer located on the surface of the substrate and the modified layer; a first dielectric layer located on a surface of the first etch stop layer; A conductive structure located in the first dielectric layer, the first etch stop layer and the interlayer dielectric layer, wherein the top surface of the conductive structure is flush with the top surface of the first dielectric layer; A second etch stop layer located on the surface of the first dielectric layer and the conductive structure; a second dielectric layer located on the second etch stop layer; a first opening located in the second dielectric layer, the second etch stop layer, the first dielectric layer and the first etch stop layer, wherein the first opening exposes the modified layer, and a second opening located in the second dielectric layer and the second etch stop layer, wherein the second opening exposes the top surface of the conductive structure; A first conductive layer is located in the first opening, and a second conductive layer is located in the second opening, and the top surfaces of the first conductive layer and the second conductive layer are flush with the top surface of the second dielectric layer, and the growth rate of the material of the first conductive layer on the surface of the modified layer is higher than the growth rate of the material of the first conductive layer on the surface of the covering layer.

2. The semiconductor structure according to claim 1, wherein: The substrate further comprises a source-drain layer located in the substrate at both sides of the gate structure, and the conductive structure is located on the surface of the source-drain layer.

3. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a base, a gate structure located on the base, and an interlayer dielectric layer located on the base, wherein the interlayer dielectric layer is also located on a sidewall of the gate structure and exposes a top surface of the gate structure; Forming a covering layer on the top surface of the gate structure, wherein the material of the covering layer includes metal; Performing modification treatment on the surface of the covering layer to form a modified layer; forming a first etch stop layer on the surfaces of the substrate and the modified layer; forming a first dielectric layer on a surface of the first etch stop layer; forming a conductive structure in the first dielectric layer, the first etch stop layer and the interlayer dielectric layer, wherein a top surface of the conductive structure is flush with a top surface of the first dielectric layer; forming a second etch stop layer on the first dielectric layer and the surface of the conductive structure; forming a second dielectric layer on a surface of the second etch stop layer; Forming a first opening and a second opening, wherein the first opening is located in the second dielectric layer, the second etch stop layer, the first dielectric layer and the first etch stop layer, and the first opening exposes the modified layer, and the second opening is located in the second dielectric layer and the second etch stop layer, and the second opening exposes the top surface of the conductive structure; A first conductive layer is formed in the first opening, and a second conductive layer is formed in the second opening, and the top surfaces of the first conductive layer and the second conductive layer are flush with the top surface of the second dielectric layer, and a growth rate of the material of the first conductive layer on the surface of the modified layer is higher than a growth rate of the material of the first conductive layer on the surface of the covering layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The substrate further comprises a source-drain layer located in the base at both sides of the gate structure; the conductive structure is located on the surface of the source-drain layer.

5. The method for forming a semiconductor structure according to claim 3, wherein: Also includes: After forming the first opening and before forming the first conductive layer, surface treatment is performed on the modified layer exposed by the first opening so that the surface of the modified layer has second ions.

6. The method for forming a semiconductor structure according to claim 5, wherein: Before forming the modified layer, the covering layer has a first ion, the material of the covering layer includes a metal ion, a first chemical bond is formed between the first ion and the metal ion; a second chemical bond is formed between the second ion and the metal ion, and the bond energy of the second chemical bond is lower than the bond energy of the first chemical bond.

7. The method for forming a semiconductor structure according to claim 6, wherein: The first ions include chloride ions; and the second ions include fluoride ions.

8. The method for forming a semiconductor structure according to claim 5, wherein: The process parameters of the surface treatment include: using fluorine-containing gas and a treatment temperature range of 300 degrees Celsius to 400 degrees Celsius.

9. The method for forming a semiconductor structure according to claim 8, wherein: The fluorine-containing gas includes a combination of one or more of fluorine gas, hydrogen fluoride, and tungsten hexafluoride.

10. The method for forming a semiconductor structure according to claim 3, wherein: The modification treatment process includes a plasma treatment process; The process parameters of the plasma treatment process include: the reaction gas includes hydrogen.

11. The method for forming a semiconductor structure according to claim 3, wherein: The process of forming the capping layer includes a selective atomic layer deposition process.

12. The method for forming a semiconductor structure according to claim 11, wherein: The process parameters of the atomic layer deposition process include: the reaction gas includes tungsten chloride and hydrogen, and the reaction temperature ranges from 400 degrees Celsius to 500 degrees Celsius.

13. The method for forming a semiconductor structure according to claim 3, wherein: The formation process of the first conductive layer and the second conductive layer includes a selective deposition process.

14. The method for forming a semiconductor structure according to claim 13, wherein: The process parameters of the selective deposition process include: the reaction gas includes tungsten hexafluoride and hydrogen, and the reaction temperature ranges from 300 degrees Celsius to 400 degrees Celsius.

15. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the first conductive layer and the second conductive layer includes: depositing a conductive material layer in the first opening and the second opening until the first opening and the second opening are filled; planarizing the conductive material layer until the second dielectric layer is exposed; and the growth rate of the conductive material layer in the first opening is higher than the growth rate in the second opening.

16. The method for forming a semiconductor structure according to claim 15, wherein: The conductive material layer includes tungsten.

17. The method for forming a semiconductor structure according to claim 3, wherein: The material of the conductive structure includes cobalt.

18. The method for forming a semiconductor structure according to claim 3, wherein: The metal includes tungsten.

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