A resistor layout and design method thereof, and semiconductor structure

Abstract

The present invention provides a resistor layout, a design method thereof, and a semiconductor structure, wherein the resistor layout includes: a first resistor array and a second resistor array; the first resistor array includes a plurality of first resistor unit segments extending along a first direction and arranged along a second direction, wherein the first and second directions intersect; the second resistor array includes a plurality of second resistor unit segments extending along the first direction and arranged along the second direction; wherein the second resistor array is located outside the first resistor array in the second direction. In an embodiment of the present invention, by arranging the second resistor array outside the first resistor array, the first resistor unit segments located at the edge are further away from the processing edge. This reduces the impact of process on the resulting desired resistance during manufacturing, thereby improving the resistance accuracy and reliability.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and in particular relates to a resistor pattern and a design method thereof, and a semiconductor structure. Background Art

[0002] Resistors are used in analog circuits as bias resistors to determine the circuit's operating point. Resistors, along with capacitors, can form filters, delay circuits, voltage dividers, current shunts, and load resistors. Resistors are widely used in analog circuits. Analog circuit design requires a precise resistor. For example, in an LDO (low drop-out regulator) circuit, the reference voltage is calculated by multiplying the current by the resistance, necessitating very high resistor precision. During the manufacturing process, semiconductor device resistors are affected by semiconductor process variations and the varying semiconductor process handling of surrounding components. Consequently, the actual resistor value produced may deviate from the designed value. Ignoring this resistance deviation can compromise product stability and reliability.

[0003] The resistors produced based on the current resistor layout structure have a large error between the resistance values ​​expected in the circuit design. Therefore, how to optimize the resistor layout structure and further improve the accuracy and reliability of the resistors is an urgent problem to be solved. Summary of the Invention

[0004] The present invention is intended to solve all or part of the problems of the above-mentioned prior art and provides a resistor layout. By setting a second resistor array on the periphery of the first resistor array, the first resistor unit segment located at the edge is made farther away from the process edge. The desired resistance finally obtained is less affected by the process during the manufacturing process, thereby improving the resistance accuracy and reliability.

[0005] The present invention provides a resistor layout comprising: a first resistor array and a second resistor array; the first resistor array comprising a plurality of first resistor unit segments extending along a first direction and arranged along a second direction, wherein the first and second directions intersect; and the second resistor array comprising a plurality of second resistor unit segments extending along the first direction and arranged along the second direction; wherein the second resistor array is located outside the first resistor array in the second direction. In an embodiment of the present invention, the second resistor array is disposed peripherally to the first resistor array, so that the environment of the first resistor unit segments at the edge of the first resistor array is the same as that of the other first resistor unit segments, thereby improving resistance accuracy. Furthermore, the first resistor unit segments at the edge are further away from the processing edge, so that the resulting desired resistance is less susceptible to process influences during manufacturing, thereby improving resistance accuracy and reliability. Furthermore, the impact of noise on the first resistor unit segments at the edge can be reduced. The second resistor array not only improves the resistance value accuracy of the first resistor array but also provides a backup second resistor unit segment for correcting the resistance value of the first resistor array.

[0006] Under normal circumstances, the second resistor array can be provided in one group; alternatively, two groups can be provided, one located on opposite sides of the first resistor array in the second direction. Preferably, the second resistor array is symmetrically arranged outside the first resistor array, so that both edges of the first resistor array are protected.

[0007] The resistor layout further includes: a plurality of first contact vias, each of the first resistor unit segments being provided with the first contact vias along a first direction, the first contact vias being electrically connected to the first resistor unit segment. Preferably, the first contact vias are provided at both ends of the first resistor unit segment along the first direction. Of course, the number and positions of the first contact vias may be set according to actual needs; a plurality of first connecting conductors, each of the first connecting conductors being electrically connected to the first contact vias located in different first resistor unit segments; a plurality of second contact vias, each of the second resistor unit segments being provided with the second contact vias along the first direction, the second contact vias being electrically connected to the second resistor unit segment. Preferably, the second contact vias are provided at both ends of the second resistor unit segment along the first direction. Of course, the number and positions of the second contact vias may be set according to actual needs; optimally, the number and position of the second contact vias located in one second resistor unit segment are the same as the number and position of the first contact vias located in the nearest first resistor unit segment; and a plurality of second connecting conductors, each of the second connecting conductors being electrically connected to the second contact vias located in different second resistor unit segments. Here, the first resistance unit segment includes but is not limited to polysilicon resistors, well resistors, metal resistors, etc. The first resistance unit segment and the second resistance unit segment can be the same. The total resistance value of the first resistor array can be adjusted by connecting multiple first resistance unit segments through the first connecting conductor and the first contact via. The multiple first resistance unit segments are connected in series through the multiple first connecting conductors, and / or the multiple second resistance unit segments are connected in series through the multiple second connecting conductors. In this way, the total resistance value of the multiple first resistance unit segments can be easily adjusted.

[0008] The resistor layout also includes: a plurality of third connecting conductors, each of which electrically connects two second contact vias located in the same second resistor unit segment; and a fourth connecting conductor, through which the second resistor array is connected to a ground line. This short-circuits the two second contact vias in each second resistor unit segment and connects the second resistor array to the circuit ground line, further reducing noise interference with the resistors.

[0009] The spacing between adjacent first resistor unit segments along the second direction is a first width; the spacing between the first resistor array and the second resistor array along the second direction is a second width; and the spacing between adjacent second resistor unit segments along the second direction is a third width; wherein the first width, the second width, and the third width are equal. Due to edge process effects, theoretical and experimental data indicate that when the spacing between the first resistor array and the second resistor array along the second direction is equal to the spacing between the first resistor unit segments along the second direction, the protection effect of the second resistor array is better than when the spacing is unequal; when the spacing between adjacent second resistor unit segments along the second direction is equal to the spacing between adjacent first resistor unit segments along the second direction, the protection effect of the second resistor array is better than when the spacing is unequal; and the best technical effect is achieved when the first width, the second width, and the third width are equal.

[0010] The resistor layout also includes dummy resistors located outside the second resistor array along the second direction, extending along the first direction and parallel to the second resistor unit segments. The dummy resistors can further ensure that the process environment of the second resistor unit segments at the edge is consistent with the process environment of other second resistor unit segments. In subsequent processes, all second resistor unit segments can serve as backup trimming resistors for the first resistor unit segments.

[0011] The resistor layout also includes a third resistor array comprising a plurality of third resistor unit segments extending along the first direction and arranged along the second direction. The third resistor array is located outside the first resistor array in the first direction. Preferably, the third resistor arrays are located on opposite sides of the first resistor array in the first direction. This protects the first resistor array, reduces process margin effects, and improves resistor accuracy.

[0012] The present invention also provides a semiconductor structure, including the resistor pattern described in the present invention, or prepared by the resistor pattern.

[0013] The present invention also provides a resistor layout design method, comprising: Step S1: obtaining an original resistor layout group, wherein the original resistor layout group includes at least a first resistor array layout, wherein the first resistor array layout includes a plurality of first resistor unit segments extending along a first direction and arranged along a second direction; Step S2: providing a second resistor array layout within the original resistor layout group, wherein the second resistor array layout is located outside the first resistor array layout in the second direction, and includes a plurality of second resistor unit segments extending along the first direction and arranged along the second direction. Generally, the layout layer of the second resistor unit segments is the same as the layout layer of the first resistor unit segments; however, under specific process conditions, the second and first resistor unit segments may also be located on different layout layers.

[0014] In step S1, the first resistor array layout further comprises: a plurality of first contact vias, each of which is disposed along a first direction in the first resistor unit segment and electrically connected to the first resistor unit segment; and a plurality of first connecting conductors, each of which is electrically connected to the first contact vias located in different first resistor unit segments. In step S2, the second resistor array layout further comprises: a plurality of second contact vias, each of which is disposed along the first direction in the second resistor unit segment and electrically connected to the second resistor unit segment; and a plurality of second connecting conductors, each of which is electrically connected to the second contact vias located in different second resistor unit segments. Generally, the layout layer of the second contact vias is the same as that of the first contact vias, and the layout layer of the second connecting conductors is the same as that of the first connecting conductors. However, under specific process conditions, the layout layer of the second contact vias may be located on a different layout layer from that of the first contact vias, and the layout layer of the second connecting conductors may be located on a different layout layer from that of the first connecting conductors.

[0015] After setting the second resistor array layout, the method further includes: providing a plurality of third connecting conductors, each of the third connecting conductors electrically connecting two second contact vias located on the same second resistor unit segment; and providing a fourth connecting conductor, the second resistor array layout being connected to a ground line via the fourth connecting conductor. The layout layers of the third connecting conductors, the fourth connecting conductors, and the second connecting conductors may be the same.

[0016] After providing the fourth connecting conductor, the method further includes: providing a fifth connecting conductor, the fifth connecting conductor connecting the first resistor array layout and the second resistor array layout; removing a portion of the second connecting conductor to decompose the second resistor array layout into a practical second resistor array layout and a dummy second resistor array layout, the practical second resistor array layout being connected to the first resistor array layout via the fifth connecting conductor; and removing a third connecting conductor located within the practical second resistor array layout. The layout layer of the fifth connecting conductor may be the same as the layout layer of the second connecting conductor.

[0017] Compared with the prior art, the present invention has the following main beneficial effects:

[0018] The resistor layout provided by the present invention, by disposing a second resistor array outside the first resistor array, ensures that the environment of the first resistor unit segments at the edge of the first resistor array is the same as that of the other first resistor unit segments, thereby improving resistance accuracy. Furthermore, the first resistor unit segments located at the edge are far from the processing edge, so the resulting desired resistance is less affected by the process during the manufacturing process, thereby improving the reliability of resistance accuracy. At the same time, the impact of noise on the first resistor unit segments located at the edge can be reduced. The second resistor array not only improves the resistance value accuracy of the first resistor array but also provides a spare second resistor unit segment for correcting the resistance value of the first resistor array.

[0019] The resistor layout design method provided by the present invention can directly utilize the second resistor unit segments in the second resistor array layout, change the connecting lines to connect part of the second resistor unit segments with the first resistor array layout, thereby adjusting the resistance value of the original layout group, which can reduce the resistor layout design time, improve the layout design efficiency, and save costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic structural diagram of a resistor layout provided by an embodiment of the present invention;

[0021] Figure 2 A schematic structural diagram of another resistor layout provided by an embodiment of the present invention;

[0022] Figure 3 A schematic structural diagram of another resistor layout provided by an embodiment of the present invention;

[0023] Figure 4 A schematic flow chart of a resistor layout design method provided by an embodiment of the present invention;

[0024] Figures 5a-5f A schematic diagram of the structure of the resistor layout provided in an embodiment of the present invention during the design process.

[0025] Reference numerals:

[0026] 10-original resistor layout group; 11-first resistor array; 111-first resistor unit segment; 112-first contact via; 113-first connecting conductor; 12-second resistor array; 121-second resistor unit segment; 122-second contact via; 123-second connecting conductor; 124-third connecting conductor; 125-fourth connecting conductor; 126-ground wire; 127-dummy resistor; 128-fifth connecting conductor; 13-third resistor array; 14-actual second resistor array; 15-dummy second resistor array. DETAILED DESCRIPTION

[0027] The following is a clear and complete description of the technical solutions in the specific embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0028] In semiconductor manufacturing, a complete semiconductor device is completed through multiple process steps. The closer the semiconductor device is to the edge of the process, the greater the impact of process errors. In actual operation, when preparing resistors through resistor layout, the edge resistor segments may fail to etch due to over- or under-exposure, or the reflection and diffraction of light during the photolithography process may affect the size and accuracy of the physical pattern of the resistor segment. In layout design, adding resistor protection structures around resistors is a common practice to improve resistor accuracy. Traditional resistor protection layout structures, such as polysilicon resistors, add dummy resistors of the same size and spacing as the polysilicon resistor segments on both sides of the polysilicon resistor. This traditional resistor protection structure has limited effect on improving resistor accuracy.

[0029] Based on this, see Appendix Figure 1 The present invention provides a resistor layout, which includes: a first resistor array 11 and a second resistor array 12; the first resistor array 11 includes a plurality of first resistor unit segments 111 extending along a first direction and arranged along a second direction, wherein the first direction and the second direction intersect; the second resistor array 12 includes a plurality of second resistor unit segments 121 extending along the first direction and arranged along the second direction; wherein the second resistor array 12 is located outside the first resistor array 11 in the second direction.

[0030] In this embodiment of the present invention, a second resistor array is disposed outside the first resistor array, ensuring that the environment of the first resistor unit segments at the edge of the first resistor array is consistent with that of the other first resistor unit segments, thereby improving resistance accuracy. Furthermore, the first resistor unit segments located at the edge are further away from the process edge, minimizing the impact of process changes on the resulting desired resistance during manufacturing, thereby improving resistance accuracy and reliability. Furthermore, the impact of noise on the first resistor unit segments located at the edge can be reduced. The second resistor array not only improves the resistance accuracy of the first resistor array but also provides a backup second resistor unit segment for resistance value correction. The width and length of the first resistor unit segment can be any value permitted by the process and are not limited. The first resistor unit segment includes, but is not limited to, poly (polysilicon) resistors, well resistors, metal resistors, and the like. The first and second resistor unit segments can be identical. The resistor array can include positive (PLUS) and negative (MINUS) terminals for input and output of test signals.

[0031] In some embodiments, the resistor array may also include three terminals: positive (PLUS), negative (MINUS), and B. For example, in a polysilicon resistor, the substrate directly below the three-terminal resistor is connected to a fixed potential, corresponding to the B terminal. For example, the B terminal of an n-well resistor is connected to power, while the B terminal of a p-well resistor is connected to ground. The B terminal provides a potential to the substrate below the resistor, reducing the impact of substrate noise on the polysilicon.

[0032] In some embodiments, the second resistor array 12 can be provided in one group or two groups, one located on opposite sides of the first resistor array 11 in the second direction. Preferably, the second resistor array can be symmetrically arranged outside the first resistor array, so that both edges of the first resistor array are protected.

[0033] See the attached Figure 1The resistor layout further includes: a plurality of first contact vias 112, the first resistor unit segment 111 is provided with first contact vias 112 along the first direction, the first contact vias 112 are electrically connected to the first resistor unit segment 111, preferably, the first contact vias are provided at both ends of the first resistor unit segment along the first direction, of course, the number and position of the first contact vias can also be set according to actual needs; a plurality of first connecting conductors 113, the first connecting conductors 113 are respectively electrically connected to the first contact vias 112 located on different first resistor unit segments 111; a plurality of second contact vias 122, the second resistor unit segment 121 is provided with first contact vias 112 along the first direction Second contact vias 122 are provided, electrically connected to the second resistor unit segments 111. Preferably, the second contact vias are located at both ends of the second resistor unit segments along the first direction. Of course, the number and location of the second contact vias can also be adjusted based on actual needs. In the most optimal case, the number and location of the second contact vias on a second resistor unit segment are the same as the number and location of the first contact vias on the closest first resistor unit segment. A plurality of second connecting conductors 123 are provided, each electrically connecting to the second contact vias 122 located on a different second resistor unit segment 121. In actual operation, the first connecting conductors and the second connecting conductors can extend along the second direction. The connection of the plurality of first resistor unit segments via the first connecting conductors and the first contact vias can adjust the total resistance value of the first resistor array.

[0034] In some embodiments, as shown in the attached Figure 1 As shown, multiple first resistance unit segments are connected in series through multiple first connecting conductors 113, and / or, multiple second resistance unit segments are connected in series through multiple second connecting conductors 123. In this way, it is convenient to subsequently adjust the total resistance of the multiple first resistance unit segments. In other embodiments, multiple first resistance unit segments can be connected in parallel through multiple first connecting conductors 113, and / or, multiple first resistance unit segments can be connected in parallel through multiple first connecting conductors 113. Taking the example of multiple first resistance unit segments connected in series through multiple first connecting conductors 113, the resistance of each first resistance unit segment is R1. Since the resistance of the first connecting conductor and the second connecting conductor, as well as the resistance of the contact via are much smaller than the resistance of the first resistance unit segment, they can be omitted.

[0035] In some embodiments, see Appendix Figure 1 The resistor layout further includes: a plurality of third connecting conductors 124, each of which electrically connects two second contact vias 122 located on the same second resistor unit segment 121; and a fourth connecting conductor 125, through which the second resistor array 121 is connected to a ground line 126. The third connecting conductors may be parallel to the second resistor unit segment.

[0036] In this way, the two second contact vias of each second resistor unit segment are short-circuited, and the second resistor array is connected to the ground line in the circuit, further reducing the interference of noise on the resistors.

[0037] The first, second, third, and fourth connecting conductors include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. It should be noted that the resistance of the first, second, third, and fourth connecting conductors is very small compared to the resistance of the first resistance unit segment and can be ignored.

[0038] In some embodiments, as shown in the attached Figure 1 As shown, the spacing between adjacent first resistor unit segments 111 along the second direction is a first width W1; the spacing between the first resistor array 11 and the second resistor array 12 along the second direction is a second width W2; and the spacing between adjacent second resistor unit segments 121 along the second direction is a third width W3. The first width W1, the second width W2, and the third width W3 are equal. Due to edge processing effects, theory and experiments have shown that when the spacing between the first resistor array 11 and the second resistor array 12 along the second direction is equal to the spacing between the first resistor unit segments along the second direction, the protection effect of the second resistor array is better than when the spacing is unequal, i.e., W2 = W1. When the spacing between adjacent second resistor unit segments 121 along the second direction is equal to the spacing between adjacent first resistor unit segments along the second direction, the protection effect of the second resistor array is better than when the spacing is unequal, i.e., W3 = W1. The optimal technical effect is achieved when the first width, the second width, and the third width are equal, i.e., W3 = W2 = W1.

[0039] In some embodiments, as shown in the attached Figure 2 As shown, the resistor layout also includes: dummy resistors 127, which are located outside the second resistor array 12 along the second direction. The dummy resistors 127 extend along the first direction and are parallel to the second resistor unit segments 121. The spacing between the second resistor array 12 and the dummy resistors 127 along the second direction is a fourth width W4, which is equal to the third width W3. In this way, the dummy resistors can further ensure that the process environment of the second resistor unit segments at the edge is consistent with the process environment of other second resistor unit segments. In subsequent processes, all second resistor unit segments can be used as backup trimming resistors for the first resistor unit segments.

[0040] In some embodiments, as shown in the attached Figure 3As shown, the resistor layout also includes: a third resistor array 13, the third resistor array 13 includes a plurality of third resistor unit segments 131 extending along the first direction and arranged along the second direction; wherein the third resistor array is located outside the first resistor array in the first direction. Preferably, the third resistor array is located on two opposite sides of the first resistor array in the first direction. In actual operation, the connection method of each third resistor unit segment in the third resistor array can be the same as the connection method of each first resistor unit segment in the first resistor array. Here, the spacing between adjacent third resistor unit segments along the second direction is a fifth width W5; experiments show that when the spacing between the third resistor unit segments along the second direction is equal to the spacing between the first resistor unit segments along the second direction, the protection effect of the second resistor array is optimal, that is, W5=W1. In this way, the third resistor array can protect the first resistor array, reduce the impact of process edges, and improve resistance accuracy. The third resistor unit segment 131 can be the same as the first resistor unit segment 111.

[0041] The present invention also provides a method for designing a resistor layout. Figure 4 As shown, the design method includes:

[0042] Step S1: obtaining an original resistor layout, the original resistor layout including a first resistor array, the first resistor array including a plurality of first resistor unit segments extending along a first direction and arranged along a second direction, wherein the first direction and the second direction intersect;

[0043] Step S2: providing a second resistor array, the second resistor array being located outside the first resistor array in the second direction, the second resistor array comprising a plurality of second resistor unit segments extending along the first direction and arranged along the second direction.

[0044] The following is combined with Figure 5a -Attached Figure 5f The design method of the resistor layout provided by the embodiment of the present invention is described in detail.

[0045] First, execute step S1, see the attached Figure 5a , obtaining an original resistor layout group 10. The original resistor layout group 10 includes at least a first resistor array 11 layout. The first resistor array 11 layout includes a plurality of first resistor unit segments 111 extending along a first direction and arranged along a second direction, wherein the first direction and the second direction intersect. Generally, the layout layer of the second resistor unit segments is the same as the layout layer of the first resistor unit segments; however, under specific process conditions, the two may also be located on different layout layers.

[0046] The first resistor array 11 layout is further provided with: a plurality of first contact vias 112, wherein the first contact vias 112 are respectively provided at both ends of the first resistor unit segment along the first direction, and the first contact vias 112 are electrically connected to the first resistor unit segment 111; and a plurality of first connecting conductors 113, wherein the first connecting conductors 113 are electrically connected to the first contact vias 112 respectively located on different first resistor unit segments 111.

[0047] Then execute step S2, see the attached Figure 5b , setting a second resistor array 12 layout, the second resistor array 12 layout is located outside the first resistor array 11 layout in the second direction, and the second resistor array 12 layout includes a plurality of second resistor unit segments 121 extending along the first direction and arranged along the second direction.

[0048] The second resistor array 12 layout further includes: a plurality of second contact vias 122, one located at each end of the second resistor unit segment 121 along the first direction, electrically connecting the second contact vias 122 to the second resistor unit segment 121; and a plurality of second connecting conductors 123, electrically connecting the second contact vias 122 located on different second resistor unit segments 121. Generally, the second contact vias are located on the same layout layer as the first contact vias, and the second connecting conductors are located on the same layout layer as the first connecting conductors. However, under specific process conditions, the second contact vias and the first contact vias may also be located on different layout layers, and the second connecting conductors and the first connecting conductors may also be located on different layout layers.

[0049] In some embodiments, as shown in the attached Figure 5b As shown, the spacing between adjacent first resistor unit segments 111 along the second direction is a first width W1; the spacing between the first resistor array 11 and the second resistor array 12 along the second direction is a second width W2; and the spacing between adjacent second resistor unit segments 121 along the second direction is a third width W3. The first width W1, the second width W2, and the third width W3 are equal. Due to edge process effects, both theory and experimentation indicate that when the spacing between the first resistor array 11 and the second resistor array 12 along the second direction is equal to the spacing between the first resistor unit segments along the second direction, the protection effect of the second resistor array is better than when the spacing is unequal, i.e., W2 = W1. When the spacing between adjacent second resistor unit segments 121 along the second direction is equal to the spacing between adjacent first resistor unit segments along the second direction, the protection effect of the second resistor array is better than when the spacing is unequal, i.e., W3 = W1. The optimal technical effect occurs when the first width, the second width, and the third width are equal, i.e., W3 = W2 = W1.

[0050] In some embodiments, see Appendix Figure 5c After setting the second resistor array layout, the method further includes: providing a plurality of third connecting conductors 124, each third connecting conductor 124 electrically connecting two second contact vias 122 located on the same second resistor unit segment 121; and providing a fourth connecting conductor 125, connecting the second resistor array 12 layout to a ground line 126 via the fourth connecting conductor 125. The layout layers of the third connecting conductors, the fourth connecting conductors, and the second connecting conductors can be the same.

[0051] In some embodiments, see Appendix Figure 5d -Attached Figure 5f After providing the fourth connecting conductor 125, the method further includes: providing a fifth connecting conductor 128, the fifth connecting conductor 128 connecting the first resistor array 11 layout and the second resistor array 12 layout; removing a portion of the second connecting conductor 123, so that the second resistor array 12 layout is decomposed into an actual second resistor array 14 layout and a dummy second resistor array 15 layout, the actual second resistor array 14 layout being connected to the first resistor array 11 layout via the fifth connecting conductor 128; and removing the third connecting conductor 124 located within the actual second resistor array 14 layout. The layout layer of the fifth connecting conductor can be the same as the layout layer of the second connecting conductor.

[0052] Specifically, first, see the attached Figure 5d A fifth connecting conductor 128 is provided, and the fifth connecting conductor 128 connects the first resistor array 11 layout and the second resistor array 12 layout.

[0053] Next, see the attached Figure 5e , part of the second connecting conductor 123 is removed, so that the second resistor array 12 layout is decomposed into a practical second resistor array 14 layout and a dummy second resistor array 15 layout, and the practical second resistor array 14 layout is connected to the first resistor array 11 layout through the fifth connecting conductor 128.

[0054] Then, see the attached Figure 5f , remove the third connecting conductor 124 located in the layout of the practical second resistor array 14.

[0055] The resistance value of the first resistor array in the original layout group is the desired resistance value designed in the simulation circuit. As shown in Figure 5, taking six first resistor unit segments connected in series as an example, the first resistor array 11 includes six first resistor unit segments 111 extending along the first direction and arranged along the second direction. The resistance value of the first resistor array is 6R1.

[0056] However, after actual testing, the resistor value may need to be changed. For example, when the ECO (Engineering Change Order) circuit is modified, the resistor value needs to be changed, which means that the resistor layout needs to be redesigned, wasting design time and affecting project progress.

[0057] As attached Figure 5a -Attached Figure 5f As shown, by setting the fifth connecting conductor, part of the second connecting conductor and the third connecting conductor are removed, so that part of the second resistance unit segment is connected to the first resistance array layout. Take 6 first resistance unit segments, and 3 second resistance unit segments are set on both sides of the first resistance array as an example. The resistance value of the first resistance unit segment is R1, and the resistance value of the second resistance unit segment is R2. The expected resistance value is 6R1, and the adjusted resistance value is 6R1+4R2. Under normal circumstances, R1 is equal to R2, that is, the adjusted resistance is 10R1. It should be understood that, taking the chain series resistor as an example, the input and output of the test signal are correspondingly transferred to the second resistance unit segment located at the edge of the practical second resistance array layout.

[0058] In some embodiments, the dummy second resistor array layouts on both sides of the first resistor array layout are symmetrical with respect to the first resistor array layout. This improves resistor reliability by utilizing the second resistor unit segments on both sides of the first resistor array layout.

[0059] In some embodiments, see Appendix Figure 2 After setting the second resistor array layout, the method further includes: setting a dummy resistor 127, the dummy resistor 127 is located outside the second resistor array 12 layout along the second direction, and the dummy resistor 127 extends along the first direction and is parallel to the second resistor unit segment 121. The spacing between the second resistor array 12 layout and the dummy resistor 127 along the second direction is a fourth width W4, and the fourth width W4 is equal to the third width W3. In this way, the dummy resistor can further make the process environment of the second resistor unit segment at the edge consistent with the process environment of other second resistor unit segments. In this way, all second resistor unit segments can be used as spare trimming resistors for the first resistor unit segment. Generally, the layout layer of the dummy resistor is the same as the layout layer of the second resistor unit segment; under specific process conditions, the two can also be located in different layout layers.

[0060] The layout design method provided by the present invention can directly utilize the second resistance unit segments in the second resistor array layout, change the connecting lines to connect part of the second resistance unit segments with the first resistor array layout, thereby adjusting the resistance value of the original layout group, which can reduce the resistor layout design time, improve the layout design efficiency, accelerate the ECO progress, and save costs.

[0061] Embodiments of the present invention also provide a semiconductor structure comprising or formed using the resistor layout of the above-described embodiment. The resistor layout provided by the present invention comprises a second resistor array disposed peripherally to a first resistor array. As such, the semiconductor structure (e.g., a resistor) formed using the resistor layout of the present invention is less susceptible to process influences during manufacturing. The semiconductor structure thus fabricated has improved performance, reliability, and precision.

[0062] In summary, the embodiments of the present invention improve resistance accuracy by disposing a second resistor array outside the first resistor array so that the environment of the first resistor unit segments at the edge of the first resistor array is the same as that of the other first resistor unit segments. Furthermore, since the first resistor unit segments at the edge are far from the process edge, the resulting desired resistance is less affected by the process during the manufacturing process, thereby improving the reliability of resistance accuracy. At the same time, the impact of noise on the first resistor unit segments at the edge can be reduced. The second resistor array not only improves the resistance value accuracy of the first resistor array but also provides a spare second resistor unit segment for correcting the resistance value of the first resistor array.

[0063] In order to facilitate the description of the present invention, some common English nouns or letters are used for illustrative reference only and are not intended to be restrictive or specific. The scope of protection of the present invention should not be limited by their possible Chinese translations or specific letters.

[0064] It should also be noted that, in this article, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. A resistor pattern, characterized in that: include: A first resistor array (11), a second resistor array (12), a plurality of third connecting conductors (124), a fourth connecting conductor (125), and a fifth connecting conductor (128); The first resistor array (11) comprises a plurality of first resistor unit segments (111) extending along a first direction and arranged along a second direction, a plurality of first contact guide holes (112), and a plurality of first connecting conductors (113), wherein the first direction and the second direction intersect, the first resistor unit segments (111) are provided with the first contact guide holes (112) along the first direction, the first contact guide holes (112) are electrically connected to the first resistor unit segments (111), and the first connecting conductors (113) are respectively electrically connected to the first contact guide holes (112) located on different first resistor unit segments (111); The second resistor array (12) comprises a plurality of second resistor unit segments (121) extending along the first direction and arranged along the second direction, a plurality of second contact guide holes (122) and a plurality of second connecting conductors (123); wherein the second resistor array (12) is respectively located on two opposite outer sides of the first resistor array (11) in the second direction, the first resistor unit segment (111) and the second resistor unit segment (121) are identical, the second resistor unit segment (121) is provided with the second contact guide hole (122) along the first direction, and the second contact guide hole (122) is provided on the second resistor unit segment (121). ) is electrically connected to the second resistance unit segment (121), and the second connection conductor (123) is electrically connected to the second contact guide holes (122) located on different second resistance unit segments (121); the spacing between adjacent first resistance unit segments (111) along the second direction is a first width; the spacing between the first resistance array (11) and the second resistance array (12) along the second direction is a second width; the spacing between adjacent second resistance unit segments (121) along the second direction is a third width; wherein the first width, the second width and the third width are equal; Each of the third connecting conductors (124) is electrically connected to two of the second contact vias (122) located on the same second resistance unit segment (121); the second resistor array (12) is connected to the ground line (126) via the fourth connecting conductor (125); and the fifth connecting conductor (128) connects the first resistor array (11) layout and the second resistor array (12) layout.

2. The resistor pattern according to claim 1, wherein: Also includes: A dummy resistor (127), the dummy resistor (127) is located outside the second resistor array (12) along the second direction, and the dummy resistor (127) extends along the first direction and is parallel to the second resistor unit segment (121).

3. The resistor pattern according to claim 1, wherein: Also includes: A third resistor array (13), the third resistor array (13) comprising a plurality of third resistor unit segments (131) extending along the first direction and arranged along the second direction; wherein the third resistor array (13) is respectively located on two opposite sides of the first resistor array (11) in the first direction.

4. A method for designing a resistor layout, characterized in that: include: Step S1: obtaining an original resistor layout group (10), wherein the original resistor layout (10) includes a first resistor array (11) layout, wherein the first resistor array (11) layout includes a plurality of first resistor unit segments (111) extending along a first direction and arranged along a second direction, wherein the first direction and the second direction intersect; the first resistor array (11) layout is provided with a plurality of first contact guide holes (112) and a plurality of first connecting conductors (113); the first resistor unit segment (111) is provided with the first contact guide holes (112) along the first direction, the first contact guide holes (112) are electrically connected to the first resistor unit segment (111), and the first connecting conductors (113) are respectively electrically connected to the first contact guide holes (112) located on different first resistor unit segments (111); Step S2: setting a second resistor array (12) layout, wherein the second resistor array (12) layout is located outside the first resistor array (11) layout in the second direction, and the second resistor array (12) layout includes a plurality of second resistor unit segments (121) extending along the first direction and arranged along the second direction; wherein the second resistor array (12) layout is provided with a plurality of second contact guide holes (122) and a plurality of second connecting conductors (123); the second resistor unit segments (121) are provided with the second contact guide holes (122) along the first direction, the second contact guide holes (122) are electrically connected to the second resistor unit segments (121), and the second connecting conductors (123) are respectively electrically connected to the second contact guide holes (122) located on different second resistor unit segments (121); Step S3: providing a plurality of third connecting conductors (124), each of the third connecting conductors (124) being electrically connected to two of the second contact vias (122) located on the same second resistance unit segment (121); providing a fourth connecting conductor (125), the second resistance array (12) layout being connected to the ground line (126) via the fourth connecting conductor (125); Step S4: setting a fifth connecting conductor (128), wherein the fifth connecting conductor (128) connects the first resistor array (11) layout and the second resistor array (12) layout; removing part of the second connecting conductor (123), so that the second resistor array (12) is decomposed into a practical second resistor array (14) layout and a dummy second resistor array (15) layout, wherein the practical second resistor array (14) layout is connected to the first resistor array (11) layout via the fifth connecting conductor (128); and removing the third connecting conductor (124) located in the practical second resistor array (12).

5. A semiconductor structure, characterized in that The invention comprises the resistor pattern according to any one of claims 1 to 3.

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