Semiconductor structure and preparation method therefor, and electronic device

Abstract

The present invention relates to the field of semiconductors. Provided are a semiconductor structure and a preparation method therefor, and an electronic device, which are used for simplifying semiconductor structures and preparation methods therefor. The preparation method for the semiconductor structure comprises: forming 2n stacked material layer groups (2101) on a first substrate (100), wherein each stacked material layer group (2101) comprises a first material film layer (2111) and a second material film layer (2121); forming n first openings (10) with different depths, and among the first openings (10) from shallow to deep, forming first isolation layers (310) at ends of the first (i-1) first material film layers (2111) penetrated by the ith first opening (10); forming a second opening (20) below each first opening (10), and forming second isolation layers (320) at ends of the first (n-1) first material film layers (2111) penetrated by each second opening (20); and below each second opening (20), forming a third opening (30) extending to the first substrate (100), and forming third isolation layers (330) at ends of the first material film layers (2111) penetrated by each third opening (30).

Description

Semiconductor structure and preparation method thereof, and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to a Chinese patent application filed with the Patent Office of China on February 29, 2024, with application number 2024102243938 and invention name “Semiconductor structure, preparation method thereof, and electronic device”. The entire contents of the patent application are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a preparation method thereof, and an electronic device. Background Art

[0004] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0005] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0006] Summary of the Invention

[0007] According to various embodiments of the present disclosure, a semiconductor structure, a method for manufacturing the same, and an electronic device are provided.

[0008] According to various embodiments of the present disclosure, a method for preparing a semiconductor structure is provided, the method comprising:

[0009] Providing a first substrate, and periodically stacking 2n stacked material layer groups on the first substrate, each of the stacked material layer groups including a first material film layer and a second material film layer, where n is a positive integer ≥ 2;

[0010] Etching the stacked material layer group to form n first openings with increasing depths, wherein the i-th first opening only penetrates the first to i-th stacked material layer groups in a direction close to the first substrate, 1≤i≤n; among the first material film layers exposed in each first opening, the last first material film layer is exposed, and first isolation layers are provided at ends of the other first material film layers;

[0011] Continue etching n stacked material layer groups downward from each of the first openings to form a second opening connected to the first opening, wherein the last first material film layer exposed in each of the second openings is exposed, and second isolation layers are provided at ends of the other first material film layers;

[0012] Continue etching the stacked material layer group downward in each of the second openings until the first substrate is exposed, forming a third opening connected to the second opening, and providing a third isolation layer at the end of each first material film layer exposed in the third opening;

[0013] A first conductive plug extending to the first substrate is formed in the second opening, and a second conductive plug insulated from the first conductive plug is formed in the first opening.

[0014] In some embodiments, the 2n first material film layers are 2n sacrificial material layers, and the 2n second material film layers are 2n insulating material layers. After forming the first conductive plug and the second conductive plug, the method further includes:

[0015] Replacing the 2n first material film layers in the 2n stacked material layer groups with 2n conductive layers, wherein the 2n conductive layers sequentially include the 1st to nth conductive layers and the n+1th to 2nth conductive layers in a direction close to the first substrate;

[0016] The first to nth conductive layers are connected to the second conductive plugs in a one-to-one correspondence;

[0017] The n+1th to 2nth conductive layers are connected to the first conductive plugs in a one-to-one correspondence.

[0018] In some embodiments, the 2n first material film layers are 2n conductive layers, and the 2n second material film layers are 2n insulating material layers;

[0019] Periodically stacking 2n stacked material layer groups on the first substrate, comprising: alternately forming 2n conductive layers and 2n insulating material layers on the first substrate;

[0020] In a direction close to the first substrate, the 2n conductive layers sequentially include the 1st to nth conductive layers and the n+1th to 2nth conductive layers;

[0021] The first to nth conductive layers are connected to the second conductive plugs in a one-to-one correspondence;

[0022] The n+1th to 2nth conductive layers are connected to the first conductive plugs in a one-to-one correspondence.

[0023] In some embodiments, forming the first isolation layer includes:

[0024] Anisotropically etching the stacked material layer group in a direction close to the first substrate to form n first initial holes with increasing depths, wherein the i-th first initial hole only penetrates the 1st to (i-1)th stacked material layer groups in a direction close to the first substrate;

[0025] etching back the first material film layers exposed by the first initial hole by wet etching to form a first transverse groove;

[0026] The first isolation layer is filled only in each of the first transverse grooves.

[0027] In some embodiments, forming the n first openings includes:

[0028] One of the stacked material layers is further etched downward along each of the first initial holes to form n first openings.

[0029] In some embodiments, filling the first isolation layer only in each of the first transverse grooves includes:

[0030] depositing a first isolation material layer in the first initial hole and the first transverse groove;

[0031] The first isolation material layer outside the first transverse groove is removed by anisotropic etching, and the first isolation material layer within the first transverse groove is retained as the first isolation layer.

[0032] In some embodiments, forming the second opening and the second isolation layer includes:

[0033] After forming the first opening, forming a first protective layer located on a sidewall of the first opening, wherein the first protective layer covers the first material film layer and the first isolation layer exposed by the first opening;

[0034] Continue etching downwards (n-1) of the stacked material layers in the first opening to form a second initial hole;

[0035] performing transverse etching on each first material film layer exposed by the second initial hole to form a second transverse groove;

[0036] forming a second isolation layer in the second transverse groove;

[0037] Continue etching one of the stacked material layers downward along the second initial hole to form the second opening.

[0038] In some embodiments, forming the third opening and the third isolation layer includes:

[0039] forming a second protective layer on a sidewall of the second opening, wherein the second protective layer covers the first material film layer and the second isolation layer exposed by the second opening;

[0040] Etching the remaining stacked material layer group downward in the second opening to form a third opening extending to the first substrate;

[0041] performing transverse etching on each first material film layer exposed by the third opening along the third opening to form a third transverse groove;

[0042] A third isolation layer is formed in each of the third transverse grooves in the third opening.

[0043] In some embodiments, forming a first conductive plug extending to the first substrate in the second opening, and forming a second conductive plug insulated from the first conductive plug in the first opening, includes:

[0044] Depositing a first plug material layer in each of the first openings, the corresponding second openings, and the third openings;

[0045] In a direction close to the first substrate, etching back each first plug material layer to the (n+1)th first material film layer to form the first conductive plug;

[0046] forming a plug insulating material layer on top of the first conductive plug;

[0047] In a direction close to the first substrate, etching the plug insulating material layer back to the (n+1)th second material film layer to form a plug insulating layer;

[0048] A second plug material layer is deposited in each of the first openings, the second openings, and on the plug insulating material layer, so that the second plug material layer completely fills the first openings.

[0049] According to various embodiments of the present disclosure, a semiconductor structure is further provided, comprising:

[0050] first base;

[0051] A stacked structure comprising 2n periodically distributed stacked layers stacked on the first substrate, each stacked layer comprising a conductive layer and an insulating isolation layer, where n is a positive integer ≥ 2;

[0052] The 2n periodically distributed stacked layer groups include: 1st to nth conductive layers and n+1th to 2nth conductive layers sequentially distributed in a direction close to the first substrate;

[0053] n through holes located in different areas of the first substrate, each of the n through holes passing through the stacked structure and exposing the first substrate; each of the through holes containing a first conductive plug, a plug insulating layer, and a second conductive plug sequentially distributed from a direction close to the first substrate;

[0054] Each of the first conductive plugs extends from the (n+1)th conductive layer to the 2nth conductive layer and is electrically connected to only one of the conductive layers;

[0055] Each of the second conductive plugs extends from the first conductive layer to the nth conductive layer and is electrically connected to only one of the conductive layers.

[0056] In some embodiments, the present invention further comprises:

[0057] An isolation layer is located on a sidewall of the through hole, and is used to isolate each conductive layer not connected to the first conductive plug and the second conductive plug from the first conductive plug and the second conductive plug.

[0058] In some embodiments, the conductive layer of the stacked structure includes a bit line extending along a first direction.

[0059] In some embodiments, the semiconductor structure further includes a second substrate;

[0060] A first peripheral circuit is provided on the first substrate, and the through hole exposes the first peripheral circuit on the first substrate;

[0061] A second peripheral circuit is provided on the second substrate;

[0062] The first conductive plug is connected to the second peripheral circuit on the second substrate;

[0063] The second conductive plug is connected to the first peripheral circuit on the first substrate.

[0064] In some embodiments, the conductive layer is connected to a bit line, and the first peripheral circuit and the second peripheral circuit include a sense amplifier circuit.

[0065] According to various embodiments of the present disclosure, a semiconductor structure is further provided, comprising:

[0066] A plurality of signal lines are periodically stacked on the first substrate, insulated from each other, and extend along a first direction. Along a direction close to the first substrate, the plurality of signal lines sequentially include 1st to nth signal lines and n+1th to mth signal lines;

[0067] a first peripheral circuit, located in the first substrate and below the plurality of signal lines;

[0068] a second peripheral circuit, located on the second substrate and above the plurality of signal lines;

[0069] Among the plurality of signal lines, the 1st to nth signal lines are connected to the second peripheral circuit, and the (n+1)th to (m)th signal lines are connected to the first peripheral circuit;

[0070] Wherein, m and n are both positive integers.

[0071] In some embodiments, the invention includes:

[0072] a plurality of through holes, spaced apart in the first direction, each through hole passing through the plurality of signal lines and exposing the first peripheral circuit;

[0073] Each of the through holes is sequentially filled with a first conductive plug and a second conductive plug that are insulated from each other, wherein each of the first conductive plugs extends from the first peripheral circuit to the (m+1)th signal line, and the second conductive plug extends from the second peripheral circuit to above the first conductive plug and is insulated from the first conductive plug by a plug insulation layer on top of the first conductive plug;

[0074] Each of the second conductive plugs is electrically connected to only one signal line among the 1st to nth signal lines; each of the first conductive plugs is electrically connected to only one signal line among the (n+1th) to mth signal lines.

[0075] In some embodiments, the semiconductor structure includes a memory structure, and the signal line includes a bit line or a word line.

[0076] In some embodiments, only two signal lines in each through hole are electrically connected to the first conductive plug and the second conductive plug, and n signal lines are spaced between two connection regions in each through hole that are electrically connected to the first conductive plug and the second conductive plug.

[0077] In some embodiments, the number of the periodically stacked signal lines is 2n.

[0078] In some embodiments, the first substrate and the second substrate are both silicon substrates, and the second substrate is bonded to the first substrate.

[0079] According to various embodiments of the present disclosure, an electronic device is further provided, comprising: the semiconductor structure described in any one of the embodiments.

[0080] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0082] FIG1 is a flow chart of a method for preparing a semiconductor structure provided in one embodiment;

[0083] 2 to 23 are schematic diagrams of the structure obtained during the preparation process of a semiconductor structure provided in one embodiment, wherein FIG2 is a schematic diagram of a three-dimensional structure, and in FIG3, FIG22 and FIG23, (a) is a schematic diagram of a three-dimensional structure, (b) is a schematic diagram of a top view of the structure, and (c) is a schematic diagram of a cross-sectional structure along the AA' direction. In FIG4 to FIG21, (a) is a schematic diagram of a top view of the structure, and (b) is a schematic diagram of a cross-sectional structure along the AA' direction.

[0084] FIG24 is a schematic perspective view of a partial structure of a semiconductor structure provided in one embodiment;

[0085] FIG25 is a schematic diagram of the cross-sectional structure of a structure obtained during the preparation process of a semiconductor structure provided in another embodiment. DETAILED DESCRIPTION

[0086] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0087] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0088] It should be understood that when an element or layer is referred to as being "on," "connected to," or "connected to" another element or layer, it can be directly on, connected to, or there can be intervening elements or layers. It should be understood that although the terms first, second, etc. may be used to describe various elements, layers, and / or parts, these elements, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, layer, or part from another. Thus, a first element, layer, or part discussed below may be referred to as a second element, layer, or part without departing from the teachings of the present invention.

[0089] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, an element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0090] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the term "comprising" is used in this specification, it can specify the presence of the stated features, steps, elements, and / or components, but does not preclude the presence or addition of one or more other features, steps, elements, and / or components. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0091] The relevant structures of the embodiments of the present invention should not be limited to the specific shapes shown in the drawings, but include shape deviations due to, for example, manufacturing technology. The shapes shown in the drawings are schematic in nature and do not limit the scope of the present invention.

[0092] In one embodiment, referring to FIG. 1 , a method for preparing a semiconductor structure is provided, comprising the following steps:

[0093] In step S10, referring to FIG. 2 , a first substrate 100 is provided, and 2n stacked material layer groups 2101 are periodically stacked on the first substrate 100. Each stacked material layer group 2101 includes a stacked first material film layer 2111 and a second material film layer 2121. The 2n stacked material layer groups include a total of 2n first material film layers and 2n second material film layers; n is a positive integer ≥ 2.

[0094] The 2n stacked material layer groups include, in order from the direction close to the first substrate, the 1st stacked material layer group, the 2nd stacked material layer group, ..., the nth stacked material layer group, the n+1th stacked material layer group, ..., the 2nth stacked material layer group; the 1st to nth stacked material layer groups are the 1st to nth stacked material layer groups, and the n+1th to 2nth stacked material layer groups are the n+1th to 2nth stacked material layer groups.

[0095] The first i stacked material layer groups are the 1st stacked material layer group to the i-th stacked material layer group, where i is a positive integer not exceeding 2n.

[0096] Similarly, the 2n first material film layers include, from the direction close to the first substrate, the 1st first material film layer, the 2nd first material film layer, ..., the nth first material film layer, the n+1th first material film layer, ..., the 2nth first material film layer; the 1st to nth first material film layers are the 1st to nth first material film layers, and the n+1th to 2nth first material film layers are the n+1th to 2nth first material film layers.

[0097] Similarly, the 2n second material film layers include, from the direction close to the first substrate, the 1st second material film layer, the 2nd second material film layer, ..., the nth second material film layer, the n+1th second material film layer, ..., the 2nth second material film layer; the 1st to nth second material film layers are the 1st to nth second material film layers, and the n+1th to 2nth second material film layers are the n+1th to 2nth second material film layers.

[0098] In step S20, please refer to Figure 7, the stacked material layer group 2101 is etched from the direction close to the first substrate to form n first openings 10 located in different areas of the first substrate 100 and with increasing depths, wherein the i-th first opening 10 only penetrates the first i stacked material layer groups 2101, 1≤i≤n; the first i stacked material layer groups are from the first stacked material layer group to the i-th stacked material layer group.

[0099] In Figure 7, the last first material film layer 2111 in the first opening 10 is exposed, and the remaining first material film layers 2111 are shielded by the first isolation layer 310. It can be understood that, starting from the second first opening 10, the first isolation layer 310 is formed at the end of the first (i-1) first material film layer 2111 penetrated by the i-th first opening 10, and the end of the i-th first material film layer 2111 penetrated by the i-th first opening is exposed in the first opening; this exposed first material film layer 2111 will subsequently be replaced with a conductive layer and connected to the peripheral circuit located at the top of the stacked material layer group by a plug.

[0100] Step S30, referring to FIG. 9 , in some embodiments, a first protective layer 610 is formed on each region of the sidewalls of the n first openings 10 . The first protective layer 610 covers the first material film layer 2111 and the first isolation layer 310 exposed in the first openings, so that the first material film layer 2111 and the first isolation layer 310 exposed in the first openings are not affected when the stacked material layer group is subsequently etched downward and the first material film layer 2111 is etched downward.

[0101] Step S40, referring to FIG. 13 , continues to etch n stacked material layer groups 2101 downward along each first opening 10 formed with the first protective layer 610 to form a plurality of second openings 20 corresponding one-to-one with and connected to the first openings 10. In FIG. 13 , the holes not covered by the first protective layer are second openings, and the second openings and the first openings are different regions of a single deep hole. Furthermore, among the n first material film layers 2111 penetrated by each second opening 20, the end portions of the first (n-1) first material film layers 2111 form a second isolation layer 320, and the end portion of the nth first material film layer 2111 is exposed in the second opening 20. This exposed first material film layer 2111 will subsequently be replaced with a conductive layer and then connected to the peripheral circuit by a plug.

[0102] Step S50, please refer to Figure 14. On the basis of forming the above-mentioned first protective layer, a second protective layer 620 is formed on each area of ​​the side wall of the second opening 20 to cover the second isolation layer and the first material film layer exposed by the second opening to avoid the influence of subsequent etching process; in the actual process, a second protective layer will be formed on the side walls of the first opening and the second opening, and the second protective layer covers the first protective layer.

[0103] Step S60, please refer to Figure 17, continue to etch downward along the first opening 10 and the second opening 20 formed with the second protective layer 620 until the first substrate 100 is exposed, and the hole formed by this etching process is a third opening 30 extending to the first substrate 100, and a third isolation layer 330 is formed at the end of each first material film layer 2111 passing through the third opening 30 to ensure that the first material film layer 2111 in the third opening will not be electrically connected to the plug; a first peripheral circuit is provided on the first substrate, and the first material film layer 2111 in the second opening will be subsequently replaced by a conductive layer and connected to the first peripheral circuit through the plug in the second opening.

[0104] Step S70, please refer to Figure 21, for each first opening and the second opening connected thereto, after removing the second protective layer 620 and the first protective layer 610, a connection structure 400 is formed in the first opening 10, the second opening 20 and the third opening 30 that are connected to each other, and the connection structure 400 includes a first conductive plug 410, a second conductive plug 430 and a plug insulation layer 420 therebetween. Each first conductive plug 410 extends from the (n+1)th first material film layer 2111 to the first substrate 100, and each second conductive plug 430 extends from the top of each first opening 10 to the nth first material film layer 2111; each first conductive plug 410 and each second conductive plug 430 is in contact with only one first material film layer that is not covered by the first isolation layer 310, the second isolation layer 320 and the third isolation layer 330.

[0105] In step S10, the first base 100 may include a semiconductor substrate 110. The semiconductor substrate 110 may include, for example, a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the semiconductor substrate may also include a Si / SiGe, Si / SiC, a silicon-on-insulator (SOI) substrate, or a silicon germanium-on-insulator substrate.

[0106] In addition, the first base 100 may further include a first peripheral circuit 120 formed based on the semiconductor substrate 110. When the conductive layer is a bit line, the first peripheral circuit 120 may include a sense amplifier SA, etc. When the conductive layer is a word line, the first peripheral circuit 120 may be a word line gating circuit, etc.

[0107] Referring to FIG. 2 , the materials of the 2n first material film layers 2111 and the 2n second material film layers 2121 in the stacked material layer group 2101 can be configured based on actual needs. For example, the 2n first material film layers 2111 can be configured as 2n sacrificial material layers, and the 2n second material film layers 2121 can be configured as 2n insulating material layers. These 2n sacrificial material layers are ultimately replaced with 2n conductive layers, which are connected to peripheral circuits via plugs.

[0108] As an example, the 2n first material film layers 2111 can be configured as 2n conductive material layers, and the 2n second material film layers 2121 can be configured as 2n insulating material layers. The 2n conductive material layers and 2n insulating material layers are stacked before forming the hole, eliminating the process step of replacing the sacrificial layer with the conductive layer.

[0109] The first material film layer 2111 and the second material film layer 2121 need to have a certain etching selectivity ratio.

[0110] As an example, the material of the sacrificial material layer may include but is not limited to silicon nitride, polysilicon, silicon germanium and the like, and the material of the insulating material layer may include but is not limited to silicon oxide.

[0111] At this time, after the subsequent step S70, please refer to Figures 22 and 23, which may also include: replacing 2n sacrificial material layers with 2n conductive layers 211, the 1st to nth conductive layers 211 are connected one-to-one with different second conductive plugs 430, and the n+1th to 2nth conductive layers 211 are connected one-to-one with different first conductive plugs 410.

[0112] Specifically, taking a semiconductor structure as a memory device as an example, for example, 2n stacked material layers 2101 can first be patterned and etched to form a device region (e.g., a memory cell region). The remaining sacrificial material layer after etching forms a sacrificial layer 213, and the remaining insulating material layer forms an insulating isolation layer 212. Each sacrificial layer 213 is then replaced with a plurality of conductive layers 211 separated by insulating isolation layers 212. The first through nth conductive layers 211 are connected to different second conductive plugs 430 in a one-to-one correspondence, and the n+1th through 2nth different conductive layers are connected to different first conductive plugs 410 in a one-to-one correspondence.

[0113] The conductive layer 211 may include signal lines of a memory cell array, such as bit lines or word lines.

[0114] Referring to Figure 22 , the device area can be formed by dry etching. After forming the device area, the sacrificial layer 213 can be wet-etched in the removed areas to remove it. Then, referring to Figure 23 , the exposed surface of the structure after the sacrificial layer 213 is removed can be replaced with a conductive material layer through electroplating or other methods. Subsequently, chemical mechanical polishing and etching processes are performed to leave only the conductive material layer between the insulating isolation layers 212, forming the conductive layer 211. The material of the conductive layer 211 can include, but is not limited to, a metal material.

[0115] This disclosure does not specifically limit whether the device region and the signal lines of the memory cell array are manufactured sequentially or simultaneously.

[0116] 23 , conductive layers 211 and insulating isolation layers 212 are alternately stacked to form a stacked structure 200 , wherein a set of conductive layers 211 and insulating isolation layers 212 corresponding to a stacked material layer set 2101 forms a stacked layer set 210 .

[0117] Furthermore, as an example, the stacked structure 200 may include a main body 200a and branch portions 200b, wherein the main body 200a extends along a first direction. The branch portions 200b extend along a second direction and are arranged on at least one side of the main body 200a along the first direction. A plurality of branch portions 200b may be arranged on each side of the main body 200a in the second direction. The conductive layer 211 of the main body 200a may serve as a bit line. The branch portions 200b may be used to form the source and drain of a transistor, or may further form capacitor electrodes. In this case, the source and drain of the transistor may be connected to the bit line and the first capacitor electrode of the capacitor, respectively, in the second direction.

[0118] Of course, the forms of the first material film layer 2111 and the second material film layer 2121 are not limited thereto.

[0119] For example, the material of the first material film layer 2111 can also be set to a conductive material (such as metal or polysilicon), that is, the first material film layer 2111 is a conductive material layer. The first to nth conductive material layers are connected to different second conductive plugs 430 in a one-to-one correspondence, and the n+1th to 2nth different conductive material layers are connected to different first conductive plugs 410 in a one-to-one correspondence. The second material film layer 2121 is an insulating material layer. In this case, the subsequent conductive material layer can be directly patterned to form the conductive layer 211.

[0120] For another example, the first material film layer 2111 and the second material film layer 2121 can be epitaxially formed superlattice materials, such as film layers of two materials (e.g., single-crystal silicon Si and single-crystal silicon germanium SiGe). In this case, after the first material film layer 2111 and the second material film layer 2121 are patterned, both can be replaced, such that the patterned first material film layer 2111 is replaced with the conductive layer 211, and the patterned second material film layer 2121 is replaced with the insulating isolation layer 212.

[0121] Each stacked material layer group 2101 may be formed by first forming a first material film layer 2111, and then forming a second material film layer 2121 on the first material film layer 2111. When 2n stacked material layer groups 2101 are stacked on the first substrate 100, the first material film layers 2111 and the second material film layers 2121 may be alternately formed on the first substrate 100.

[0122] As an example, before forming the first material film layer 2111 of the first stacked material layer group 2101 on the first substrate 100, an insulating dielectric material layer 5001 can be first formed on the first substrate 100. The material of the insulating dielectric material layer 5001 can be the same as that of the second material film layer 2121.

[0123] In step S20, referring to FIG. 7 , the first to nth stacked material layer groups 2101 may be etched to different depths at different locations on the first substrate or at different locations on the bit lines or word lines, thereby forming n first openings 10 of varying depths. As the depth of each first opening 10 increases, the number of stacked material layer groups 2101 penetrated by each first opening 10 may increase, such that the i-th first opening 10 penetrates i stacked material layer groups 2101.

[0124] Meanwhile, when the first isolation layer is formed at the end of the first (i-1)th first material film layer exposed by the i-th first opening, a (i-1)-turn first isolation layer 310 may be formed.

[0125] It can be understood that at this time, the ends of the first i first material film layers exposed by the i-th first opening are still exposed.

[0126] At the same time, it can be understood that for the first first opening, the first (i-1) first material film layers, i.e., the first 0 first material film layers, are exposed. Therefore, the first isolation layer 310 is not formed corresponding to the first first opening. The material of the first isolation layer 310 is an insulating material. As an example, the material of the first isolation layer 310 is a low-dielectric constant (low-K) material layer, thereby reducing the parasitic capacitance of the final structure.

[0127] Furthermore, as an example, the material of the first isolation layer 310 can be a material having a high etching selectivity ratio with the first material film layer 2111. In this case, when the first material film layer 2111 needs to be replaced with the conductive layer 211 and selective etching (such as wet etching) is performed later, the first isolation layer 310 can be effectively prevented from being removed.

[0128] In step S30, referring to FIG8 , a first protective material layer 6101 may be formed on the sidewalls and bottom of the first opening 10. Then, referring to FIG9 , the first protective material layer 6101 may be anisotropically etched (e.g., dry etched) to remove the first protective material layer 6101 at the bottom of the first opening 10, thereby forming a first protective layer 610 located on the sidewalls of the first opening 10.

[0129] The first protection layer 610 can cover and protect the first material film layer 2111 located at the bottom of the sidewall of the first opening 10 when the second isolation layer 320 is subsequently formed.

[0130] In step S40, referring to FIG. 13 , the n stacked material layer groups 2101 below each first opening 10 can be etched under the same etching conditions and time based on the first protective layer 610 to form a second opening 20 below each first opening 10 that is connected to the first opening 10. At this point, the depth of each second opening 20 is the same, which can be understood as the extension distance of each second opening 20 in a direction perpendicular to the first substrate being the same. Furthermore, because the sidewalls of the first opening 10 are covered by the first protective layer 610, the average pore size of the second openings 20 is smaller than the average pore size of the first opening 10.

[0131] At the same time, a second isolation layer 320 is formed at the end of the first (n-1)th first material film layer 2111 exposed by the second opening 20. It can be understood that at this time, the end of the nth first material film layer exposed by the first opening is still exposed.

[0132] The second isolation layer 320 is made of an insulating material. The material of the second isolation layer 320 can be the same as or different from the material of the first isolation layer 310. As an example, the material of the second isolation layer 320 is a low-k material layer, thereby reducing the parasitic capacitance of the final structure.

[0133] Furthermore, as an example, the material of the second isolation layer 320 can be a material having a high etching selectivity ratio with the first material film layer 2111. In this case, when the first material film layer 2111 needs to be replaced with the conductive layer 211 and selective etching (such as wet etching) is performed later, the second isolation layer 320 can be effectively prevented from being removed.

[0134] In step S50 , the material of the second protective layer 620 may be the same as or different from the material of the first protective layer 610 .

[0135] As an example, referring to FIG. 14 , a second protective material layer can be first formed on each region of the sidewalls of the first protective layer 610, each region of the sidewalls of the second opening 20, and the bottom of the second opening 20. At the same time, because the second opening 20 is formed by etching based on the first protective layer 610, the sidewalls of the first protective layer 610 are flush or nearly flush with the sidewalls of the second opening 20. Therefore, after forming the second protective material layer, the first protective material layer 6101 can be anisotropically etched (e.g., dry etching) to easily remove the first protective material layer 6101 at the bottom of the second opening 20, thereby forming a second protective layer 620 covering the sidewalls of the first protective layer 610 and the sidewalls of the second opening 20.

[0136] Of course, in other examples, as shown in FIG. 25 , the first protective layer 610 may be removed before forming the second protective layer 620. Then, through appropriate process conditions, a continuous second protective layer 620 may be formed covering the sidewalls of the first opening 10 and the sidewalls of the second opening 20 and between the sidewalls of the first opening 10 and the second opening 20.

[0137] The second protection layer 620 can cover and protect the first material film layer 2111 at the bottom of the sidewall of the first opening 10 and the first material film layer 2111 at the bottom of the sidewall of the second opening 20 when the third isolation layer 330 is subsequently formed.

[0138] In step S60 , referring to FIG. 17 , the stacked material layer group 2101 below the second openings 20 may be etched based on the second protection layer 620 , thereby forming a third opening 30 extending to the first substrate 100 under each second opening 20 .

[0139] Meanwhile, during the etching process, since the sidewall of the second opening 20 is covered by the second protection layer 620 , the aperture of the third opening 30 is smaller than that of the second opening 20 .

[0140] At the same time, a third isolation layer 330 is formed at the end of the first material film layer 2111 exposed by the third opening 30. The material of the third isolation layer 330 is an insulating material. As an example, the material of the second isolation layer 320 is a low dielectric constant material layer, thereby reducing the parasitic capacitance of the entire semiconductor structure.

[0141] In the disclosed embodiment, the tops of the first openings are flush with each other, and the bottoms of the first openings are stepped. The second openings extend downward from the bottoms of the first openings by the same distance, forming a step between the bottoms of the second openings, and the tops of the second openings are stepped. The third openings extend downward from the bottoms of the second openings to the first substrate, with the bottoms of the third openings flush with each other and the tops forming a step. The first, second, and third openings are different regions of a single through hole.

[0142] Furthermore, as an example, the material of the third isolation layer 330 can be a material having a high etching selectivity ratio with the first material film layer 2111. In this case, when the first material film layer 2111 needs to be replaced with the conductive layer 211 and selective etching (such as wet etching) is performed later, the third isolation layer 330 can be effectively prevented from being removed.

[0143] The material of the third isolation layer 330 , the material of the second isolation layer 320 , and the material of the first isolation layer 310 may be the same, different, or not completely the same.

[0144] In step S70, referring to FIG. 18 , when the second protective layer 620 is formed on the sidewalls of the first protective layer 610 and the sidewalls of the second opening 20, the second protective layer 620 and the first protective layer 610 can be removed simultaneously, thereby exposing the sidewalls of the first opening 10 and the sidewalls of the second opening 20. Alternatively, if the first protective layer 610 is removed before forming the second protective layer 620, and the second protective layer 620 is formed on the sidewalls of the first opening 10 and the sidewalls of the second opening 20, only the second protective layer 620 can be removed, thereby exposing the sidewalls of the first opening 10 and the sidewalls of the second opening 20.

[0145] As an example, the second protection layer 620 and the first protection layer 610 may be removed by wet selective etching.

[0146] After removing the second protective layer and the first protective layer, referring to FIG19 , a first conductive plug 410 extending from the (n+1)th first material film layer 2111 to the first substrate 100 can be formed. Then, referring to FIG20 , a plug insulating layer 420 is formed on the first conductive plug 410. Then, referring to FIG21 , a second conductive plug 430 extending from the top of the first opening 10 to the nth first material film layer 2111 is formed on the plug insulating layer 420.

[0147] The first conductive plug 410 extends from the (n+1)th first material film layer 2111 to the first substrate 100 , so that the conductive layer 211 formed by the subsequent transformation of the (n+1)th first material film layer 2111 can be effectively connected to the first conductive plug 410 corresponding to the first first opening 10 .

[0148] The second conductive plug 430 extends from the top of the first opening 10 to the nth first material film layer 2111 , so that the conductive layer 211 subsequently formed by the transformation of the nth first material film layer 2111 from top to bottom can be effectively connected to the second conductive plug 430 corresponding to the nth first opening 10 .

[0149] In this embodiment, 2n stacked material layer groups 2101 are first stacked on the first substrate 100, and a first opening 10, a second opening 20, and a third opening 30 are respectively formed in the 2n stacked material layer groups 2101. The first opening 10 and the second opening 20 expose the last first material film layer 2111 they penetrate, and isolation layers (first isolation layer 310, second isolation layer 320, and third isolation layer 330) surrounding the openings are formed in the remaining first material film layers 2111 penetrated by the first opening 10 and the second opening 20, and in each first material film layer 2111 penetrated by the third opening 30. At the same time, the number of stacked material layer groups 2101 penetrated by the n first openings 10 of varying depths increases one by one. The n second openings 20 all penetrate n stacked material layer groups 2101. The first conductive plug 410 extends from the (n+1)th first material film layer 2111 to the first substrate 100, while the second conductive plug 430 extends from the top of the first opening 10 to the nth first material film layer 2111. Therefore, within the n stacked material layer groups 2101 located in the upper half, only the first material film layer 2111 exposed by the first opening 10 will be connected to the subsequently formed second conductive plug 430, and the remaining first material film layers 2111 will be insulated from the second conductive plug 430 by the first isolation layer 310 and / or the second isolation layer 320. For the n stacked material layer groups 2101 located in the lower half, only the first material film layer 2111 exposed by the second opening 20 will be connected to the first conductive plug 410 formed subsequently, and the remaining first material film layers 2111 will be insulated from the first conductive plug 410 by the second isolation layer 320 and / or the third isolation layer 330.

[0150] Therefore, after the first material film layer 2111 is subsequently replaced with a conductive layer 211 or is directly patterned to form a conductive layer 211, for the n stacked material layer groups 2101 in the upper portion are transformed into the n stacked groups 210, each second conductive plug 430 is only connected to one conductive layer 211, and can be effectively insulated and isolated from the other conductive layers 211 by the first isolation layer 310 or the second isolation layer 320, and different conductive layers 211 are connected to different second conductive plugs 430; for the n stacked groups 210 in the lower portion are transformed into the n stacked material layer groups 2101, each first conductive plug 410 is only connected to one conductive layer 211, and can be effectively insulated and isolated from the other conductive layers 211 by the second isolation layer 320 or the third isolation layer 330, and different conductive layers 211 are connected to different first conductive plugs 410. At the same time, a plug insulating layer 420 is provided between the second conductive plugs 430 and the first conductive plugs 410. Therefore, each first conductive plug 410 can be connected to the first peripheral circuit 120 located below (e.g., the first peripheral circuit 120 located on the first substrate 100), and each second conductive plug 430 can be connected to the second peripheral circuit 810 located above (e.g., the second peripheral circuit 810 formed on the second substrate 800). Therefore, the upper and lower portions of the 2n stacked material groups 210, formed by transforming the 2n stacked material groups 2101, can be connected to peripheral circuits on their upper and lower sides, respectively.

[0151] Therefore, the method of this embodiment can effectively optimize the preparation process of the semiconductor structure of the three-dimensional memory device.

[0152] In one embodiment, step S20 includes:

[0153] In step S21, the stacked material layer group 2101 is anisotropically etched from a direction close to the first substrate to form n first initial holes 11 located in different regions of the first substrate and having increasing depths. For example, the first initial hole 11 includes a second initial hole, a third initial hole, and so on, and the nth initial hole. The depths of these n first initial holes gradually increase in the above-mentioned order. The depth difference between adjacent first initial holes is equal to the thickness of the stacked material layer group.

[0154] Wherein, starting from the second first initial hole, the i-th first initial hole 11 penetrates the 1st to (i-1)th stacked material layer groups 2101;

[0155] Step S22, referring to FIG. 4, the first material film layers 2111 exposed by the first initial holes are etched back by wet etching to form first transverse grooves 40;

[0156] In step S23 , referring to FIG. 6 , the first isolation layer 310 is filled only in each of the first transverse grooves 40 .

[0157] In step S21 , referring to FIG. 3 , a patterned mask layer 700 (eg, a hard mask) having n openings may be first formed on the top stacked material layer group 2101 .

[0158] Specifically, a mask material layer 7001 can be first formed on the top stacked material layer group 2101 (see FIG. 2 ). A first patterned photoresist is then formed using a photolithography process. The first patterned photoresist defines the opening regions of the patterned mask layer 700. Subsequently, a patterned etching process is performed on the mask material layer 7001 based on the first patterned photoresist, thereby forming a patterned mask layer 700 having n openings.

[0159] The shape of the opening of the patterned mask layer 700 can be square, circular, or other shapes, which is not limited here.

[0160] The material of the patterned mask layer 700 may include, but is not limited to, carbon, polysilicon, and the like.

[0161] Next, referring to FIG. 3 , each first initial hole 11 is drilled to a different depth through a trim etch based on the openings in the patterned mask layer 700. From shallow to deep, the i-th first initial hole 11 penetrates the first through (i-1)-th stacked material layer groups 2101. The first first initial hole 11 does not penetrate the stacked material layer group 2101.

[0162] At this point, a blocking layer (not shown) can first be filled in each opening of the patterned mask layer 700. Then, through exposure and development processes, a second patterned photoresist is formed on the patterned mask layer 700 after being filled with the blocking layer. This second patterned photoresist initially exposes the blocking layer only in one opening at the edge of the patterned mask layer 700. The exposed blocking layer is then etched away, and then etching is continued by the thickness of one stacked material layer group based on the opening in the patterned mask layer 700 where the blocking layer was removed. Thereafter, through a trimming process, the second patterned photoresist is laterally etched to successively expose the blocking layer filled in each of the remaining openings of the patterned mask layer 700. After each opening is exposed, the blocking layer is removed, and etching continues by the thickness of one stacked material layer group based on the opening where the blocking layer is removed and the opening where the blocking layer was previously removed. Etching continues until the last opening in the patterned mask layer 700 is exposed. At this time, the last exposed opening of the patterned mask layer 700 is not etched, thereby forming a first initial hole that penetrates zero stacked material layer groups 2101 (does not penetrate the stacked material layer groups 2101). Etching is performed (n-1) times with a thickness equal to the thickness of one stacked material layer group under the first exposed opening, thereby forming the nth first initial hole 11 that penetrates (n-1) stacked material layer groups 2101.

[0163] In step S22, referring to FIG4 , a wet etching liquid may be introduced into the first initial hole 11, thereby selectively etching the first material film layer 2111 laterally, thereby forming a first transverse groove 40 surrounding the first initial hole 11. The first transverse groove 40 is connected to the first initial hole 11.

[0164] As an example, step S23 may include: filling the first initial hole 11 and the first transverse groove 40 with a first isolation material layer 3101 (see FIG5 ). Then, anisotropically etching the first isolation material layer 3101 to remove the first isolation material layer 3101 outside the first transverse groove 40 , leaving the first isolation material layer 3101 within each first transverse groove 40 as the first isolation layer 310 (see FIG6 ).

[0165] At this point, a first isolation material layer 3101 can be first formed on the upper surface of the structure after the first transverse groove 40 is formed, on the first initial hole 11, and within the first transverse groove 40. Then, a chemical mechanical polishing process is performed to remove the first isolation material layer 3101 outside the first initial hole 11 and the first transverse groove 40. Then, using the patterned mask layer 700 having n openings as a mask, anisotropic etching (e.g., dry etching) can be performed on the first initial hole 11 and the first transverse groove 40 to remove the first isolation material layer 3101 outside the first transverse groove 40, thereby forming a first isolation layer 310.

[0166] In other examples, the formation method of the first isolation layer 310 is not limited to this. For example, when the material of the first material film layer 2111 is polysilicon and the second material film layer 2121 is an insulating material layer, after forming the first transverse groove 40, the first material film layer 2111 (polysilicon) exposed by the first transverse groove 40 can also be thermally oxidized to form the first isolation layer 310 surrounding the first initial hole 11.

[0167] In this embodiment, by forming the first transverse groove 40 before forming the first isolation layer 310, and then forming the first isolation layer 310 in the first transverse groove 40, the first isolation layer 310 does not occupy the space of the first initial hole 11, so that the subsequent formation of the second conductive plug 430 can have a smaller impedance.

[0168] In other embodiments, the first isolation layer 310 may be formed in a different manner. For example, when the first material film layer 2111 is made of polysilicon and the second material film layer 2121 is an insulating material layer, after forming the first initial hole 11, the first material film layer 2111 (polysilicon) exposed by the first initial hole 11 may be subjected to a thermal oxidation process to form the first isolation layer 310.

[0169] Meanwhile, as an example, forming n first openings 10 may further include:

[0170] Step S24, referring to FIG. 7 , further etching a stacked material layer group 2101 downward along each first initial hole 11 to form n first openings 10;

[0171] Specifically, anisotropic etching can be performed based on the patterned mask layer 700 to further etch the thickness of one stacked material layer group 2101. After etching, the first initial hole 11 that originally penetrated one or more stacked material layer groups 2101 can further penetrate one stacked material layer group 2101, thereby increasing its thickness and forming a first opening 10. At the same time, the first initial hole 11 that originally penetrated zero stacked material layer groups 2101 can, under the definition of the opening of the patterned mask layer 700, further penetrate one stacked material layer group 2101 downward, thereby forming the first first opening 10.

[0172] Therefore, at this time, the i-th first opening 10 can penetrate a total of i stacked material layer groups 2101 .

[0173] At this time, in the process of forming the connection structure 400 connecting different conductive layers 211 , trimming is only required during the formation of the first initial hole 11 , which can reduce the number of times trimming is used.

[0174] At the same time, a first initial hole 11 is first formed based on the patterned mask layer 700, and then a first isolation layer 310 is formed in the first material film layer 2111 through the first initial hole 11, and then a first opening 10 is formed based on the first initial hole 11, thereby effectively simplifying the process.

[0175] Of course, in other embodiments, the formation method of the first isolation layer 310 and the first opening 10 is not limited to this. For example, first openings 10 of varying depths may be formed, with the i-th first opening 10 penetrating i stacked material layer groups 2101. A filling layer is then formed within each first opening 10 to shield the bottommost stacked material layer group 2101 or the first material film layer 2111 within the stacked material layer group 2101. The first isolation layer 310 is then formed, and the filling layer is subsequently removed.

[0176] In one embodiment, step S40 includes:

[0177] Step S41 , referring to FIG. 9 , continues etching (n−1) stacked material layer groups 2101 along each first opening 10 formed with the first protection layer 610 to form a second initial hole 21 ;

[0178] Step S42 , referring to FIG. 10 , is to perform transverse etching along the second initial hole 21 on each of the first material film layers 2111 exposed by the second initial hole 21 to form a second transverse groove 50 ;

[0179] Step S43 , referring to FIG. 12 , forming a second isolation layer 320 only in the second transverse groove 50 ;

[0180] In step S44 , referring to FIG. 13 , a stacked material layer group 2101 is further etched downwardly along each second initial hole 21 to form n second openings 20 .

[0181] In step S41, referring to FIG9 , anisotropic etching (such as dry etching) can be performed to form the second initial holes 21. Etching of (n-1) stacked material layer groups 2101 continues under each first opening 10, and n second initial holes 21 corresponding to each other are formed under the n first openings 10. The n second initial holes 21 are etched to the same depth under the first openings, so the hole depths of the n second initial holes 21 are the same. At the same time, since the n second initial holes 21 are formed under the different n first openings 10 with a stepped bottom distribution, the positions of the lower surfaces of the n first openings 10 are at different heights, forming a stepped distribution. Therefore, the positions of the lower surfaces of the n second openings 20 are at different heights, forming a stepped distribution.

[0182] In step S42, referring to FIG. 10 , an etching liquid may be introduced into the second initial hole 21 through the first opening 10. Since the sidewalls of the first opening 10 are covered by the first protective layer 610 , a wet selective etching method may be used to laterally etch only the first material film layer 2111 corresponding to the second initial hole 21 , thereby forming a second transverse groove 50 surrounding the second initial hole 21 . The second transverse groove 50 communicates with the second initial hole 21 .

[0183] In this case, the material of the first protective layer 610 can be set to have a high etching selectivity ratio with the first material film layer 2111, so as to prevent the first protective layer 610 and the overlying first material film layer 2111 from being accidentally etched when the first material film layer 2111 is laterally etched to form the second lateral groove 50. Specifically, the first protective layer 610 can be a low-k dielectric constant material or a high-k dielectric constant material. As an example, when the first material film layer 2111 is silicon nitride, the material of the first protective layer 610 can be hafnium oxide (HfO2).

[0184] In step S43, referring to FIG11 , a second isolation material layer 3201 may be first filled into the first opening 10, the second initial hole 21, and the second transverse groove 50. Then, referring to FIG12 , the second isolation material layer 3201 may be anisotropically etched to remove the second isolation material layer 3201 outside the first transverse groove 40, thereby forming a second isolation layer 320.

[0185] Alternatively, after forming the second transverse groove 50 , the first material film layer 2111 (eg, polysilicon) exposed by the second transverse groove 50 may be thermally oxidized to form a second isolation layer 320 surrounding the second initial hole 21 .

[0186] In step S44 , referring to FIG. 13 , anisotropic etching may be used to continue etching to a thickness of the stacked material layer group 2101 .

[0187] In this embodiment, a second isolation layer 320 is first formed in the first material film layer 2111 through the second initial hole 21, and then, based on the second initial hole 21, etching is continued to form the second opening 20 by the thickness of a stacked material layer group 2101, thereby effectively simplifying the process.

[0188] At the same time, in this embodiment, by forming the second lateral groove 50 before forming the second isolation layer 320, and then forming the second isolation layer 320 in the second lateral groove 50, the second isolation layer 320 does not occupy the space of the second initial hole 21, so that the subsequent formation of the first conductive plug 410 and / or the second conductive plug 430 can have a smaller impedance.

[0189] In other embodiments, after forming the second initial hole 21, the first material film layer 2111 (e.g., polysilicon) exposed by the second initial hole 21 may be directly subjected to thermal oxidation treatment to form a second isolation layer 320 surrounding the second initial hole 21. Alternatively, in other embodiments, similar to the description of the first opening 10 above, the second opening 20 may be directly formed by etching.

[0190] In one embodiment, step S60 includes:

[0191] In step S61 , referring to FIG. 15 , the stacked material layer group 2101 below the second opening 20 is etched again along the first opening and the second opening formed with the second protective layer to form a third opening 30 extending to the first substrate 100 .

[0192] Step S62 , referring to FIG. 16 , is to perform transverse etching along the third openings 30 on the first material film layers 2111 exposed by the third openings 30 to form third transverse grooves 60 ;

[0193] In step S63 , referring to FIG. 17 , a third isolation layer 330 is formed only in the third transverse groove 60 .

[0194] In step S61 , referring to FIG. 15 , anisotropic etching (eg, dry etching) may be performed to etch through the stacked material layer group 2101 below the second opening 20 to expose the first substrate 100 , thereby forming a third opening 30 .

[0195] In step S62, referring to FIG. 16 , an etching liquid can be introduced into the third opening 30 through the first opening 10 and the second opening 20. Since the sidewalls of the first opening 10 and the second opening 20 are covered by the second protective layer 620, a wet selective etching method can be used to laterally etch only the first material film layer 2111 corresponding to the third opening 30, thereby forming a third transverse groove 60 surrounding the third opening 30. The third transverse groove 60 is connected to the third opening 30. Therefore, the first material film layer 2111 exposed by the third opening 30 is the first material film layer 2111 exposed by the third transverse groove 60.

[0196] At this time, the material of the second protective layer 620 can be set to a material with a high etching selectivity ratio with the first material film layer 2111, so as to prevent the second protective layer 620 and the upper first material film layer 2111 covered by it from being accidentally etched when the first material film layer 2111 is laterally etched to form the third lateral groove 60. Specifically, the second protective layer 620 can be a low dielectric constant material or a high dielectric constant material. As an example, when the first material film layer 2111 is silicon nitride, the material of the second protective layer 620 can be hafnium oxide (HfO2). The material of the second protective layer 620 can be the same as or different from the material of the first protective layer 610.

[0197] In step S63, referring to FIG17 , a third isolation material layer may be formed in the first opening 10, the second opening 20, the third opening 30, and the third transverse groove 60. Then, the third isolation material layer may be anisotropically etched (e.g., dry-etched) to remove the third isolation material layer outside the third transverse groove 60, thereby forming a third isolation layer 330.

[0198] Alternatively, after forming the third transverse groove 60 , the first material film layer 2111 (eg, polysilicon) exposed by the third transverse groove 60 may be thermally oxidized to form a third isolation layer 330 surrounding the third opening 30 .

[0199] In this embodiment, by forming the third transverse groove 60 before forming the third isolation layer 330, and then forming the third isolation layer 330 in the third transverse groove 60, the third isolation layer 330 does not occupy the space of the third opening 30, so that the subsequent formation of the first conductive plug 410 can have a smaller impedance.

[0200] In other embodiments, after forming the third opening 30 , the first material film layer 2111 (eg, polysilicon) exposed by the third opening 30 may be thermally oxidized to form the third isolation layer 330 .

[0201] In one embodiment, step S70 includes:

[0202] Step S71, referring to FIG. 18 , for each of the n first openings and the second openings connected thereto, the second protective layer and the first protective layer are removed;

[0203] Step S72, forming a first plug material layer in the first opening 10, the second opening 20, and the third opening 30;

[0204] Step S73 , referring to FIG. 19 , the first plug material layer is etched back to be flush with the upper surface of the (n+1)th first material film layer 2111 to form the first conductive plug 410 ;

[0205] Step S74, forming a plug insulating material layer in the first opening 10 and the second opening 20 after forming the first conductive plug 410;

[0206] Step S75 , referring to FIG. 20 , the plug insulating material layer is etched back to be flush with the upper surface of the (n+1)th second material film layer 2121 to form the plug insulating layer 420 ;

[0207] In step S76 , referring to FIG. 21 , the second conductive plug 430 is formed in the first opening 10 and the second opening 20 after the plug insulating layer 420 is formed.

[0208] In step S71 , the second protective layer and the first protective layer may be removed simultaneously by wet etching.

[0209] In step S72 , the material of the first plug material layer may include, but is not limited to, a metal material. The first plug material layer may be formed by physical vapor deposition or chemical vapor deposition.

[0210] In step S73 , the first plug material layer may be etched back by wet etching or dry etching until it is flush with the upper surface of the (n+1)th first material film layer 2111 . The remaining first plug material layer after etching back may form the first conductive plug 410 .

[0211] In step S74 , a plug insulating material layer may be formed by a deposition process.

[0212] In step S75 , the plug insulating material layer may be etched back by wet etching or dry etching until it is flush with the upper surface of the (n+1)th second material film layer 2121 . The remaining plug insulating material layer after etching back may form the plug insulating layer 420 .

[0213] In step S76, a material layer of the second conductive plug 430 may be first deposited, and then chemical mechanical polishing or the like may be performed to form the second conductive plug 430. The material of the second conductive plug 430 may include, but is not limited to, a metal material.

[0214] In this embodiment, the top end of the first conductive plug 410 penetrates the (n+1)th first material film layer 2111. The bottom end of the second conductive plug 430 penetrates the nth first material film layer 2111. Therefore, when the first material film layer 2111 is subsequently replaced or patterned to be transformed into a conductive layer 211, the conductive layer 211 formed by the (n+1)th first material film layer 2111 can be well connected to the first conductive plug 410 corresponding to the first first opening 10, and the conductive layer 211 formed by the nth first material film layer 2111 can be well connected to the second conductive plug 430 corresponding to the nth first opening 10.

[0215] In other embodiments, the connection structure 400 may have a different form. For example, in step S73, the first plug material layer may be etched back to between the upper surface of the (n+1)th first material film layer 2111 and the upper surface of the (n+2)th second material film layer 2121 to form the first conductive plug 410. In this case, the top of the first conductive plug 410 may extend upward to between the upper surface of the (n+1)th first material film layer 2111 and the upper surface of the (n+2)th second material film layer 2121.

[0216] For another example, in step S75, the plug insulating material layer may be etched back to between the upper surface of the (n+1)th second material film layer 2121 and the upper surface of the nth first material film layer 2111 to form the plug insulating layer 420. In this case, the top of the second conductive plug 430 may extend downward to between the upper surface of the (n+1)th second material film layer 2121 and the upper surface of the nth first material film layer 2111.

[0217] It should be understood that although the various steps in the flowchart of FIG1 are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in FIG1 may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0218] In one embodiment, referring to FIG. 23 and FIG. 24 , a semiconductor structure is further provided, which includes a first substrate 100 , a stacked structure 200 , n connection structures 400 , and a plurality of isolation layers.

[0219] The n connecting structures correspond one-to-one to the n through holes, and the n through holes are through holes including the first opening, the second opening, and the third opening. The n through holes correspond one-to-one to the n first openings.

[0220] Among them, the 1st through hole corresponds to the 1st first opening, and so on, the ith through hole corresponds to the ith first opening, and the nth through hole corresponds to the nth first opening.

[0221] Similarly, the first through hole corresponds to the first connection structure, and so on, the ith through hole corresponds to the ith connection structure, and the nth through hole corresponds to the nth connection structure.

[0222] The first base 100 may include a semiconductor substrate 110, and may further include a first peripheral circuit 120 formed based on the semiconductor substrate 110. The first peripheral circuit 120 may include a sense amplifier SA and the like.

[0223] The stacked structure 200 includes 2n stacked layers 210 periodically stacked on the first substrate 100 , where n is a positive integer ≥ 2. The stacked layers 210 include a conductive layer 211 and an insulating isolation layer 212 .

[0224] As an example, an insulating dielectric layer 500 may be further provided between the conductive layer 211 of the first stacked layer group 210 formed on the first substrate 100 and the first substrate 100 .

[0225] The n connection structures 400 are respectively located in n through-holes in different regions on the first substrate 100. The n through-holes respectively penetrate the stacked structure 200 and expose the first substrate 100. Each connection structure 400 includes a first conductive plug 410 located in the corresponding through-hole, a second conductive plug 430, and a plug insulating layer 420 therebetween.

[0226] Each first conductive plug 410 extends from the (n+1)th conductive layer 211 to the 2nth conductive layer 211, for example, to the first substrate 100. The first conductive plug 410 is electrically connected to only one of the conductive layers 211. The first conductive plug 410 connects one of the conductive layers 211 to the first peripheral circuit 120 on the first substrate 100.

[0227] Each second conductive plug 430 extends from the top of the stacked structure 200 to the nth conductive layer 211. Each second conductive plug 430 is electrically connected to only one of the conductive layers 211. The second conductive plug 430 electrically connects one of the conductive layers 211 to the second peripheral circuit 810 above the stacked structure 200. In the i-th connection structure 400, the first conductive plug 410 is connected to the (n+i)th conductive layer 211, and the second conductive plug 430 is connected to the i-th conductive layer 211, where 1≤i≤n.

[0228] As an example, the top of the first conductive plug 410 may penetrate the (n+1)th conductive layer 211 and stop at the lower surface of the plug insulating layer 420 above the (n+1)th conductive layer 211. This ensures that the (n+1)th conductive layer 211 is well electrically connected to the corresponding first conductive plug 410. Of course, the top of the first conductive plug 410 may also extend upward to between the upper surface of the (n+1)th conductive layer 211 and the upper surface of the (n+2)th insulating isolation layer 212.

[0229] As an example, the bottom end of the second conductive plug 430 may penetrate the nth conductive layer 211 and stop at the upper surface of the plug insulating layer 420 above the (n+1)th conductive layer 211. In this case, the nth conductive layer 211 can be well electrically connected to the corresponding second conductive plug 430. Of course, the bottom end of the second conductive plug 430 may also extend downward to between the upper surface of the (n+1)th insulating isolation layer 212 and the upper surface of the nth conductive layer 211.

[0230] A plurality of isolation layers are located on sidewalls of the through hole, and the isolation layers are used to isolate the conductive layers not connected to the first conductive plug and the second conductive plug from the first conductive plug and the second conductive plug.

[0231] Specifically, the plurality of isolation layers may include a plurality of first isolation layers 310 , a plurality of second isolation layers 320 , and a plurality of third isolation layers 330 .

[0232] A plurality of first isolation layers 310 surround the periphery of the remaining connection structures 400, other than the first connection structure 400 electrically connected to the first conductive layer 211. The first isolation layer 310 surrounding the periphery of the i-th connection structure 400 is located at the end of the first (i-1) conductive layer 211 through which the i-th connection structure 400 passes. The first isolation layer 310 is used to isolate the corresponding conductive layer 211 from the second conductive plug 430.

[0233] A plurality of second isolation layers 320 surround the periphery of the connection structure 400. The second isolation layers 320 surrounding each connection structure 400 are located at the ends of the (n-1) conductive layers 211 below the conductive layer 211 electrically connected to the second conductive plug 430. The second isolation layers 320 are used to isolate the corresponding conductive layer 211 from the first conductive plug 410 or the second conductive plug 430.

[0234] The third isolation layer 330 surrounds the periphery of the connection structure 400. The third isolation layer 330 surrounding the periphery of the i-th connection structure 400 is located at the ends of each conductive layer 211 below the (n+i)-th conductive layer 211. The third isolation layer 330 is used to isolate the corresponding conductive layer 211 from the first conductive plug 410.

[0235] In this embodiment, for the n stack groups 210 in the upper portion, each second conductive plug 430 is connected to only one conductive layer 211, and can be effectively insulated and isolated from the other conductive layers 211 by a first isolation layer 310 or a second isolation layer 320 surrounding its periphery and located at the end of the conductive layer 211. Different conductive layers 211 are connected to different second conductive plugs 430. For the n stack groups 210 in the lower portion, each first conductive plug 410 is connected to only one conductive layer 211, and can be effectively insulated and isolated from the other conductive layers 211 by a second isolation layer 320 or a third isolation layer 330 surrounding its periphery and located at the end of the conductive layer 211. Different conductive layers 211 are connected to different first conductive plugs 410. At the same time, a plug insulating layer 420 is provided between the second conductive plugs 430 and the first conductive plugs 410. Therefore, each first conductive plug 410 can be connected to the first peripheral circuit 120 located below (e.g., the first peripheral circuit 120 formed on the first substrate 100), and each second conductive plug 430 can be connected to the second peripheral circuit 810 located above (e.g., the second peripheral circuit 810 formed on the second substrate 800). Therefore, the upper and lower parts of the 2n stacked groups 210 can be connected to peripheral circuits on their upper and lower sides, respectively.

[0236] In one embodiment, the first substrate 100 includes a first peripheral circuit 120, and the semiconductor structure further includes a second substrate 800, on which a second peripheral circuit 810 is disposed. The second peripheral circuit 810 above the stacked structure 200 is located on the second substrate 800 and is electrically bonded to the top of each of the second conductive plugs 430.

[0237] The first peripheral circuit 120 on the first substrate 100 is located below the stacked structure 200 , and the first peripheral circuit 120 is electrically connected to the bottom ends of the first conductive plugs 410 .

[0238] In one embodiment, the conductive layer 211 of the stacked structure includes bit lines extending along a first direction. N connection structures 400 are arranged at intervals in the first direction and penetrate each bit line in a direction perpendicular to the first substrate 100 .

[0239] The stacked structure 200 includes a main body 200a and a branch 200b, wherein the main body 200a extends along a first direction. The branch 200b extends along a second direction. The branch 200b is arranged along the first direction on at least one side of the main body 200a in the second direction. A plurality of branches 200b can be arranged on each side of the main body 200a in the second direction. The conductive layer 211 of the main body 200a can serve as a bit line. The branch 200b can be used to form the source and drain of a transistor, and can form the first capacitor electrode of a capacitor. At this time, the source and drain of the transistor can be connected to the bit line and the first capacitor electrode of the capacitor respectively in the second direction. The transistor and the capacitor form a memory cell.

[0240] When a plurality of branches 200 b are arranged on both sides of the trunk portion 200 a in the second direction, the bit line on the trunk portion 200 a can be shared by the memory cells on both sides thereof.

[0241] The n connection structures 400 penetrate each layer of trunk 200a, that is, each layer of bit lines, so that signals of each layer of bit lines can be introduced and extracted through the first conductive plug 410 and the second conductive plug 430. The n connection structures 400 are arranged along the first direction, thereby facilitating circuit layout.

[0242] In one embodiment, a semiconductor structure is provided, comprising a plurality of signal lines. The plurality of signal lines are periodically stacked on a first substrate, insulated from each other, and extend along a first direction. The plurality of signal lines sequentially include 1st to nth signal lines and n+1th to mth signal lines in a direction approaching the first substrate.

[0243] The signal lines are sequentially arranged from the direction close to the first substrate and named as the 1st signal line, the 2nd signal line, the 3rd signal line, ..., the nth signal line, the (n+1)th signal line, ..., the mth signal line.

[0244] a first peripheral circuit, located in the first substrate and below the plurality of signal lines;

[0245] The second peripheral circuit is located on the second substrate and above the plurality of signal lines; wherein m and n are both positive integers.

[0246] As an example, the semiconductor structure includes a storage structure, such as a memory (e.g., DRAM, NAND, etc.), and the signal lines include bit lines or word lines. For example, referring to FIG. 23 , the plurality of signal lines may be bit lines formed by the conductive layer 211 on the trunk portion 200 a of the stacked structure 200 in FIG. 23 .

[0247] Please refer to FIG. 24 , the first peripheral circuit 120 is located on the first substrate 100 and below the plurality of signal lines.

[0248] The second peripheral circuit 810 is located on the second substrate 800 and above the plurality of signal lines.

[0249] Among the plurality of signal lines, the first to nth signal lines are connected to the second peripheral circuit, and the (n+1)th to mth signal lines are connected to the first peripheral circuit.

[0250] In this embodiment, a plurality of signal lines of the semiconductor structure can be connected to the first peripheral circuit and the second peripheral circuit at the upper and lower sides respectively, thereby effectively simplifying the semiconductor structure and improving storage density.

[0251] In one embodiment, the semiconductor structure includes a plurality of through holes that are spaced apart in the first direction, and each through hole passes through the plurality of signal lines to expose the first peripheral circuit 120 .

[0252] Each of the through holes is filled successively with a first conductive plug 410 and a second conductive plug 430 that are insulated from each other. Each first conductive plug 410 extends from the first peripheral circuit 120 to the (m+1)th signal line, and the second conductive plug 430 extends from the second peripheral circuit 810 to above the first conductive plug 410 and is insulated from the first conductive plug 410 by a plug insulation layer 420 on top of the first conductive plug 410.

[0253] Each of the second conductive plugs is electrically connected to only one signal line among the 1st to nth signal lines; each of the first conductive plugs is electrically connected to only one signal line among the (n+1th) to mth signal lines.

[0254] In one embodiment, only two signal lines electrically connect the first conductive plug and the second conductive plug in each through hole, and n signal lines are spaced between two connection regions electrically connected to the first conductive plug and the second conductive plug in each through hole.

[0255] It is understandable that in other embodiments, in some through holes, there may be only one signal line electrically connected to the first conductive plug or the second conductive plug.

[0256] In one embodiment, the number of the periodically stacked signal lines is 2n, the 1st to nth signal lines are connected to the second conductive plug 430 , and the (n+1)th to 2nth signal lines are connected to the first conductive plug 410 .

[0257] In one embodiment, the first substrate and the second substrate are both silicon substrates, and the second substrate is bonded to the first substrate.

[0258] In one embodiment, an electronic device is also provided, comprising one or more semiconductor structures as described in the above embodiments. Examples of electronic devices include data storage devices, copiers, network equipment, household appliances, instruments, mobile phones, computers, and other devices with data storage capabilities. The electronic device may include a housing, a circuit board disposed within the housing, and a memory or data read / write circuit integrated on the circuit board. For the structure of the memory, please refer to the relevant descriptions in some of the above embodiments. The electronic device may also include other necessary elements or components, which are not limited in the present embodiments.

[0259] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0260] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor structure, comprising: Providing a first substrate, and periodically stacking 2n stacked material layer groups on the first substrate, each of the stacked material layer groups including a first material film layer and a second material film layer, where n is a positive integer ≥ 2; Etching the stacked material layer group to form n first openings with increasing depths, wherein the i-th first opening only penetrates the first to i-th stacked material layer groups in a direction close to the first substrate, 1≤i≤n; among the first material film layers exposed in each first opening, the last first material film layer is exposed, and first isolation layers are provided at ends of the other first material film layers; Continue etching n stacked material layer groups downward from each of the first openings to form a second opening connected to the first opening, wherein the last first material film layer exposed in each of the second openings is exposed, and second isolation layers are provided at ends of the other first material film layers; Continue etching the stacked material layer group downward in each of the second openings until the first substrate is exposed, forming a third opening connected to the second opening, and providing a third isolation layer at the end of each first material film layer exposed in the third opening; A first conductive plug extending to the first substrate is formed in the second opening, and a second conductive plug insulated from the first conductive plug is formed in the first opening.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The 2n first material film layers are 2n sacrificial material layers, and the 2n second material film layers are 2n insulating material layers. After the first conductive plug and the second conductive plug are formed, the method further includes: Replacing the 2n first material film layers in the 2n stacked material layer groups with 2n conductive layers, wherein the 2n conductive layers sequentially include the 1st to nth conductive layers and the n+1th to 2nth conductive layers in a direction close to the first substrate; The first to nth conductive layers are connected to the second conductive plugs in a one-to-one correspondence; The n+1th to 2nth conductive layers are connected to the first conductive plugs in a one-to-one correspondence.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The 2n first material film layers are 2n conductive layers, and the 2n second material film layers are 2n insulating material layers; Periodically stacking 2n stacked material layer groups on the first substrate, comprising: alternately forming 2n conductive layers and 2n insulating material layers on the first substrate; In a direction close to the first substrate, the 2n conductive layers sequentially include the 1st to nth conductive layers and the n+1th to 2nth conductive layers; The first to nth conductive layers are connected to the second conductive plugs in a one-to-one correspondence; The n+1th to 2nth conductive layers are connected to the first conductive plugs in a one-to-one correspondence.

4. The method for preparing a semiconductor structure according to claim 1, wherein: Forming the first isolation layer includes: Anisotropically etching the stacked material layer group in a direction close to the first substrate to form n first initial holes with increasing depths, wherein the i-th first initial hole only penetrates the 1st to (i-1)th stacked material layer groups in a direction close to the first substrate; etching back the first material film layers exposed by the first initial hole by wet etching to form a first transverse groove; The first isolation layer is filled only in each of the first transverse grooves.

5. The method for preparing a semiconductor structure according to claim 4, wherein: Forming the n first openings comprises: One of the stacked material layers is further etched downward along each of the first initial holes to form n first openings.

6. The method for preparing a semiconductor structure according to claim 4, wherein: The step of filling only the first transverse grooves with the first isolation layer includes: depositing a first isolation material layer in the first initial hole and the first transverse groove; The first isolation material layer outside the first transverse groove is removed by anisotropic etching, and the first isolation material layer within the first transverse groove is retained as the first isolation layer.

7. The method for preparing a semiconductor structure according to claim 6, wherein: Forming the second opening and the second isolation layer includes: After forming the first opening, forming a first protective layer located on a sidewall of the first opening, wherein the first protective layer covers the first material film layer and the first isolation layer exposed by the first opening; Continue etching downwards (n-1) of the stacked material layers in the first opening to form a second initial hole; performing transverse etching on each first material film layer exposed by the second initial hole to form a second transverse groove; forming a second isolation layer in the second transverse groove; Continue etching one of the stacked material layers downward along the second initial hole to form the second opening.

8. The method for preparing a semiconductor structure according to claim 7, wherein: Forming the third opening and the third isolation layer includes: forming a second protective layer on a sidewall of the second opening, wherein the second protective layer covers the first material film layer and the second isolation layer exposed by the second opening; Etching the remaining stacked material layer group downward in the second opening to form a third opening extending to the first substrate; performing transverse etching on each first material film layer exposed by the third opening along the third opening to form a third transverse groove; A third isolation layer is formed in each of the third transverse grooves in the third opening.

9. The method for preparing a semiconductor structure according to claim 1, wherein: Forming a first conductive plug extending to the first substrate in the second opening, and forming a second conductive plug insulated from the first conductive plug in the first opening, comprising: depositing a first plug material layer in each of the first openings, the corresponding second openings, and the third openings; In a direction close to the first substrate, etching back each first plug material layer to the (n+1)th first material film layer to form the first conductive plug; forming a plug insulating material layer on top of the first conductive plug; In a direction close to the first substrate, etching the plug insulating material layer back to the (n+1)th second material film layer to form a plug insulating layer; A second plug material layer is deposited in each of the first openings, the second openings, and on the plug insulating material layer, so that the second plug material layer completely fills the first openings.

10. A semiconductor structure comprising: first base; A stacked structure comprising 2n periodically distributed stacked layers stacked on the first substrate, each stacked layer comprising a conductive layer and an insulating isolation layer, where n is a positive integer ≥ 2; The 2n periodically distributed stacked layer groups include: 1st to nth conductive layers and n+1th to 2nth conductive layers sequentially distributed in a direction close to the first substrate; n through holes located in different areas of the first substrate, each of the n through holes passing through the stacked structure and exposing the first substrate; each of the through holes containing a first conductive plug, a plug insulating layer, and a second conductive plug sequentially distributed from a direction close to the first substrate; Each of the first conductive plugs extends from the (n+1)th conductive layer to the 2nth conductive layer and is electrically connected to only one of the conductive layers; Each of the second conductive plugs extends from the first conductive layer to the nth conductive layer and is electrically connected to only one of the conductive layers.

11. The semiconductor structure according to claim 10, wherein Also includes: An isolation layer is located on a sidewall of the through hole, and is used to isolate each conductive layer not connected to the first conductive plug and the second conductive plug from the first conductive plug and the second conductive plug.

12. The semiconductor structure according to claim 10, wherein The conductive layer of the stacked structure includes a bit line extending along a first direction.

13. The semiconductor structure according to claim 10, wherein The semiconductor structure further includes a second substrate; A first peripheral circuit is provided on the first substrate, and the through hole exposes the first peripheral circuit on the first substrate; A second peripheral circuit is provided on the second substrate; The first conductive plug is connected to the second peripheral circuit on the second substrate; The second conductive plug is connected to the first peripheral circuit on the first substrate.

14. The semiconductor structure according to claim 13, wherein: The conductive layer is connected to a bit line, and the first peripheral circuit and the second peripheral circuit include a sense amplifier circuit.

15. A semiconductor structure comprising: A plurality of signal lines are periodically stacked on the first substrate, insulated from each other, and extend along a first direction. Along a direction close to the first substrate, the plurality of signal lines sequentially include 1st to nth signal lines and n+1th to mth signal lines; a first peripheral circuit located in the first substrate and below the plurality of signal lines; a second peripheral circuit, located on the second substrate and above the plurality of signal lines; Among the plurality of signal lines, the 1st to nth signal lines are connected to the second peripheral circuit, and the (n+1)th to (m)th signal lines are connected to the first peripheral circuit; Wherein, m and n are both positive integers.

16. The semiconductor structure according to claim 15, wherein include: a plurality of through holes, spaced apart in the first direction, each through hole passing through the plurality of signal lines and exposing the first peripheral circuit; Each of the through holes is sequentially filled with a first conductive plug and a second conductive plug that are insulated from each other, wherein each of the first conductive plugs extends from the first peripheral circuit to the (m+1)th signal line, and the second conductive plug extends from the second peripheral circuit to above the first conductive plug and is insulated from the first conductive plug by a plug insulation layer on top of the first conductive plug; Each of the second conductive plugs is electrically connected to only one signal line among the 1st to nth signal lines; each of the first conductive plugs is electrically connected to only one signal line among the (n+1th) to mth signal lines.

17. The semiconductor structure according to claim 16, wherein The semiconductor structure includes a memory structure, and the signal line includes a bit line or a word line.

18. The semiconductor structure according to claim 17, wherein Only two signal lines in each through hole are electrically connected to the first conductive plug and the second conductive plug, and n signal lines are spaced between two connection regions in each through hole that are electrically connected to the first conductive plug and the second conductive plug.

19. The semiconductor structure according to claim 18, wherein The number of the periodically stacked signal lines is 2n.

20. The semiconductor structure of claim 15, wherein The first substrate and the second substrate are both silicon substrates, and the second substrate is bonded to the first substrate.

21. An electronic device comprising: The semiconductor structure according to any one of claims 10 to 20.

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