Reverse-conducting lateral insulated gate bipolar transistor

Abstract

The reverse-conducting lateral insulated gate bipolar transistor provided in the embodiment of the present application includes: a drift region formed on a substrate, a gate located on the drift region, an emitter region located on the drift region and close to the gate, and a collector region located on the drift region and away from the gate; wherein, two or more N-well regions are arranged at intervals on the side where the collector region of the drift region is located; a P-well region is arranged between the two or more N-well regions; a P+ contact region is arranged on the N-well region; an N+ contact region is arranged on the P-well region; the P+ contact region and the N+ contact region are both conductively connected to the collector lead end; in this way, not only does the improved device structure not require an additional parallel FWD for current flow, but also the switching characteristics of the entire device are improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a reverse-conducting lateral insulated gate bipolar transistor. Background Art

[0002] A lateral insulated-gate bipolar transistor (LIGBT) combines the advantages of both MOS and bipolar transistors. Silicon-on-insulator (SOI) technology, with its ideal dielectric isolation, is widely used in power integrated circuit manufacturing. SOI-LIGBT devices are LIGBT devices manufactured using SOI technology.

[0003] Intelligent power modules (IPMs) are now widely used in electric motor drives and motor drives. Under medium-power conditions, fully integrated SOI-LIGBTs are often used as the power switching device, and the LIGBT in parallel with a high-voltage freewheeling diode (FWD) is the most classic switching device structure. When the LIGBT is forward-conducting, hole injection generates a large current, driving the inductive load to operate normally. When the LIGBT is turned off, the inductive load cannot change its current suddenly, so a loop is required to continue the current. At this time, the parallel FWD plays a freewheeling role. In the next stage, the LIGBT gate opens, and after reverse recovery, the FWD returns to the off state, completing a working cycle.

[0004] When designing an integrated power module, since LIGBT and FWD are two different types of devices, they need to be highly matched during operation to ensure normal switching characteristics. Therefore, the E when the LIGBT is turned off needs to be considered when designing the device. off The relationship between the trr during FWD reverse recovery is very important, otherwise it is easy to cause excessive loss and long delay, which will affect the reliability of the LIGBT module.

[0005] In order to reduce the turn-off loss, patent document CN111816699A proposes an adaptive SOIL IGBT device, which mainly integrates a Zener diode. Because the Zener diode will adaptively reverse breakdown and conduct as the collector voltage rises, it also provides an additional path for quickly extracting the holes stored in the drift region during the turn-off process; in this patent document, it is also mentioned that the collector structure is a collector NMOS structure, and there is also a second P-type well region, a P+ well potential region, an N+ collector region and a collector trench gate in the N-type buffer layer; the P+ potential region and the P+ well potential region are short-circuited, so that the potential difference between the collector and the P+ well potential region is also small, and an inversion layer cannot be formed in the second P-well region, resulting in the conductive path between the N+ collector region and the N-type buffer layer being blocked, and the device cannot enter the unipolar conduction mode, thereby eliminating the snap-back effect when the device is forward-conducted. However, the structure of this patent document introduces a Zener diode. Since the Zener diode generally has a Zener-type tunnel breakdown, when it is used as a freewheeling diode in a reverse-conducting LIGBT, its use under high-voltage or ultra-high-voltage conditions during reverse breakdown is relatively limited. Moreover, although the Zener diode in this patent document has a certain effect in suppressing the snap-back effect of forward conduction, it cannot achieve a faster recovery characteristic. Due to the setting of its collector structure, the switch turn-off rate of the LIGBT in the reverse recovery stage still needs to be improved. Summary of the Invention

[0006] Based on this, an embodiment of the present application provides a reverse conducting lateral insulated gate bipolar transistor to solve at least one problem existing in the background technology.

[0007] To achieve the above-mentioned object, an embodiment of the present application provides a reverse-conducting lateral insulated gate bipolar transistor, comprising: a drift region formed on a substrate, a gate located on the drift region, an emitter region located on the drift region and close to the gate, and a collector region located on the drift region and away from the gate; wherein,

[0008] Two or more N-well regions are arranged at intervals on one side of the drift region where the collector region is located;

[0009] A P-well region is provided between two or more N-well regions arranged at intervals;

[0010] A P+ contact region is provided on the N-well region;

[0011] An N+ contact region is provided on the P-well region;

[0012] The P+ contact region and the N+ contact region are both conductively connected to the collector lead terminal.

[0013] In an optional embodiment, the two or more spaced-apart N-well regions include at least a first N-well region and a second N-well region; the P-well region includes at least a first P-well region arranged between the first N-well region and the second N-well region; the areas of the first N-well region and the second N-well region are equal, and the first N-well region and the second N-well region are symmetrically distributed relative to the first P-well region.

[0014] In an optional embodiment, along a direction parallel to the plane where the substrate is located, the N+ contact region is surrounded by the P-well region.

[0015] In an optional embodiment, the N+ contact region includes a first part and a second part; the first part includes a sidewall portion and a bottom, the sidewall portion extends in a direction perpendicular to the plane of the substrate, and the bottom is connected to the sidewall portion on a side close to the substrate; the second part is connected to the sidewall portion on a side away from the substrate; the depth of the sidewall portion is greater than the depth of the second part.

[0016] In an optional embodiment, the depth of the sidewall portion is greater than the depth of the P+ contact region.

[0017] In an optional embodiment, a trench is formed in the P-well region; the sidewall portion and the bottom portion of the first part are formed by doping the side surface and the bottom surface of the trench, respectively.

[0018] In an optional embodiment, a filling structure is formed in the trench; and the second portion is located on the filling structure.

[0019] In an optional embodiment, the material of the filling structure includes insulating material and / or polysilicon.

[0020] In an optional embodiment, there are multiple P-well regions, and multiple N+ contact regions are respectively located in the multiple P-well regions; the multiple N+ contact regions and the P+ contact regions are staggered in a plane parallel to the substrate.

[0021] In an optional embodiment, the two or more N-well regions that are spaced apart and the plurality of P-well regions are staggeredly distributed on a plane parallel to the plane where the substrate is located.

[0022] Compared to the prior art, the reverse-conducting lateral insulated gate bipolar transistor provided in the embodiments of the present application includes: a drift region formed on a substrate, a gate located on the drift region, an emitter region located on the drift region and close to the gate, and a collector region located on the drift region and away from the gate; wherein, two or more spaced-apart N-well regions are provided on one side of the drift region where the collector region is located; a P-well region is provided between the two or more spaced-apart N-well regions; a P+ contact region is provided on the N-well region; an N+ contact region is provided on the P-well region; and both the P+ contact region and the N+ contact region are conductively connected to the collector terminal. In this way, by improving the structure of the LIGBT collector region, not only does the improved device structure not require an additional parallel FWD for freewheeling, which can greatly save layout area when the module is in operation and improve the reliability of the LIGBT, but also, due to the spaced-apart N-well region structure, the P-well region is provided between the spaced-apart N-well regions, thereby further improving the switching turn-off rate of the LIGBT during the reverse recovery phase and improving the switching characteristics of the entire device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 is a cross-sectional schematic diagram of a common lateral insulated gate bipolar transistor;

[0025] Figure 2 A schematic cross-sectional view of a reverse-conducting lateral insulated gate bipolar transistor provided in a related embodiment;

[0026] Figure 3 A schematic cross-sectional view of a reverse-conducting lateral insulated gate bipolar transistor provided in the first embodiment;

[0027] Figure 4 A schematic cross-sectional view of a reverse-conducting lateral insulated gate bipolar transistor provided in the second embodiment;

[0028] Figure 5a-5c Schematic top view of the collector region of a reverse conducting lateral insulated gate bipolar transistor in an optional embodiment. DETAILED DESCRIPTION

[0029] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0031] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "in contact with," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0032] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0033] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] First, please refer to Figure 1 . Figure 1 This is a cross-sectional schematic diagram of a common lateral insulated gate bipolar transistor (IGBT). As shown, the lateral insulated gate bipolar transistor comprises: an SOI substrate (including a bottom silicon layer 100, a buried oxide layer 110, and a top silicon layer 120); a drift region 121 located in the top silicon layer 120; a field oxide layer 130; a gate 140; a polysilicon field plate 150 at the collector; an emitter region located on the drift region 121 and close to the gate; and a collector region located on the drift region 121 and away from the gate. The emitter region is provided with a channel region 161, specifically a P-well region, which serves as the conductive channel for the lateral MOS in the LIGBT. A substrate ohmic contact region 171 and a source ohmic contact region 172 are provided on the channel region 161, and both the substrate ohmic contact region 171 and the source ohmic contact region 172 are conductively connected to the emitter terminal. The collector region is provided with an N-type buffer region (hereinafter referred to as N-well region 162 ), and a P+ contact region 173 is provided on the N-well region 162 ; the P+ contact region 173 and the polysilicon field plate 150 are both conductively connected to the collector lead terminal.

[0035] In the above structure, the LIGBT requires a parallel FWD. When the LIGBT is forward-conducting, hole injection creates a large current flow, driving the inductive load to operate normally. When the LIGBT is turned off, the inductive load requires a loop to continue the current because its current cannot change suddenly. At this time, the parallel FWD plays a role in continuing the current. In the next stage, the gate of the LIGBT is opened, and the FWD returns to the cut-off state after reverse recovery, and a working cycle ends. However, since the LIGBT and FWD are two different types of devices, they require a high degree of matching during operation to ensure normal switching characteristics. Therefore, how to integrate the independent FWD with the LIGBT has become an important research direction in this field.

[0036] Considering the above structure, since the collector is P+ (please refer to Figure 1The P+ contact area 173 in the middle makes the LIGBT have no current discharge path and can only flow out from the parallel diode (i.e., FWD); This application first proposes a related embodiment, which provides a reverse conducting lateral insulated gate bipolar transistor. By improving the LIGBT collector structure, the characteristics of the LIGBT during switching are improved. For details, please refer to Figure 2 As shown in the figure, in this related embodiment, in addition to the P+ contact region 173, an N+ contact region 174 is also provided in the N-well region 162, that is, an N+ contact region is added to the collector region; and the lower end of the N+ contact region 174 is surrounded by the P-well region 163. Therefore, when the LIGBT is normally turned on, the holes in the P+ contact region 173 are injected into the N-well region 162 and the drift region 121 to produce a conductivity modulation effect, triggering the PNP transistor and causing the current to rise sharply. The LIGBT enters forward conduction operation. At this time, the N+ contact region 174 and the P-well region 163 are in a reverse bias state, and the electrons cannot cross the depletion layer to form LDMOS. Therefore, when the LIGBT is turned on in the forward direction, it does not affect the normal start-up operation. When the LIGBT is reversely turned off, the collector of the LIGBT loses voltage and becomes zero potential. At this time, since the driven inductive load current cannot change suddenly, the P+ of the emitter (please refer to Figure 2 Compared with the conventional structure in the prior art, the structure provided by the relevant embodiment has an N+ contact area 174, so that there is a current path to return to the coil during freewheeling, so there is no need for an additional parallel FWD for freewheeling, which can greatly save the layout area when the module is working and improve the reliability of the LIGBT.

[0037] However, in Figure 2 In the relevant embodiment shown, the P+ contact region 173, the N+ contact region 174, and the P-well region 163 are all arranged on the same N-well region 162. During the reverse recovery of the LIGBT, the potential barrier that the minority holes need to cross is relatively high, and the switching turn-off rate of the LIGBT during the reverse recovery stage needs to be improved.

[0038] Based on this, the present application proposes the following embodiment: a reverse-conducting lateral insulated gate bipolar transistor comprises: a drift region formed on a substrate, a gate located on the drift region, an emitter region located on the drift region and close to the gate, and a collector region located on the drift region and away from the gate; wherein,

[0039] Two or more N-well regions are arranged at intervals on one side of the drift region where the collector region is located;

[0040] A P-well region is provided between two or more N-well regions arranged at intervals;

[0041] A P+ contact region is provided on the N-well region;

[0042] An N+ contact region is provided on the P-well region;

[0043] The P+ contact region and the N+ contact region are both conductively connected to the collector lead terminal.

[0044] It can be understood that compared with the prior art, the embodiment of the present application improves the structure of the LIGBT collector region, which not only makes the improved device structure do not need an additional parallel FWD for freewheeling, but also can greatly save the layout area when the module is working and improve the reliability of the LIGBT. In addition, due to the spaced N-well region structure, the P-well region is arranged between the spaced N-well regions, thereby further improving the switching turn-off rate of the LIGBT in the reverse recovery phase and improving the switching characteristics of the entire device.

[0045] First, combine Figure 3 The embodiments of the present application are further explained. Figure 3 A cross-sectional schematic diagram of a reverse conducting lateral insulated gate bipolar transistor provided in the first embodiment of the present application; as shown in the figure, the reverse conducting lateral insulated gate bipolar transistor includes: an SOI substrate, namely, a bottom silicon layer 100, a buried oxide layer 110 and a top silicon layer 120.

[0046] The bottom silicon layer 100 has a first conductivity type, specifically, P-type, for example. That is, the bottom silicon layer 100 is a P-type substrate (Psub). Its material is silicon; of course, the present invention is not limited thereto. Commonly used materials in the art, such as silicon carbide, gallium arsenide, indium phosphide, or silicon germanium, can also be used as the material for the bottom substrate of the SOI substrate in the present invention.

[0047] The buried oxide layer 110 is located on the bottom silicon layer 100 and is typically made of silicon oxide, such as silicon dioxide. The buried oxide layer 110 is generally named (BOX) for its function and is specifically an insulating layer. The material of the buried oxide layer 110 may also be other insulating materials, not limited to silicon dioxide.

[0048] The top silicon layer 120 is located on the buried oxide layer 110, and can specifically be an epitaxial layer with a second conductivity type, which serves as a layer for manufacturing devices. The top silicon layer 120 serves as a drift region in the LIGBT device (represented by drift region 121 in the figure). The second conductivity type can specifically be N-type, which serves as a drift region with a conductivity type opposite to that of the bottom silicon layer 100. The drift region 121 is specifically an N-region. The material of the top silicon layer 120 is silicon; of course, the embodiments of the present application are not limited thereto, and materials commonly used in the art, such as silicon carbide, gallium arsenide, indium phosphide or silicon germanium, can also be used as the material of the top substrate of the SOI substrate in the embodiments of the present application.

[0049] A field oxide layer 130 is formed on the drift region 121. The field oxide layer 130 may be made of silicon oxide, such as silicon dioxide. The field oxide layer 130 is the field region of the LIGBT and serves as lateral isolation for the device.

[0050] A gate 140 is formed on the field oxide layer 130 . The gate 140 is made of, for example, polysilicon and serves as the gate of the LIGBT.

[0051] A collector polysilicon field plate 150 is further formed on the field oxide layer 130 , serving as a polysilicon field plate at the collector of the LIGBT.

[0052] Both the channel region 161 and the N-well region 162 are located on the drift region 121 and are spaced apart along the first direction in the figure. The channel region 161 is located near the gate 140 and has a first conductivity type, specifically, a P-well. The channel region 161 forms the conductive channel of the lateral MOS. The N-well region 162 is located away from the gate 140. The N-well region 162 serves as an N-type buffer layer in the collector region of the LIGBT to prevent punch-through.

[0053] Disposed within the channel region 161 are a substrate ohmic contact region 171 of a first conductivity type and a source ohmic contact region 172 of a second conductivity type. The substrate ohmic contact region 171 is a P+ type region, serving as a substrate lead. The source ohmic contact region 172 is an N+ type region, serving as an ohmic contact to the source terminal of the MOS transistor. The source ohmic contact region 172 contacts the channel region 161 on the side facing the gate 140, thereby inducing a channel within the channel region 161.

[0054] On one side of the collector region of the drift region 121 (as shown in the dotted box in the figure), there are two or more N-well regions ( Figure 3 (The first N-well region 1621 and the second N-well region 1622 are shown as examples); the N-well region serves as a buffer zone for the LIGBT. In the reverse-conducting LIGBT provided in this embodiment, the buffer zone is separated into two or more spaced-apart N-well regions, thereby forming independent LIGBT units.

[0055] A P+ contact region 173 is provided on the N-well region. The P+ contact region 173 can also be called a collector ohmic contact region. It serves as the collector ohmic contact of the LIGBT and provides an electrode lead. Specifically, an independent P+ contact region can be provided on each N-well region; each P+ contact region can be as follows: Figure 3 As shown, they are located in the corresponding N-well regions, and the sides and bottom of the P+ contact region are covered by the N-well region; the P+ contact regions can also be located on the corresponding N-well regions, with only the bottom covered by the N-well region.

[0056] A P-well region 163 is provided between two or more spaced-apart N-well regions (eg, between the first N-well region 1621 and the second N-well region 1622 ); the P-well region 163 is a forward-conducting cutoff P-well.

[0057] An N+ contact region 174 is provided on the P-well region 163 ; the N+ contact region 174 serves as an N+ lead of the collector terminal of the LIGBT and is the cathode of the diode generated during reverse conduction.

[0058] As shown in the figure, both the P+ contact region 173 and the N+ contact region 174 are conductively connected to the collector terminal.

[0059] Thus, the emitter, collector, and gate of the LIGBT are shown in the figure.

[0060] Here, a direction perpendicular to the plane where the substrate is located is defined as a third direction, ie, the stacking direction of each layer structure. Two mutually perpendicular first and second directions are defined on a plane parallel to the plane where the substrate is located.

[0061] The embodiment of the present application separates the entire N-well region 162 in the related embodiment into several independent ( Figure 3 Only two N-well regions are shown schematically. In actual application, there may be at least two spaced N-well regions. In this way, not only is there no need for an additional parallel FWD for freewheeling, but the switch turn-off rate during the reverse recovery phase of the LIGBT can also be improved.

[0062] It should be understood that at least a portion of N+ contact region 174 (specifically, the portion excluding the upper surface) is in direct contact with at least a portion of P-well region 163, forming a PN junction therebetween, specifically P / N+. At least a portion of P-well region 163 (including at least the portion where the lower surface is located) is in direct contact with drift region 121, forming a PN junction therebetween, specifically P / N-. The potential barrier between P-well region 163 and drift region 121 is significantly lower than the potential barrier between P-well region 163 and N-well region 162 in the related embodiment.

[0063] Please continue to refer to Figure 3 The two or more spaced N-well regions include at least a first N-well region 1621 and a second N-well region 1622; the P-well region 163 includes at least a first P-well region disposed between the first N-well region 1621 and the second N-well region 1622 (due to Figure 3 The cross section shown has only one P-well region, so the P-well region 163 in the figure can be referred to); the areas of the first N-well region 1621 and the second N-well region 1622 are equal, and the first N-well region 1621 and the second N-well region 1622 are symmetrically distributed relative to the first P-well region.

[0064] Understandably, because the first and second N-well regions have equal areas and are symmetrically distributed relative to the first P-well region, when the device is forward-conducting, current can flow more evenly to each P+ contact region in the collector region, making the device's conduction characteristics more stable. Conversely, if the distribution is asymmetrical or uneven, it can easily cause the device to turn on prematurely before passing through the PNP stage, causing the entire device to lose its conductivity modulation effect and become an LDMOS. The same problem arises during reverse freewheeling. If the distribution is uneven, the freewheeling characteristics of the reverse-conducting diode decrease, the resistance increases, and it is difficult to recover quickly. However, when the first and second N-well regions have equal areas and are symmetrically distributed, the freewheeling characteristics are better and recovery is faster.

[0065] The first N-well region 1621, the first P-well region, and the second N-well region 1622 are arranged sequentially, for example, along a first direction. This first direction is also the direction from the emitter region to the collector region. The first N-well region 1621, the first P-well region, and the second N-well region 1622 can be sequentially adjacent to each other to save area.

[0066] Along a direction parallel to the substrate plane, the N+ contact region 174 is surrounded by the P-well region 163. Understandably, after the P-well region 163 covers the N+ contact region 174, the LIGBT does not experience the snap-back phenomenon (i.e., when the forward voltage reaches a certain level, the voltage decreases as the current increases) during the initial turn-on phase of the LIGBT, unlike conventional LIGBTs. This is because the N+ contact region 174 does not participate in the forward turn-on phase of the LIGBT. At this time, it operates like a penetrating LIGBT, with a low forward conduction voltage drop and, therefore, a smaller Vcesat characteristic. Furthermore, during turn-off, some minority carriers will cross the PN junction barrier formed by the N+ contact region 174 and the P-well region 163 and recombine with the N+ contact region 174, thereby reducing LIGBT tailing and lowering turn-off losses.

[0067] Figure 4 A schematic cross-sectional view of a reverse-conducting lateral insulated gate bipolar transistor according to a second embodiment is shown. As shown, in this embodiment, N+ contact region 174 includes a first portion 1742 and a second portion 1744. First portion 1742 includes a sidewall portion and a bottom portion. The sidewall portion extends perpendicular to the substrate plane, and the bottom portion connects to the sidewall portion on the side closest to the substrate. Second portion 1744 connects to the sidewall portion on the side away from the substrate. The depth of the sidewall portion is greater than that of second portion 1744.

[0068] Here, the bottom of the second portion 1744 and the first portion 1742 can serve as the lateral N+ lead of the LIGBT collector terminal; and the sidewall portion of the first portion 1742 can serve as the longitudinal N+ lead of the LIGBT collector terminal; all of the above serve as the cathode of the diode during reverse conduction.

[0069] This second embodiment further achieves the following beneficial effects: Firstly, the contact area of ​​the N+ in the collector region is increased, namely, the lateral N+ and longitudinal N+, and conductive contact is established on the upper surface of the N+ contact region. Because of the large N+ contact area, the N+ can maximize its role as a reverse diode, significantly enhancing the reverse freewheeling capability of the reverse-conducting LIGBT. Furthermore, during reverse recovery as a diode, the number of minority carrier holes moving along the sidewalls is greater than that along the upper surface, resulting in a shorter path for minority carrier movement, further improving the efficiency of hole recombination, increasing the reverse recovery time trr, and reducing the peak current Irr during reverse recovery. Secondly, the area of ​​the LIGBT collector region can be significantly reduced because the pitch (i.e., spacing) of the structure forming the first portion 1742 (specifically, the trench structure) can be designed to be very small. At the same depth, the N+ implantation area is not reduced. Therefore, by reducing the collector region area, the overall LIGBT area can be reduced.

[0070] In the actual manufacturing process, the first portion 1742 can be formed by first forming a trench in the P-well region 163 and doping the side and bottom surfaces of the trench. Then, the trench is filled and the second portion 1744 is formed on the top of the trench. The doping is performed, for example, by ion implantation.

[0071] In the device structure, a trench is formed within the P-well region 163. The sidewalls and bottom of the first portion 1742 are formed by doping the side and bottom surfaces of the trench, respectively. Thus, the cross-sectional shape of the first portion 1742 can be similar to that of the trench, such as a U-shape.

[0072] A filling structure 180 is formed in the trench; the second portion 1744 is located on the filling structure 180 .

[0073] The material of the aforementioned filling structure 180 includes an insulating material and / or polysilicon. In an alternative embodiment, the material of the filling structure 180 includes an insulating material, specifically, silicon oxide; and polysilicon may be further filled on the insulating material, thereby forming the second portion 1744 in the polysilicon. In another alternative embodiment, polysilicon may be directly filled in the trench, and the second portion 1744 may be formed on the upper surface of the polysilicon.

[0074] Thus, at least a filling material is included between the first portion 1742 and the second portion 1744 , that is, inside the N+ contact region 174 .

[0075] In this embodiment, the depth of the sidewall portion of the first portion 1742 is, for example, greater than the depth of the P+ contact region 173 .

[0076] Figure 5a-5c Schematic top view of the collector region of a reverse conducting lateral insulated gate bipolar transistor in an optional embodiment.

[0077] First, please refer to Figure 5a As shown in the figure, there may be multiple P-well regions, and multiple N+ contact regions are respectively located in the multiple P-well regions; the multiple N+ contact regions and the P+ contact regions are staggered in a plane parallel to the substrate.

[0078] Although the P+ contact region is not explicitly shown here, it is understood that there is a P+ contact region between two adjacent N+ contact regions, regardless of whether along the first direction or the second direction. Furthermore, there is a P+ contact region between two adjacent N+ contact regions, and there is an N+ contact region between two adjacent P+ contact regions.

[0079] and Figure 5b The figure shows a possible scenario where the P+ contact region is located between each N+ contact region, specifically between each P-well region. The P+ contact regions are connected as a whole, and each P-well region and the N+ contact region located within the corresponding P-well region are distributed like islands within the P+ contact region.

[0080] Understandably, compared to a grid-type layout (or matrix array arrangement), a staggered distribution structure is more suitable for applications with high current density. High-current LIGBTs are prone to snap-back in the emitter region, and the staggered layout of N+ and P+ can largely eliminate the conditions for the device to snap back, making it difficult for the PN junction to turn on, thereby improving the safe operating area of ​​the LIGBT.

[0081] because Figure 5a and Figure 5b The situation inside the device (inside the top silicon layer 120) is not shown, so the Figure 5c The middle dashed line represents the N-well region located inside the top silicon layer 120. Figure 5c As shown, two or more spaced-apart N-well regions may be staggered with multiple P-well regions on a plane parallel to the substrate.

[0082] In a specific embodiment, along the first direction, multiple N-well regions and multiple P-well regions are arranged in the manner of "N-well region-P-well region-N-well region..."; along the second direction, multiple N-well regions and multiple P-well regions are also arranged in the manner of "N-well region-P-well region-N-well region..."

[0083] Understandably, even in Figure 5b In the structure shown in FIG. 1 , the P+ contact regions are connected to form a whole on the upper surface of the top silicon layer 120 , and the N-well regions should be spaced apart below the P+ contact regions.

[0084] The N-well region may be adjacent to the P-well region; of course, this application does not exclude the possibility of a gap between the two. On the upper surface of the top silicon layer 120, the P-well region should have an exposed portion; while the N-well region may not be exposed.

[0085] The upper surface mentioned in each embodiment of the present application should be understood as the surface of the corresponding structure away from the substrate; correspondingly, the lower surface should be understood as the surface of the corresponding structure close to the substrate.

[0086] It should be noted that embodiments of the present invention should not be limited to the specific shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present invention.

[0087] In the description of this specification, the reference terms "in one embodiment," "in an alternative embodiment," "in other embodiments," etc., mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0088] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0089] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A reverse conducting lateral insulated gate bipolar transistor, characterized in that: include: A drift region formed on a substrate, a gate located on the drift region, an emitter region located on the drift region and close to the gate, and a collector region located on the drift region and away from the gate; wherein, Two or more N-well regions are arranged at intervals on one side of the drift region where the collector region is located; A P-well region is provided between two or more N-well regions arranged at intervals; A P+ contact region is provided on the N-well region; An N+ contact region is provided on the P-well region; The P+ contact region and the N+ contact region are both conductively connected to the collector lead terminal; The two or more spaced-apart N-well regions include at least a first N-well region and a second N-well region; the P-well region includes at least a first P-well region disposed between the first N-well region and the second N-well region; The first N-well region, the first P-well region, and the second N-well region are arranged in sequence along a direction from the emitter region to the collector region; The areas of the first N-well region and the second N-well region are equal, and the first N-well region and the second N-well region are symmetrically distributed relative to the first P-well region.

2. The reverse conducting lateral insulated gate bipolar transistor according to claim 1, wherein: Along a direction parallel to the plane where the substrate is located, the N+ contact region is surrounded by the P-well region.

3. The reverse conducting lateral insulated gate bipolar transistor according to claim 1, wherein: The N+ contact region includes a first part and a second part; the first part includes a sidewall portion and a bottom, the sidewall portion extends in a direction perpendicular to the plane of the substrate, and the bottom is connected to the sidewall portion on a side close to the substrate; the second part is connected to the sidewall portion on a side away from the substrate; the depth of the sidewall portion is greater than the depth of the second part.

4. The reverse conducting lateral insulated gate bipolar transistor according to claim 3, wherein: The depth of the sidewall portion is greater than the depth of the P+ contact region.

5. The reverse conducting lateral insulated gate bipolar transistor according to claim 3, wherein: A trench is formed in the P-well region; the sidewall portion and the bottom portion of the first portion are formed by doping the side surface and the bottom surface of the trench, respectively.

6. The reverse conducting lateral insulated gate bipolar transistor according to claim 5, wherein: A filling structure is formed in the trench; and the second portion is located on the filling structure.

7. The reverse conducting lateral insulated gate bipolar transistor according to claim 6, wherein: The material of the filling structure includes insulating material and / or polysilicon.

8. The reverse conducting lateral insulated gate bipolar transistor according to claim 1, wherein: There are multiple P-well regions, and multiple N+ contact regions are respectively located in the multiple P-well regions; the multiple N+ contact regions and the P+ contact regions are staggeredly distributed on a plane parallel to the substrate.

9. The reverse conducting lateral insulated gate bipolar transistor according to claim 8, wherein: The two or more N-well regions and the plurality of P-well regions that are spaced apart are staggeredly distributed on a plane parallel to the substrate.

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