Substrate comprising a capacitor configured for power amplifier output matching

Abstract

An apparatus including a substrate and a power amplifier coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects, and a capacitor configured to operate as an output matching element, wherein the capacitor is defined by a plurality of capacitor interconnects. The power amplifier is coupled to the capacitor. The capacitor is configured to operate as an output matching element for the power amplifier. The substrate includes an inductor coupled to the capacitor, wherein the inductor is defined by at least one inductor interconnect. The capacitor and the inductor are configured to operate as a resonant trap or an output matching element.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and interest in non-provisional application serial number 16 / 870,383, filed with the U.S. Patent and Trademark Office on May 8, 2020, the entire contents of which are incorporated herein by reference, as if their entire contents were fully set forth below and used for all applicable purposes. Technical Field

[0003] Various features relate to a substrate including capacitors, but more specifically to a substrate including capacitors configured for power amplifier output matching. Background Technology

[0004] Figure 1 A package 100 is shown, comprising a substrate 102, an integrated device 104, and a power amplifier 106. The substrate 102 includes at least one dielectric layer 120, multiple interconnects 122, and multiple solder interconnects 124. Multiple solder interconnects 144 are coupled to the substrate 102 and the integrated device 104. The power amplifier 106 is coupled to the substrate 102. The power amplifier 106 can generate a significant amount of heat. Heat dissipation of the package 100 has always been a challenge, as it can affect the performance of the package 100. There is a current need for packages with better performance. Summary of the Invention

[0005] Various features relate to a substrate including capacitors, but more specifically to a substrate including capacitors configured for power amplifier output matching.

[0006] One example provides a device including a substrate and a power amplifier coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects, and a capacitor configured to operate as an output matching element, wherein the capacitor is defined by the plurality of capacitor interconnects. The power amplifier is coupled to the capacitor. The capacitor is configured to operate as an output matching element of the power amplifier.

[0007] Another example provides an apparatus including a substrate and devices for coupling a power amplifier to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects, and devices for capacitors, the devices for capacitors being configured to operate as output matching elements. The devices for power amplification are coupled to the devices for capacitors. The devices for capacitors are configured to operate as output matching elements for the devices for power amplification.

[0008] Another example provides a method for manufacturing a device. The method provides a substrate. Providing the substrate includes forming at least one dielectric layer. Providing the substrate includes forming a plurality of interconnects. The method forms a capacitor configured to operate as an output matching element, wherein the capacitor is defined by the plurality of capacitor interconnects. The method couples a power amplifier to the substrate. The power amplifier is coupled to the capacitor. The capacitor is configured to operate as an output matching element of the power amplifier. Attached Figure Description

[0009] When taken in conjunction with the accompanying drawings, various features, properties and advantages will become apparent from the detailed description set forth below, in which similar reference characters are correspondingly used throughout the drawings.

[0010] Figure 1 A cross-sectional view of the package (package) including the integrated device and the substrate is shown.

[0011] Figure 2 A cross-sectional view of the substrate is shown, including capacitors configured for power amplifier output matching.

[0012] Figure 3 A cross-sectional view of another substrate is shown, including capacitors configured for power amplifier output matching.

[0013] Figure 4 A cross-sectional view of another substrate is shown, including capacitors configured for power amplifier output matching.

[0014] Figure 5 A plan view is shown, including a substrate containing capacitors configured for power amplifier output matching.

[0015] Figure 6 An assembly diagram of capacitors configured for power amplifier output matching is shown.

[0016] Figure 7 A plan view of two metal layers configured for power amplifier output matching is shown.

[0017] Figure 8 A plan view of two metal layers configured for power amplifier output matching is shown.

[0018] Figure 9 A cross-sectional view of multiple metal layers configured for power amplifier output matching is shown.

[0019] Figures 10A-10D An exemplary sequence for manufacturing a substrate including a capacitor configured for power amplifier output matching is shown.

[0020] Figure 11An exemplary flowchart is shown for a method of manufacturing a substrate including a capacitor configured for power amplifier output matching.

[0021] Figure 12 A cross-sectional view of a package including an integrated device and a substrate is shown, the substrate including capacitors configured for power amplifier output matching.

[0022] Figure 13 An exemplary sequence for manufacturing a package is shown, the package including an integrated device and a substrate, the substrate including a capacitor configured for power amplifier output matching.

[0023] Figure 14 An exemplary flowchart illustrating a method for manufacturing a package is shown. The package includes an integrated device and a substrate, the substrate including capacitors configured for power amplifier output matching.

[0024] Figure 15 Various electronic devices that can be integrated into the dies, integrated devices, integrated passive devices (IPDs), passive components, packages and / or device packages described herein are shown. Detailed Implementation

[0025] In the following description, specific details are set forth to provide a thorough understanding of various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be represented by block diagrams to avoid obscuring aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of this disclosure.

[0026] This disclosure describes a device including a substrate and a power amplifier coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects, and a capacitor configured to operate as an output matching element, wherein the capacitor is defined by the plurality of capacitor interconnects. The power amplifier is coupled to the capacitor. The capacitor is configured to operate as an output matching element of the power amplifier. The substrate includes an inductor coupled to the capacitor, wherein the inductor is defined by at least one inductor interconnect. The capacitor and inductor may be configured to operate as a resonant trap or an output matching element. An integrated device may be coupled to the substrate. In addition to providing output matching for the power amplifier, the capacitor may be configured to help dissipate heat generated by the power amplifier. This, in turn, helps to improve the performance of the device and / or package.

[0027] An exemplary substrate including a capacitor configured as an output matching element.

[0028] Figure 2A cross-sectional view of a device 200 including a substrate with an embedded capacitor configured to operate as an output matching element of a power amplifier is shown. As will be further described below, the embedded capacitor may be further configured to dissipate heat generated by the power amplifier.

[0029] Device 200 includes a substrate 202 and a power amplifier 206 coupled to the substrate 202. The power amplifier 206 can be configured to amplify at least one electrical signal (e.g., an electrical signal from at least one transmit path). In some implementations, the power amplifier 206 can be configured to be coupled to at least one antenna. The power amplifier 206 can be a device for power amplification. The power amplifier 206 may generate a significant amount of heat that needs to be properly dissipated. As will be further described below, capacitors embedded in the substrate can be coupled to the power amplifier 206 to help dissipate the heat generated by the power amplifier 206.

[0030] The substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 230. Different implementations may use different types of substrates. The substrate 202 may include a multilayer substrate, a coreless substrate (e.g., a coreless embedded trace substrate (ETS)), or a substrate including a core layer.

[0031] The substrate 202 also includes at least one interconnect 232, multiple ground interconnects 234, at least one bottom ground interconnect 246, and a capacitor 250. The capacitor 250 is coupled to the power amplifier 206. The capacitor 250 can be electrically coupled to the power amplifier 206 via at least one interconnect 232. At least one current (e.g., an electrical signal) can travel between the power amplifier 206 and the capacitor 250 via at least one interconnect 232. The capacitor 250 is configured to operate as an output matching element for the power amplifier 206. The output matching provided by the capacitor 250 (e.g., the output matching element) can be impedance matching, which helps to match the output impedance of the power amplifier 206 to the input load of another component (e.g., an integrated device, a die) to maximize energy transfer between the power amplifier 206 and the other component. The capacitor 250 may be defined by multiple capacitor interconnects. The capacitor 250 may be defined by at least one metal layer of the substrate 202. The capacitor 250 may be embedded in the substrate 202. As will be further described below, capacitor 250 may include several rows of grounded capacitor interconnects and several rows of capacitor interconnects interleaved with each other. Capacitor 250 may be a device for capacitance. At least below... Figures 6-8 An example of capacitor 250 is further shown and described in the figure.

[0032] Power amplifier 206 can be coupled to capacitor 250 via multiple ground interconnects 234 and at least one bottom ground interconnect 246. For example, grounding can travel between power amplifier 206 and capacitor 250 via multiple ground interconnects 234 and at least one bottom ground interconnect 246. Note that at least one bottom ground interconnect 246 can be an interconnect located on the lowest metal layer of substrate 202 or an interconnect located on any metal layer of substrate 202. At least one bottom ground interconnect 246 can be an interconnect located on a metal layer below capacitor 250. Power amplifier 206 and / or capacitor 250 can be coupled to other components (e.g., integrated devices, dies) via multiple interconnects 230.

[0033] In addition to providing output matching (e.g., impedance matching), capacitor 250 can be configured as a heat sink to dissipate heat generated by power amplifier 206. The design and / or shape of capacitor 250 enable it to dissipate more heat than another capacitor of similar capacitance (e.g., a surface mount capacitor). For example, a surface mount capacitor with approximately 0.9 picofarads (pF) of capacitance can dissipate heat such that its junction temperature can reach 43 degrees Celsius for approximately 1 watt (W) of power. Conversely, capacitor 250 can have a capacitance of approximately 0.9 picofarads (pF) and can dissipate heat such that its junction temperature (e.g., capacitor junction temperature) can reach a maximum of 23 degrees Celsius for approximately 1 watt (W) of power, which is substantially less than the junction temperature of the surface mount capacitor. In some implementations, junction temperature can be defined as transistor junction temperature. In some implementations, junction temperature can be defined as the temperature of a transistor in a device (directly or indirectly) coupled to the capacitor. In some implementations, junction temperature can be defined as the temperature of the power amplifier. In some implementations, junction temperature can be defined as the temperature of one or more output matching elements (e.g., capacitors, inductors). Therefore, the junction temperature used in this disclosure is not limited to the temperature of a capacitor, but can refer to the temperature of other components.

[0034] Figure 3 A device 300 is shown, comprising a substrate 302 and a power amplifier 206. Device 300 is similar to device 200 and may include components similar to those in device 200. Substrate 302 is similar to substrate 202 and may include components similar to those in substrate 202. Figure 3 As shown, substrate 302 includes at least one dielectric layer 220, a plurality of interconnects 230, at least one interconnect 232, a plurality of ground interconnects 234, at least one bottom ground interconnect 246, a capacitor 250, and an inductor 340. The inductor 340 may be formed from at least one inductor interconnect. The inductor 340 may be formed on at least one metal layer of substrate 302. The inductor 340 may include a spiral inductor.

[0035] Inductor 340 is configured to be coupled (e.g., electrically coupled) to capacitor 250. At least one interconnect may be used to couple inductor 340 to capacitor 250 and vice versa. Capacitor 250 may be located above inductor 340 in a substrate. Both capacitor 250 and inductor 340 may be embedded in substrate 302. The combination of capacitor 250 and inductor 340 may be configured to operate as a resonant trap or output matching element of power amplifier 206. The output matching provided by capacitor 250 and inductor 340 may be impedance matching, which helps to match the output impedance of power amplifier 206 to the input load of another component (e.g., an integrated device, a die) in order to maximize energy transfer between power amplifier 206 and the other component.

[0036] The power amplifier 206 can be coupled to the inductor 340 via a plurality of ground interconnects 234 and at least one bottom ground interconnect 246. For example, grounding can be routed between the power amplifier 206 and the inductor 340 via the plurality of ground interconnects 234 and at least one bottom ground interconnect 246. Note that the at least one bottom ground interconnect 246 can be an interconnect located on the lowest metal layer of the substrate 302 or an interconnect located on any metal layer of the substrate 302. The at least one bottom ground interconnect 246 can be an interconnect located on a metal layer below the inductor 340.

[0037] Power amplifier 206 can be electrically coupled to capacitor 250 via at least one interconnect 232. At least one current (e.g., an electrical signal) can travel between power amplifier 206 and capacitor 250 via at least one interconnect 232. Power amplifier 206, capacitor 250 and / or inductor 340 can be coupled to other components (e.g., integrated devices, chips) via multiple interconnects 230.

[0038] Figure 4 A device 400 is shown, comprising a substrate 402 and a power amplifier 206. Device 400 is similar to device 300 and may include components similar to those in device 300. Substrate 402 is similar to substrate 302 and may include components similar to those in substrate 302. Figure 4 As shown, substrate 402 includes at least one dielectric layer 220, a plurality of interconnects 230, at least one interconnect 232, a plurality of ground interconnects 234, at least one bottom ground interconnect 246, a capacitor 250, and an inductor 340. The inductor 340 may be formed from at least one inductor interconnect. The inductor 340 may be formed on at least one metal layer of substrate 402. The inductor 340 may include a spiral inductor.

[0039] Inductor 340 is configured to be coupled (e.g., electrically coupled) to capacitor 250. At least one interconnect may be used to couple inductor 340 to capacitor 250 and vice versa. Inductor 340 may be located above capacitor 250 in a substrate. Both capacitor 250 and inductor 340 may be embedded in substrate 402. The combination of capacitor 250 and inductor 340 may be configured to operate as a resonant trap or output matching element for power amplifier 206. As described above, the output matching provided by capacitor 250 and inductor 340 may be impedance matching, which helps to match the output impedance of power amplifier 206 to the input load of another component (e.g., an integrated device, a die) in order to maximize energy transfer between power amplifier 206 and the other component.

[0040] The power amplifier 206 can be coupled to the capacitor 250 via a plurality of ground interconnects 234 and at least one bottom ground interconnect 246. For example, grounding can be routed between the power amplifier 206 and the capacitor 250 via the plurality of ground interconnects 234 and at least one bottom ground interconnect 246. Note that the at least one bottom ground interconnect 246 can be an interconnect located on the lowest metal layer of the substrate 402 or an interconnect located on any metal layer of the substrate 402. The at least one bottom ground interconnect 246 can be an interconnect located on a metal layer below the capacitor 250.

[0041] Power amplifier 206 can be electrically coupled to inductor 340 via at least one interconnect 232. At least one current (e.g., an electrical signal) can travel between power amplifier 206 and inductor 340 via at least one interconnect 232. Power amplifier 206, capacitor 250 and / or inductor 340 can be coupled to other components (e.g., integrated devices, chips) via multiple interconnects 230.

[0042] Figure 5 A plan view of a device 500 is shown, including a substrate 302, a capacitor 250, an inductor 340, an inductor 510, an inductor 520, and a capacitor 550. The capacitor 550 may be similar to the capacitor 250, but may have a different shape, a different design, and / or a different size. Inductors 510 and 520 may be coupled to at least one component of the device 500. Inductors 510 and / or 520 may be embedded inductors located in a substrate (e.g., 202, 302, 402).

[0043] Devices 200, 300, 400, and / or 500 may be or may include a package comprising a substrate 202, 302, and / or 402. Devices 200, 300, 400, and / or 500 may be implemented in a radio frequency front-end (RFFE) package.

[0044] Figure 6 An exemplary assembly diagram of capacitor 250 is shown. Capacitor 250 may be formed and / or located on four (4) metal layers of a substrate. However, capacitor 250 may be formed and / or located on at least one metal layer of a substrate. Different embodiments may include capacitors formed on fewer than four metal layers or more than four metal layers.

[0045] The capacitor 250 includes a first ground node 602a on a first metal layer on a substrate (e.g., 202, 302, 402), a first output matching node 602b on a first metal layer on the substrate, a second ground node 603a on a second metal layer on the substrate, a second output matching node 603b on a second metal layer on the substrate, a third ground node 604a on a third metal layer on the substrate, a third output matching node 604b on a third metal layer on the substrate, a fourth ground node 605a on a fourth metal layer on the substrate, and a fourth output matching node 605b on a fourth metal layer on the substrate.

[0046] The first ground node 602a can be coupled to the second ground node 603a (e.g., via a grounding via). The second ground node 603a can be coupled to the third ground node 604a (e.g., via a grounding via). The third ground node 604a can be coupled to the fourth ground node 605a (e.g., via a grounding via). The first output matching node 602b can be coupled to the second output matching node 603b (e.g., via an output matching via). The second output matching node 603b can be coupled to the third output matching node 604b (e.g., via an output matching via). The third output matching node 604b can be coupled to the fourth output matching node 605b (e.g., via an output matching via).

[0047] The grounding nodes of capacitor 250 (e.g., 602a, 603a, 604a, 605a) can be coupled to power amplifier 206 via grounding interconnects, such as... Figure 2 The output matching nodes of capacitor 250 (e.g., 602b, 603b, 604b, 605b) can be coupled to power amplifier 206 via interconnects, as described above. Figure 2 The ground node and / or output matching node of capacitor 250 may be coupled to an inductor (e.g., 340).

[0048] The first ground node 602a includes at least two rows of first ground capacitor interconnects on a first metal layer of the substrate. For example, the first ground node 602a includes first ground capacitor interconnects 620b, 620d, 620f, and 620h. The first output matching node 602b includes at least two rows of first capacitor interconnects on a first metal layer of the substrate. For example, the first output matching node 602b includes first capacitor interconnects 622a, 622c, 622e, and 622g.

[0049] The second ground node 603a includes at least two rows of second ground capacitor interconnects located on a second metal layer of the substrate. For example, the second ground node 603a includes second ground capacitor interconnects 630a, 630c, 630e, and 630g. The second output matching node 603b includes at least two rows of second capacitor interconnects located on a second metal layer of the substrate. For example, the second output matching node 603b includes second capacitor interconnects 632b, 632d, 632f, and 632h.

[0050] The third ground node 604a includes at least two rows of third ground capacitor interconnects located on a third metal layer of the substrate. For example, the third ground node 604a includes third ground capacitor interconnects 640b, 640d, 640f, and 640h. The third output matching node 604b includes at least two rows of third capacitor interconnects located on a third metal layer of the substrate. For example, the third output matching node 604b includes third capacitor interconnects 642a, 642c, 642e, and 642g.

[0051] The fourth ground node 605a includes at least two rows of fourth ground capacitor interconnects located on a fourth metal layer of the substrate. For example, the fourth ground node 605a includes fourth ground capacitor interconnects 650a, 650c, 650e, and 650g. The fourth output matching node 605b includes at least two rows of fourth capacitor interconnects located on a fourth metal layer of the substrate. For example, the fourth output matching node 605b includes fourth capacitor interconnects 652b, 652d, 652f, and 652h.

[0052] Capacitor 250 may include a different number of capacitor interconnects (e.g., a different number of rows of capacitor interconnects). The metal layer on the substrate over which capacitor 250 is formed is arbitrary. Figure 6 In the example, capacitor 250 is formed on layers M2, M3, M4, and M5 of the substrate. However, capacitor 250 can be formed on different metal layers of the substrate.

[0053] The grounding capacitor interconnect rows and capacitor interconnect rows of capacitor 250 can be arranged in a checkerboard pattern, such as... Figure 9As shown and described. The rows of ground capacitor interconnects and capacitor interconnects of capacitor 250 can be arranged in an alternating pattern (e.g., alternating between ground capacitor interconnects and capacitor interconnects). For example, for a given metal layer, the interconnects for the capacitor can alternate between ground capacitor interconnects and capacitor interconnects. Similarly, for a column of interconnects on multiple metal layers, the interconnects for the capacitor can alternate between ground capacitor interconnects and capacitor interconnects. This arrangement of ground capacitor interconnects and capacitor interconnects can help reduce parasitic inductance in capacitor 250, which helps improve the performance of capacitor 250.

[0054] Figure 7 A plan view of a first ground node 602a and a first output matching node 602b of capacitor 250 is shown. The first ground node 602a includes first ground capacitor interconnects 620b, 620d, 620f, and 620h arranged in a row. The first output matching node 602b includes first capacitor interconnects 622a, 622c, 622e, and 622g arranged in a row. The first ground capacitor interconnects and the first capacitor interconnects are disposed on a first metal layer of a substrate such that the first ground capacitor interconnects are staggered (e.g., laterally staggered) with the first capacitor interconnects. For example, the first ground capacitor interconnects and the first capacitor interconnects are formed on the first metal layer such that they alternate back and forth on the first metal layer.

[0055] Figure 7 A plan view of the second ground node 603a and the second output matching node 603b of capacitor 250 is also shown. The second ground node 603a includes second ground capacitor interconnects 630a, 630c, 630e, and 630g arranged in a row. The second output matching node 603b includes second capacitor interconnects 632b, 632d, 632f, and 632h arranged in a row. The second ground capacitor interconnects and the second capacitor interconnects are arranged on a second metal layer of the substrate such that the second ground capacitor interconnects are staggered (e.g., laterally staggered). For example, the second ground capacitor interconnects and the second capacitor interconnects are formed on the second metal layer such that they alternate back and forth on the second metal layer.

[0056] Figure 8 A plan view of the first ground node 602a and the first output matching node 602b, which overlap with the second ground node 603a and the second output matching node 603b, is shown.

[0057] Figure 9A cross-sectional view through a YY section of capacitor 250 is shown. Capacitor 250 includes multiple rows of grounded capacitor interconnects and multiple rows of capacitor interconnects. For a given metal layer, the rows of grounded capacitor interconnects and the rows of capacitor interconnects of capacitor 250 can be arranged in a staggered pattern (e.g., a laterally staggered pattern alternating between grounded capacitor interconnects and capacitor interconnects). For example, for a given metal layer, the interconnects for the capacitor can alternate between grounded capacitor interconnects and capacitor interconnects. Similarly, for a column of interconnects spanning several metal layers (e.g., column A, column B, ..., column H), the interconnects for capacitor 250 can alternate between grounded capacitor interconnects and capacitor interconnects. The pattern of the grounded capacitor interconnects and capacitor interconnects can be a checkerboard pattern.

[0058] like Figure 9 As shown, (i) capacitor interconnect 622a, ground capacitor interconnect 630a, capacitor interconnect 642a and ground capacitor interconnect 650a at least partially overlap vertically, (ii) ground capacitor interconnect 620b, capacitor interconnect 632b, ground capacitor interconnect 640b and capacitor interconnect 652b at least partially overlap vertically, (iii) capacitor interconnect 622c, ground capacitor interconnect 630c, capacitor interconnect 642c and ground capacitor interconnect 650c at least partially overlap vertically, and (iv) ground capacitor interconnect 620d, capacitor interconnect 632d, ground capacitor interconnect 640d and capacitor interconnect 652d at least partially overlap vertically. (v) capacitor interconnect 622e, ground capacitor interconnect 630e, capacitor interconnect 642e and ground capacitor interconnect 650e at least partially vertically overlap; (vi) ground capacitor interconnect 620f, capacitor interconnect 632f, ground capacitor interconnect 640f and capacitor interconnect 652f at least partially vertically overlap; (vii) capacitor interconnect 622g, ground capacitor interconnect 630g, capacitor interconnect 642g and ground capacitor interconnect 650g at least partially vertically overlap; and (viii) ground capacitor interconnect 620h, capacitor interconnect 632h, ground capacitor interconnect 640h and capacitor interconnect 652h at least partially vertically overlap.

[0059] This arrangement of the grounding capacitor interconnects and capacitor interconnects helps reduce the parasitic inductance in capacitor 250, which helps improve the performance of capacitor 250.

[0060] Exemplary sequence for manufacturing the substrate

[0061] In some implementations, the manufacturing substrate involves multiple processes. Figures 10A-10DAn exemplary sequence for providing or manufacturing a substrate including capacitors and inductors is shown. In some implementations, Figures 10A-10D The order can be used for supplying or manufacturing. Figure 3 The substrate is 302. However, Figures 10A-10D The process can be used to manufacture any substrate described in this disclosure.

[0062] It should be noted that Figures 10A-10D The sequence of processes can be combined with one or more stages to simplify and / or clarify the order in which the substrate is provided or manufactured. In some implementations, the sequence of processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the spirit of this disclosure.

[0063] like Figure 10A As shown, stage 1 illustrates the state after a carrier 1000 is provided and a metal layer is formed on the carrier 1000. The metal layer can be patterned to form interconnects 1002. Electroplating and etching processes can be used to form the metal layer and the interconnects.

[0064] Phase 2 illustrates the state after the dielectric layer 1020 is formed over the carrier 1000 and the interconnect 1002. The dielectric layer 1020 may include polyimide. However, different embodiments may use different dielectric layer materials.

[0065] Stage 3 shows the state after the plurality of cavities 1010 are formed in the dielectric layer 1020. The plurality of cavities 1010 can be formed using an etching process (e.g., a photolithography process) or a laser process.

[0066] Stage 4 illustrates the state after interconnects 1012 are formed in and on the dielectric layer 1020. For example, vias, pads, and / or traces may be formed. Electroplating processes may be used to form the interconnects.

[0067] Stage 5 illustrates the state after another dielectric layer 1022 is formed on dielectric layer 1020. Dielectric layer 1022 can be made of the same material as dielectric layer 1020. However, different implementations may use different dielectric layer materials.

[0068] like Figure 10B As shown, stage 6 illustrates the state after multiple cavities 1030 have been formed in the dielectric layer 1022. The cavities 1030 can be formed using an etching process or a laser process.

[0069] Stage 7 illustrates the state after interconnects 1014 are formed in and on the dielectric layer 1022. For example, vias, pads, and / or traces may be formed. Electroplating processes may be used to form the interconnects.

[0070] Stage 8 illustrates the state after another dielectric layer 1024 is formed on dielectric layer 1022. Dielectric layer 1024 can be made of the same material as dielectric layer 1020. However, different implementations may use different dielectric layer materials.

[0071] Stage 9 shows the state after multiple cavities 1040 have been formed in the dielectric layer 1024. The cavities 1040 can be formed using an etching process or a laser process.

[0072] like Figure 10C As shown, stage 10 illustrates the state after interconnects 1016 are formed in and on the dielectric layer 1024. For example, vias, pads, and / or traces may be formed. Electroplating processes may be used to form the interconnects.

[0073] Stage 11 illustrates the state after the formation of dielectric layers (e.g., 1026, 1027, 1028, 1029) and interconnects 1018. In some embodiments, forming the dielectric layers and interconnects 1018 may include an iterative process of forming the dielectric layers, forming cavities in the dielectric layers, and forming over the dielectric layers and cavities. For example, this process may be repeated repeatedly. Figures 10B-10C Stages 8-10 are used to form the dielectric layer and interconnects. The dielectric layer can be formed using deposition processes. The cavity can be formed using etching or laser processes. The interconnects can be formed using electroplating processes.

[0074] Some or all of interconnects 1002, 1012, 1014, 1016 and / or 1018 may define multiple interconnects 230, at least one interconnect 232, multiple ground interconnects 234, at least one bottom ground interconnect 246, capacitors 250 and / or inductors 340. Dielectric layers 1020, 1022, 1024, 1026, 1027, 1028, 1029 may be represented by at least one dielectric layer 220.

[0075] like Figure 10D As shown, stage 12 illustrates the state of the carrier 1000 after it has been decoupled (e.g., removed, ground) from at least one dielectric layer 220 and left the substrate 302. Stage 12 may show the substrate 302 including the capacitor 250 and the inductor 340.

[0076] Different implementations may use different processes to form the metal layer. In some implementations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to form the metal layer. For example, sputtering, spraying, and / or electroplating processes may be used to form the metal layer.

[0077] Exemplary flowchart of a method for manufacturing a substrate

[0078] In some implementations, the manufacturing substrate involves multiple processes. Figure 11 An exemplary flowchart of a method 1100 for providing or manufacturing a substrate is shown. In some implementations, Figure 11 Method 1100 can be used to provide or manufacture Figure 3 The base. For example. Figure 11 The method can be used to manufacture substrate 302.

[0079] It should be noted that Figure 11 The method can combine one or more processes to simplify and / or clarify the methods used to provide or manufacture the substrate. In some implementations, the order of processes can be changed or modified.

[0080] The method provides (at 1105) a carrier 1000. Different embodiments may use different materials for the carrier. The carrier may include a substrate, glass, quartz, and / or a carrier strip. Figure 10A Phase 1 shows an example of the provided carrier.

[0081] This method involves forming a metal layer (at 1110) on a carrier 1000. This metal layer can be patterned to form interconnects. An electroplating process can be used to form the metal layer and the interconnects. Figure 10A Phase 1 shows an example of the formation of metal layers and interconnects.

[0082] The method involves forming a dielectric layer (e.g., 1020) on the carrier 1000 and the interconnect 1002 (at 1115). The dielectric layer 1020 may comprise polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1010) within the dielectric layer (e.g., 1020). The plurality of cavities may be formed using an etching process (e.g., photolithography) or a laser process. Figure 10A Stages 2-3 show examples of dielectric layer and cavity formation.

[0083] This method forms interconnects (at 1120) in and on the dielectric layer. For example, interconnect 1012 may be formed in and on the dielectric layer 1020. Electroplating processes may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Figure 10A Phase 4 shows an example of interconnect formation.

[0084] This method forms (at 1125) an additional dielectric layer (e.g., 1022) over a dielectric layer (e.g., 1020) and interconnects. The dielectric layer (e.g., 1022) may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1030) within the dielectric layer (e.g., 1022). The plurality of cavities may be formed using an etching process or a laser process. This method forms interconnects over the dielectric layer (at 1125). An electroplating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer over and / or within the dielectric layer. Forming the interconnects may include forming a plurality of interconnects 230, at least one interconnect 232, a plurality of ground interconnects 234, at least one bottom ground interconnect 246, a capacitor 250, and an inductor 340. Figures 10A-10C Stages 5-11 illustrate examples of dielectric layer and interconnect formation. Different implementations may use different processes to form the metal layer. In some implementations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to form the metal layer. For example, sputtering, spraying, and / or electroplating processes may be used to form the metal layer.

[0085] Once all dielectric layers and additional interconnects are formed, this method can decouple the carrier (e.g., 1000) from dielectric layer 1020 (at 1130), leaving substrate 302. In some implementations, this method can form a solder mask layer on the substrate. Figure 10D Phase 12 shows an example of carrier decoupling.

[0086] An exemplary package includes a substrate having a capacitor configured as an output matching element.

[0087] Figure 12 A package 1200 is shown, comprising a substrate 302, a power amplifier 206, and an integrated device 1208. The package 1200 can be implemented in a device. The integrated device 1208 is coupled to the substrate 302 via multiple solder interconnects 1210.

[0088] The substrate 302 includes a plurality of interconnects 230, at least one interconnect 232, a plurality of ground interconnects 234, at least one bottom ground interconnect 246, a capacitor 250, and an inductor 340. The inductor 340 may be formed from at least one inductor interconnect. The inductor 340 may be formed on at least one metal layer of the substrate 302. The inductor 340 may include a spiral inductor.

[0089] Inductor 340 is configured to be coupled (e.g., electrically coupled) to capacitor 250. At least one interconnect may be used to couple inductor 340 to capacitor 250 and vice versa. Capacitor 250 may be located above inductor 340 in a substrate. Both capacitor 250 and inductor 340 may be embedded in substrate 302. The combination of capacitor 250 and inductor 340 may be configured to operate as a resonant trap or output matching element of power amplifier 206. The output matching provided by capacitor 250 and inductor 340 may be impedance matching, which helps to match the output impedance of power amplifier 206 to the input load of another component (e.g., integrated device 1208) in order to maximize energy transfer between power amplifier 206 and the other component (e.g., integrated device 1208).

[0090] The power amplifier 206 can be coupled to the inductor 340 via a plurality of ground interconnects 234 and at least one bottom ground interconnect 246. For example, grounding can be routed between the power amplifier 206 and the inductor 340 via the plurality of ground interconnects 234 and at least one bottom ground interconnect 246. Note that the at least one bottom ground interconnect 246 can be an interconnect located on the lowest metal layer of the substrate 302 or an interconnect located on any metal layer of the substrate 302. The at least one bottom ground interconnect 246 can be an interconnect located on a metal layer below the inductor 340.

[0091] Power amplifier 206 can be electrically coupled to capacitor 250 via at least one interconnect 232. At least one current (e.g., an electrical signal) can travel between power amplifier 206 and capacitor 250 via at least one interconnect 232. Power amplifier 206, capacitor 250 and / or inductor 340 can be coupled to integrated device 1208 via multiple interconnects 230.

[0092] The integrated device (e.g., 1208) may include a die (e.g., a bare die). The integrated device may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon carbide (SiC) based integrated devices, memories, and / or combinations thereof.

[0093] Instead of substrate 302, package 1200 may include any substrate described in this disclosure. Package 1200 may be implemented as a radio frequency front-end (RFFE) package.

[0094] An exemplary sequence for manufacturing a package, the package including a substrate having a capacitor configured as an output matching element up to this point.

[0095] Figure 13An exemplary sequence for providing or manufacturing a package is shown, the package including a base having a capacitor configured as an output matching element. In some implementations, Figure 13 The order can be used to provide or manufacture package 1200, or any package described in this disclosure.

[0096] It should be noted that Figure 13 The sequence of processes can be combined with one or more stages to simplify and / or clarify the sequence of processes used to provide or manufacture a package including a substrate with capacitors configured as output matching elements. In some implementations, the process sequence can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the spirit of this disclosure. Figure 13 The order can be used to manufacture one or more packages (as part of a wafer) at a time.

[0097] like Figure 13 As shown, stage 1 illustrates the state after substrate 302 is provided. Substrate 302 includes capacitor 250 and inductor 340. Different implementations can provide different substrates (e.g., 202, 402). Substrate 302 can be provided by a supplier or use, for example... Figures 10A-10D The process described above is used for manufacturing.

[0098] Phase 2 illustrates the state after the integrated device 1208 is coupled to the substrate 302. Solder interconnects can be used to couple the integrated device 1208 to the substrate 302. A reflow process can be used to couple the integrated device 1208 to the substrate 302. The integrated device 1208 can be coupled to the substrate 302 such that the integrated device 1208 is configured to be electrically coupled to the capacitor 250 and the inductor 340.

[0099] Phase 3 illustrates the state after the power amplifier 206 is coupled to the substrate 302. Pick-and-place processes can be used to couple the power amplifier 206 to the substrate 302. The power amplifier 206 can be coupled to the substrate 302 such that the power amplifier 206 is configured to be electrically coupled to the capacitor 250 and the inductor 340. Phase 3 may illustrate a package 1200 including the substrate 302, the power amplifier 206, and the integrated device 1208. The capacitor 250 and the inductor 340 can be embedded in the substrate 302.

[0100] An exemplary flowchart of a method for manufacturing a package, the package including a substrate having a capacitor configured as an output matching element.

[0101] In some implementations, manufacturing a package that includes a substrate with a capacitor configured as an output matching element involves several processes. Figure 14An exemplary flowchart of a method 1400 for providing or manufacturing a package is shown, the package including a substrate having a capacitor configured as an output matching element. In some implementations, Figure 14 Method 1400 can be used to provide or manufacture the invention described in this disclosure. Figure 12 Package 1200. However, method 1400 can be used to provide or manufacture any package described in this disclosure.

[0102] It should be noted that Figure 14 The order of processes can be combined to simplify and / or clarify the methods used to provide or manufacture a package comprising a substrate having a capacitor configured as an output matching element. In some implementations, the order of processes can be changed or modified.

[0103] The method provides (at 1405) a substrate (e.g., 302) comprising a capacitor (e.g., 250) and an inductor (e.g., 340). Different implementations may provide different substrates (e.g., 202, 402). The capacitor may be configured as an output matching element. The capacitor and inductor may be configured as output matching elements, and the capacitor may be configured to aid in heat dissipation. Providing the substrate may include forming at least one dielectric layer, forming a plurality of interconnects, and forming a capacitor configured to operate as an output matching element, wherein the capacitor is defined by a plurality of capacitor interconnects. Figures 10A-10D An example of providing or manufacturing a substrate that includes capacitors and / or inductors is shown. Figure 13 Phase 1 shows an example of a substrate including a capacitor.

[0104] This method couples an integrated device (e.g., 1208) to a substrate (e.g., 302) at 1410. Solder interconnects can be used to couple the integrated device 1208 to the substrate 302. A reflow process can be used to couple the integrated device 1208 to the substrate 302. The integrated device can be coupled (e.g., directly or indirectly) to a capacitor and / or an inductor. Figure 13 Phase 2 shows an example of coupling an integrated device to a substrate.

[0105] This method couples a power amplifier (e.g., 206) to a substrate (e.g., 302) at 1415. Pick-and-place processes can be used to couple the power amplifier 206 to the substrate 302. The power amplifier can be coupled (e.g., directly or indirectly) to a capacitor. The capacitor is configured to operate as an output matching element for the power amplifier. Figure 13 Phase 3 illustrates an example of coupling a power amplifier to a substrate, such that the power amplifier is coupled (e.g., directly or indirectly) to a capacitor.

[0106] Exemplary electronic devices

[0107] Figure 15Various electronic devices are illustrated that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, packages on packages (PoP), systems in packages (SiP), or systems on chips (SoC). For example, mobile phone device 1502, laptop computer device 1504, fixed-location terminal device 1506, wearable device 1508, or motor vehicle 1510 may include device 1500 as described herein. For example, device 1500 may be any of the devices and / or integrated circuit (IC) packages described herein. Figure 15 The devices 1502, 1504, 1506, and 1508 shown, as well as vehicle 1510, are merely exemplary. Other electronic devices may also feature device 1500, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., automobiles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0108] Figures 2-9 , Figures 10A-10D and / or Figures 11-15 One or more of the components, processes, features, and / or functions shown may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may be added without departing from this disclosure. It should also be noted that... Figures 2-9 , Figures 10A-10D and / or Figures 11-15 The corresponding description in this disclosure is not limited to dies and / or ICs. In some implementations, Figures 2-9 , Figures 10A-10D and / or Figures 11-15 The descriptions and their corresponding information can be used to manufacture, create, provide, and / or produce equipment and / or integrated equipment. In some implementations, the equipment may include a die, integrated device, integrated passive device (IPD), die package, integrated circuit (IC) device, device package, integrated circuit (IC) package, wafer, semiconductor device, package-on-package (PoP) device, thermal device, and / or interposer.

[0109] Note that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, these figures may not be drawn to scale. In some cases, not all components and / or parts may be shown for clarity. In some cases, the location, orientation, size, and / or shape of the various parts and / or components in the figures may be exemplary. In some implementations, the various components and / or parts in the figures may be optional.

[0110] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior or advantageous to other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to refer to direct or indirect coupling between two objects. For example, if object A is physically in contact with object B, and object B is in contact with object C, then object A and object C can still be considered coupled to each other—even if they are not in direct physical contact with each other. The term “electrically coupled” can mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can travel between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term “encapsulation” means that an object can partially or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component located at the top can be located above a component positioned at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component located “above” a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, the first component can be located above (e.g., on top) a first surface of the second component, and the third component can be located above (e.g., below) a second surface of the second component, where the second surface is opposite to the first surface. It is also noted that the term “above” as used in this application in the context of one component being above another component can be used to refer to a component located on and / or in another component (e.g., on the surface of the component or embedded in the component). Thus, for example, a first component located above a second component can mean (1) that the first component is above the second component but does not directly contact the second component, (2) that the first component is on the second component (e.g., on the surface of the second component), and / or (3) that the first component is located (e.g., embedded) in the second component. As used in this disclosure, the term "approximately" or "approximately" means within 10% of the value x. For example, a value of approximately 1 or approximately 1 means a value in the range of 0.9 to 1.1.

[0111] In some implementations, an interconnect is a device or packaged element or component that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some implementations, an interconnect may include traces, vias, pads, pillars, redistributed metal layers, and / or under-bump metallization (UBM) layers. In some implementations, an interconnect is a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form the interconnect. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spray coating, and / or electroplating processes may be used to form the interconnect.

[0112] Furthermore, note that the various disclosures contained herein can be illustrated as processes described in flowcharts, flowcharts, structure diagrams, or block diagrams. Although a flowchart may describe operations as a sequential process, many operations can be performed in parallel or simultaneously. Moreover, the order of operations can be rearranged. A process terminates when its operations are completed.

[0113] Various features of the present disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of the disclosure. The description of various aspects of this disclosure is intended to be illustrative and not to limit the scope of the claims. Therefore, the teachings of the invention can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. An apparatus comprising: The substrate includes: At least one dielectric layer; Multiple interconnects; and A capacitor defined by a plurality of capacitor interconnects, wherein the capacitor includes: The first grounding node is located on the first metal layer of the substrate; The first output matching node is located on the first metal layer of the substrate; A second grounding node is located on a second metal layer of the substrate, wherein the second grounding node perpendicularly overlaps with the first output matching node; and A second output matching node is located on the second metal layer of the substrate, wherein the second output matching node vertically overlaps with the first ground node; and A power amplifier, coupled to the substrate, The power amplifier is coupled to the capacitor, and The capacitor is configured to operate as an output matching element of the power amplifier.

2. The device of claim 1, wherein the substrate includes an inductor coupled to the capacitor, wherein the inductor is defined by at least one inductor interconnect.

3. The device of claim 2, wherein the capacitor and the inductor are configured to operate as a resonant trap or the output matching element.

4. The device of claim 2, wherein the power amplifier is coupled to the capacitor via the inductor.

5. The device of claim 2, wherein the power amplifier is coupled to the inductor via the capacitor.

6. The device of claim 1, wherein the substrate includes a plurality of ground interconnects coupled to the capacitor and the power amplifier.

7. The device of claim 6, wherein the plurality of grounding interconnects includes at least one bottom grounding interconnect located in the bottom metal layer of the substrate.

8. The device according to claim 1, The first grounding node includes (i) a first grounding capacitor interconnect located on the first metal layer of the substrate and (ii) a second grounding capacitor interconnect located on the first metal layer of the substrate. The second output matching node includes (i) a first capacitor interconnect located on the second metal layer of the substrate, and (ii) a second capacitor interconnect located on the second metal layer of the substrate. The first capacitor interconnect overlaps perpendicularly with the first ground capacitor interconnect, and The second capacitor interconnect overlaps perpendicularly with the second ground capacitor interconnect.

9. The device according to claim 8, The first output matching node includes (i) a third capacitor interconnect located on the first metal layer of the substrate and (ii) a fourth capacitor interconnect located on the first metal layer of the substrate. The second grounding node includes (i) a third grounding capacitor interconnect located on the second metal layer of the substrate and (ii) a fourth grounding capacitor interconnect located on the second metal layer of the substrate. The third capacitor interconnect overlaps perpendicularly with the third ground capacitor interconnect. The fourth capacitor interconnect overlaps perpendicularly with the fourth ground capacitor interconnect. The vertical overlap between the second grounding node and the first output matching node is at least partially vertical. The vertical overlap between the second output matching node and the first grounding node is at least partially vertical. The first grounding capacitor interconnect, the second grounding capacitor interconnect, the third grounding capacitor interconnect, the fourth grounding capacitor interconnect, the first capacitor interconnect, the second capacitor interconnect, the third capacitor interconnect, and the fourth capacitor interconnect are arranged in a cross-sectional checkerboard pattern.

10. The device of claim 1, wherein the capacitor is configured as a heat sink to dissipate heat generated from the power amplifier.

11. The device of claim 1, wherein when approximately 1 watt of power is provided by the power amplifier, the capacitor comprises a capacitance of 0.9 picofarads (pF), an area of ​​0.4 mm × 0.45 mm, and a capacitor junction temperature of 23 degrees Celsius or lower.

12. The device of claim 1, further comprising an integrated device coupled to the substrate.

13. The device of claim 1, wherein the device is included in the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in automobiles.

14. An apparatus comprising: The substrate includes: At least one dielectric layer; Multiple interconnects; A device for a capacitor, configured to operate as an output matching element, wherein the device for a capacitor includes: The first grounding node is located on the first metal layer of the substrate; The first output matching node is located on the first metal layer of the substrate; A second grounding node is located on a second metal layer of the substrate, wherein the second grounding node perpendicularly overlaps with the first output matching node; and A second output matching node is located on the second metal layer of the substrate, wherein the second output matching node vertically overlaps with the first ground node; and A device for inductance, coupled to the device for capacitance, wherein the device for inductance and the device for capacitance are perpendicularly overlapped; and Devices for power amplification are coupled to the substrate. The device for power amplification is coupled to the device for capacitance, and The device for the capacitor is configured to operate as the output matching element of the device for the power amplification.

15. The apparatus according to claim 14, The vertical overlap between the second grounding node and the first output matching node is at least partially vertical. The vertical overlap between the second output matching node and the first grounding node is at least partially vertical. The interconnects from (i) the first ground node, (ii) the first output matching node, (iii) the second ground node and (iv) the second output matching node are arranged in a cross-sectional checkerboard pattern.

16. The apparatus of claim 14, wherein the device for the capacitor and the device for the inductor are configured to operate as a resonant trap or the output matching element.

17. The apparatus of claim 14, wherein the device for power amplification is coupled to the device for capacitance via the device for inductance.

18. The apparatus of claim 14, wherein the device for power amplification is coupled to the device for inductance via the device for capacitance.

19. The apparatus of claim 14, wherein the substrate includes a plurality of ground interconnects coupled to the device for capacitor and the device for power amplification.

20. The apparatus of claim 14, wherein the apparatus is included in a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in automobiles.

21. A method for manufacturing equipment, the method comprising: Provide a substrate, including: Form at least one dielectric layer; Forming multiple interconnects; and Forming a capacitor, the capacitor being defined by a plurality of capacitor interconnects, wherein forming the capacitor includes: A first grounding node is formed on the first metal layer of the substrate; A first output matching node is formed on the first metal layer of the substrate; A second grounding node is formed on the second metal layer of the substrate such that the second grounding node perpendicularly overlaps with the first output matching node; and A second output matching node is formed on the second metal layer of the substrate such that the second output matching node perpendicularly overlaps with the first ground node; and A power amplifier coupled to the substrate. The power amplifier is coupled to the capacitor, and The capacitor is configured to operate as an output matching element of the power amplifier.

22. The method of claim 21, wherein providing the substrate includes forming an inductor coupled to the capacitor, wherein the inductor is defined by at least one inductor interconnect.

23. The method of claim 22, wherein the capacitor and the inductor are configured to operate as a resonant trap or the output matching element.

24. The method of claim 22, wherein the power amplifier is coupled to the capacitor via the inductor.

25. The method of claim 22, wherein the power amplifier is coupled to the inductor via the capacitor.

26. The method according to claim 21, The formation of the first grounding node includes (i) a first grounding capacitor interconnect formed on the first metal layer of the substrate and (ii) a second grounding capacitor interconnect formed on the first metal layer of the substrate, and The formation of the second output matching node includes (i) a first capacitor interconnect formed on the second metal layer of the substrate, and (ii) a second capacitor interconnect formed on the second metal layer of the substrate. The first capacitor interconnect overlaps perpendicularly with the first ground capacitor interconnect, and The second capacitor interconnect overlaps perpendicularly with the second ground capacitor interconnect.

27. The method according to claim 26, The formation of the first output matching node includes (i) a third capacitor interconnect formed on the first metal layer of the substrate and (ii) a fourth capacitor interconnect formed on the first metal layer of the substrate. The formation of the second grounding node includes (i) a third grounding capacitor interconnect formed on the second metal layer of the substrate and (ii) a fourth grounding capacitor interconnect formed on the second metal layer of the substrate. The third capacitor interconnect overlaps perpendicularly with the third ground capacitor interconnect. The fourth capacitor interconnect overlaps perpendicularly with the fourth ground capacitor interconnect, and The first grounding capacitor interconnect, the second grounding capacitor interconnect, the third grounding capacitor interconnect, the fourth grounding capacitor interconnect, the first capacitor interconnect, the second capacitor interconnect, the third capacitor interconnect, and the fourth capacitor interconnect are arranged in a cross-sectional checkerboard pattern.

Images