Computing system and method of operation thereof

Abstract

A computing system according to the present invention can include a storage device and a host. The storage device can include a plurality of zones. The host can receive, from the storage device, storage area information including an optimal write size of an open zone among the plurality of zones, can determine a target size of data to be flushed to the storage device based on the optimal write size, a history size that is a size of data previously flushed to the storage device, and a size of buffer data of the host, and can flush data corresponding to the target size among the buffer data to the storage device.

Description

Technical Field

[0001] This invention relates to an electronic device, and more specifically, to a computing system and its operating method. Background Technology

[0002] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device can include a memory device for storing data and a memory controller for controlling the memory device. Memory devices are classified into volatile memory devices and non-volatile memory devices.

[0003] Volatile memory devices are memory devices that store data only when powered on and lose the stored data when power is off. Volatile memory devices include Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM).

[0004] Non-volatile memory devices are memory devices that do not lose data even when power is off, including ROM (Read-Only Memory), PROM (Programmable ROM), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), flash memory, etc.

[0005] The host can receive optimal write size information for zones from the storage device for sequential writes and can flush write data to the storage device by resizing it, thereby performing write operations on the storage device that correspond to the optimal write size. The storage device can receive write data corresponding to the optimal write size of the zone from the host and program it immediately, thus reducing the cost associated with write buffer management. Summary of the Invention

[0006] (a) Technical problems to be solved

[0007] Embodiments of the present invention provide a computing system and its operating method, wherein the host adjusts the size of the written data and refreshes it, so that the storage device performs a write operation corresponding to the optimal write size of the area, thereby improving write performance.

[0008] (II) Technical Solution

[0009] A computing system according to an embodiment of the present invention may include a storage device and a host. The storage device may include multiple zones. The host may receive storage region information from the storage device, including the optimal write size of open zones among the multiple zones, and may determine the target size of the data to be flushed to the storage device based on the optimal write size, the historical size of data previously flushed to the storage device, and the size of the host's buffer data, and may flush the data in the buffer data corresponding to the target size to the storage device.

[0010] An operation method for controlling a host comprising a storage device including multiple zones according to an embodiment of the present invention may include the following steps: receiving storage region information from the storage device including the optimal write size of an open zone among the multiple zones; determining the target size of data to be flushed to the storage device based on the optimal write size, a historical size as the size of data previously flushed to the storage device, and the size of the host's buffer data; and flushing the data in the buffer data corresponding to the target size to the storage device.

[0011] (III) Beneficial Effects

[0012] According to this technology, a computing system and its operation method are provided, wherein the host adjusts the size of the write data and refreshes it, so that the storage device performs a write operation corresponding to the optimal write size of the area, thereby improving write performance. Attached Figure Description

[0013] Figure 1 This is a diagram illustrating a computing system according to an embodiment of the present invention.

[0014] Figure 2 It is used for explanation Figure 1 A diagram of the structure of a memory device.

[0015] Figure 3 It is used for explanation Figure 1 A diagram illustrating the structure and operation of a memory device.

[0016] Figure 4 It is a diagram used to illustrate information managed by the host and storage devices to support write operations corresponding to the optimal write size.

[0017] Figure 5 This is a diagram used to illustrate the programming operations of a region according to one embodiment.

[0018] Figure 6A This is a diagram illustrating the programming operation of a zone buffer according to one embodiment.

[0019] Figure 6B This is a diagram illustrating the operation of programming data stored in a zone buffer into a zone according to one embodiment.

[0020] Figure 7 This is a flowchart illustrating a method of operating a host according to one embodiment.

[0021] Figure 8 This is a flowchart illustrating a method of operating a host according to one embodiment.

[0022] Figure 9 This is a flowchart illustrating an operation method of a storage device according to one embodiment.

[0023] Figure 10 This is a flowchart illustrating an operation method of a storage device according to one embodiment.

[0024] Figure 11 This is a flowchart illustrating an operation method of a storage device according to one embodiment.

[0025] Figure 12 It is used for explanation Figure 1 A diagram of another embodiment of the memory controller.

[0026] Figure 13 This is a block diagram illustrating a memory card system using a storage device according to an embodiment of the present invention.

[0027] Figure 14 This is a block diagram illustrating a solid-state drive (SSD) system that utilizes a storage device according to an embodiment of the present invention.

[0028] Figure 15 This is a block diagram illustrating a user system using a storage device according to an embodiment of the present invention.

[0029] Explanation of reference numerals in the attached figures

[0030] 50: Storage devices

[0031] 100: Memory device

[0032] 150a: First storage area

[0033] 150b: Second storage area

[0034] 200: Memory controller

[0035] 210: Write buffer

[0036] 220: Memory Operation Control Unit

[0037] 300: Host

[0038] 310: Host Buffer

[0039] 320: Refresh Control Unit Detailed Implementation

[0040] The specific structural or functional descriptions of embodiments of the concept of the present invention disclosed in this specification or application are merely for the purpose of illustrating embodiments of the concept of the present invention. Embodiments of the concept of the present invention may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0041] Figure 1 This is a diagram illustrating a computing system according to an embodiment of the present invention.

[0042] Reference Figure 1 The computing system may include a storage device 50 and a host 300.

[0043] Storage device 50 may include memory device 100 and memory controller 200 for controlling the operation of memory device. Storage device 50 is a device that stores data under the control of host 300, such as a mobile phone, smartphone, MP3 player, laptop, desktop computer, game console, television, tablet computer, or in-vehicle infotainment system.

[0044] Depending on the host interface used for communication with host 300, storage device 50 can be manufactured as any of various types of storage devices. For example, storage device 50 can be configured as any of various types of storage devices, such as SSD, MMC, eMMC, RS-MMC, micro-MMC multimedia cards; SD, mini-SD, micro-SD secure digital cards; USB (Universal Serial Bus) storage devices, UFS (Universal Flash Storage) devices, PCMCIA (Personal Computer Memory Card International Association) cards; PCI (Peripheral Component Interconnect) cards; PCI-E (PCI-Express) cards; CF (Compact Flash) cards; smart media cards; and memory sticks.

[0045] Storage device 50 can be manufactured in any of various package types. For example, storage device 50 can be manufactured in any of the following package types: POP (package on package), SIP (system-in-package), SOC (system on chip), MCP (multi-chip package), COB (chip on board), WFP (wafer-level fabricated package), and WSP (wafer-level stack package).

[0046] The memory device 100 can store data. The memory device 100 operates in response to the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) comprising a plurality of memory cells for storing data.

[0047] Each memory cell can be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a triple-level cell (TLC) that stores three data bits, or a quad-level cell (QLC) that can store four data bits.

[0048] A memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or for retrieving data stored in the memory device 100.

[0049] A memory block can be a unit used to erase data. In embodiments, the memory device 100 may be DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND flash memory, Vertical NAND flash memory, NOR flash memory, RRAM (resistive random access memory), PRAM (phase-change RAM), MRAM (magnetoresistive random access memory), FRAM (ferroelectric random access memory), or STT-RAM (spintransfer torque random access memory). For ease of explanation, this specification assumes that the memory device 100 is NAND flash memory.

[0050] Memory device 100 is configured to receive commands and addresses from memory controller 200 and access address-selected regions in the memory cell array. That is, memory device 100 can perform operations instructed by commands on address-selected regions. For example, memory device 100 can perform write operations (programming operations), read operations, and erase operations. During a programming operation, memory device 100 programs data into the address-selected region. During a read operation, memory device 100 reads data from the address-selected region. During an erase operation, memory device 100 erases the data stored in the address-selected region.

[0051] In an embodiment, the memory device 100 may include a first storage region 150a and a second storage region 150b. The first storage region 150a may include multiple zones for sequential write operations. Since each zone stores data corresponding to consecutive logical addresses, garbage collection may not be performed. An optimal write size can be set for each zone. The optimal write size may be the size of the maximum data that can be written in a single programming operation. When data corresponding to the optimal write size of an open zone is flushed from the host 300 to the storage device 50, the storage device 50 can directly program the data flushed in the write buffer 210 into the open zone without long-term holding, thereby reducing the maintenance and management costs of the write buffer 210.

[0052] The second storage area 150b may include multiple zone buffers corresponding to each of the multiple zones. A zone buffer may include memory cells that store fewer data bits than the memory cells included in a zone. For example, a zone may include a three-level cell storing three data bits. A zone buffer may include a single-level cell storing one data bit. Because zone buffers store fewer data bits per memory cell compared to zones, they can achieve faster read and write speeds and higher reliability despite their smaller capacity.

[0053] When the size of the data to be stored from the write buffer 210 into the zone is less than the preset write size, the zone buffer can be used for temporary data storage. The preset write size may include the optimal write size.

[0054] The memory controller 200 controls the overall operation of the storage device 50.

[0055] When power is applied to storage device 50, memory controller 200 can execute firmware (FW). When storage device 100 is a flash memory device, memory controller 200 can execute firmware such as Flash Translation Layer (FTL) for controlling communication between host 300 and storage device 100.

[0056] In an embodiment, the memory controller 200 can receive data and a logical block address (LBA) from the host 300 and convert the logical block address into a physical block address (PBA), which represents the address of the memory cell containing the data to be stored in the memory device 100.

[0057] The memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations according to the request of the host 300. During a programming operation, the memory controller 200 can provide the memory device 100 with a write command, a physical block address, and data. During a reading operation, the memory controller 200 can provide the memory device 100 with a read command and a physical block address. During an erasing operation, the memory controller 200 can provide the memory device 100 with an erase command and a physical block address.

[0058] In this embodiment, the memory controller 200 may generate commands, addresses, and data independently of requests from the host 300 and transmit them to the memory device 100. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations such as programming operations for wear leveling or programming operations for garbage collection.

[0059] In this embodiment, the memory controller 200 can control at least two memory devices 100. In this case, the memory controller 200 can control the memory devices 100 in an interleaved manner to improve operational performance. The interleaved manner can be an operational mode in which the operating ranges of at least two memory devices 100 overlap.

[0060] The memory controller 200 can control a plurality of memory devices 100 connected via at least one channel. Each memory device 100 may include at least one plane. Each plane may include a plurality of memory blocks.

[0061] In an embodiment, the memory controller 200 may include a write buffer 210 and a memory operation control unit 220.

[0062] The write buffer 210 can store data refreshed from the host 300. The data stored in the write buffer 210 can be programmed into a zone of the first storage area 150a or a zone buffer of the second storage area 150b.

[0063] The memory operation control unit 220 can provide the host 300 with memory region information including optimal write size information for open regions included in the first memory region 150a. An open region can be one of multiple regions that is active for writing data.

[0064] The memory operation control unit 220 can store data refreshed from the host 300 in the write buffer 210, and can program the data stored in the write buffer 210 into an open area of ​​the first memory region 150a or into a zone buffer corresponding to an open area of ​​the second memory region 150b. Specifically, the memory operation control unit 220 can program the data stored in the write buffer 210 into an open area or a zone buffer corresponding to an open area based on a comparison between the optimal write size and the size of the data stored in the write buffer.

[0065] The memory operation control unit 220 can, in response to a write request received from the host 300, compare the size of the data stored in the write buffer 210 with the optimal write size. When the size of the data stored in the write buffer 210 is greater than or equal to the optimal write size, the memory operation control unit 220 can program the data corresponding to the optimal write size from the data stored in the write buffer 210 into the open area. When the size of the data stored in the write buffer 210 is less than the optimal write size, the memory operation control unit 220 can wait without programming the data stored in the write buffer 210 into the open area until the size of the data stored in the write buffer 210 due to new data refreshed from the host 300 is greater than or equal to the optimal write size.

[0066] The memory operation control unit 220 can program data stored in the write buffer 210 into the area buffer corresponding to the open area in response to a synchronization request received from the host 300. Since the synchronization request is a request to synchronize the storage device 50 and the host 300, the memory operation control unit 220 can program the data into the area buffer even if the size of the data stored in the write buffer 210 is less than the optimal write size.

[0067] The memory operation control unit 220 can reload data stored in the area buffer into the write buffer 210 after performing an operation according to the synchronization request. The memory operation control unit 220 can program data corresponding to the optimal write size from the data loaded into the write buffer 210 and the data newly refreshed into the write buffer 210 from the host 300 into the open area.

[0068] The host 400 can utilize technologies such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed ​​Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnect), PCIe (PCI express), NVMe (NonVolatile Memory Express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), and LRDIMM (Low Load Dual In-line Memory Module). The Reduced DIMM communicates with the storage device 50 using at least one of various communication methods.

[0069] In an embodiment, the host 300 may include a host buffer 310 and a refresh control unit 320.

[0070] The host buffer 310 can store buffer data to be refreshed to the storage device 50.

[0071] The refresh control unit 320 can receive storage region information from the storage device 50, including the optimal write size of the open area included in the first storage region 150a. The refresh control unit 320 can determine the target size of the data to be refreshed to the storage device 50 based on the historical size of the data previously refreshed to the storage device 50, the size of the buffer data stored in the host buffer 310, and the optimal write size.

[0072] For example, the refresh control unit 320 can set the target size based on the historical size and the optimal write size. The refresh control unit 320 can set the initial value of the target size as the value obtained by subtracting the historical size from the optimal write size.

[0073] The refresh control unit 320 can adjust the target size based on a comparison between the target size and the size of the buffer data. When the size of the buffer data is less than the target size, the refresh control unit 320 can initialize the target size value. When the size of the buffer data is equal to the target size, the refresh control unit 320 can maintain the target size value. When the size of the buffer data is greater than the target size, the refresh control unit 320 can adjust the target size value within the range of the buffer data size to a value obtained by adding an integer multiple of the optimal write size to the initial value of the target size.

[0074] The refresh control unit 320 can refresh the data corresponding to the target size in the buffer data stored in the host buffer 310, along with the write request, to the storage device 50. The refresh control unit 320 can update the historical size after the refresh.

[0075] The refresh control unit 320 can provide a synchronization request to the storage device 50 in response to a synchronization event that synchronizes the host 300 and the storage device 50. The refresh control unit 320 can refresh the buffer data stored in the host buffer 310 along with the synchronization request to the storage device 50.

[0076] In this embodiment, the data processed in the host 300 can be managed through a file system. The file system may include a log-structured file system. The refresh control unit 320 may be controlled by the log-structured file system.

[0077] Figure 2 It is used for explanation Figure 1 A diagram of the structure of a memory device.

[0078] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0079] The memory cell array 110 includes multiple memory blocks (BLK1 to BLKz). The multiple memory blocks (BLK1 to BLKz) are connected to the address decoder 121 via row lines (RL). The multiple memory blocks (BLK1 to BLKz) are connected to the read and write circuitry 123 via bit lines (BL1 to BLm). Each of the multiple memory blocks (BLK1 to BLKz) includes multiple memory cells. In an embodiment, the multiple memory cells are non-volatile memory cells. Among the multiple memory cells, memory cells connected to the same word line are defined as a physical page. That is, the memory cell array 110 consists of multiple physical pages. According to an embodiment of the invention, each of the multiple memory blocks (BLK1 to BLKz) included in the memory cell array 110 may include multiple dummy cells. At least one dummy cell may be connected in series between a drain-select transistor and a memory cell, and between a source-select transistor and a memory cell.

[0080] Each of the memory cells in the memory device 100 can be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a triple-level cell (TLC) that stores three data bits, or a quad-level cell (QLC) that can store four data bits.

[0081] The peripheral circuit 120 may include an address decoder 121, a voltage generation unit 122, a read and write circuit 123, a data input / output circuit 124, and a sensing circuit 125.

[0082] Peripheral circuitry 120 drives memory cell array 110. For example, peripheral circuitry 120 can drive memory cell array 110 to perform programming operations, read operations, and erase operations.

[0083] Address decoder 121 is connected to memory cell array 110 via row lines (RL). Row lines (RL) may include drain select lines, word lines, source select lines, and common source lines. According to embodiments of the present invention, word lines may include normal word lines and virtual word lines. According to embodiments of the present invention, row lines (RL) may further include pipe select lines.

[0084] Address decoder 121 is configured to operate in response to control of control logic 130. Address decoder 121 receives address (ADDR) from control logic 130.

[0085] Address decoder 121 is configured to decode block addresses in received address (ADDR). Address decoder 121 selects at least one memory block from memory blocks (BLK1 to BLK2) based on the decoded block address. Address decoder 121 is also configured to decode row addresses in received address (ADDR). Address decoder 121 can select at least one word line from the word lines of the selected memory block based on the decoded row address. Address decoder 121 can apply an operating voltage (Vop) supplied from voltage generation unit 122 to the selected word line.

[0086] During programming operations, address decoder 121 can apply a programming voltage to the selected word line and can apply a pass voltage at a level lower than the programming voltage to the unselected word line. During programming verification operations, address decoder 121 can apply a verification voltage to the selected word line and can apply a verification pass voltage at a level higher than the verification voltage to the unselected word line.

[0087] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and can apply a read voltage higher than the read voltage to the unselected word line.

[0088] According to an embodiment of the present invention, the erase operation of the memory device 100 is performed on a block-by-block basis. During the erase operation, the address (ADDR) input to the memory device 100 includes the block address. The address decoder 121 can decode the block address and select at least one memory block based on the decoded block address. During the erase operation, the address decoder 121 can apply a ground voltage to the word line of the selected memory block.

[0089] According to an embodiment of the present invention, address decoder 121 can be configured to decode column addresses in transmitted address (ADDR). The decoded column addresses can be transmitted to read and write circuitry 123. For example, address decoder 121 may include components such as row decoders, column decoders, and address buffers.

[0090] The voltage generation unit 122 is configured to generate multiple operating voltages (Vop) using the external power supply voltage supplied to the memory device 100. The voltage generation unit 122 operates in response to the control of the control logic 130.

[0091] In this embodiment, the voltage generating unit 122 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generating unit 122 is used as the operating voltage of the memory device 100.

[0092] In this embodiment, the voltage generation unit 122 can generate multiple operating voltages (Vop) using an external power supply voltage or an internal power supply voltage. The voltage generation unit 122 can be configured to generate various voltages required by the memory device 100. For example, the voltage generation unit 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple non-select read voltages.

[0093] The voltage generation unit 122 includes multiple pump capacitors that receive an internal power supply voltage to generate multiple operating voltages (Vop) with different voltage levels, and the voltage generation unit 122 can selectively activate the multiple pump capacitors to generate multiple operating voltages (Vop) in response to the control of the control logic 130. The generated multiple operating voltages (Vop) can be supplied to the memory cell array 110 through the address decoder 121.

[0094] The read and write circuit 123 includes first to m-th page buffers (PB1 to PBm). The first to m-th page buffers (PB1 to PBm) are connected to the memory cell array 110 via first to m-th bit lines (BL1 to BLm), respectively. The first to m-th page buffers (PB1 to PBm) operate in response to the control of the control logic 130.

[0095] The first to m-th page buffers (PB1 to PBm) communicate with the data input / output circuit 124 via data (DATA). During programming operations, the first to m-th page buffers (PB1 to PBm) receive the data to be stored through the data input / output circuit 124 and the data line (DL).

[0096] During programming, when a programming voltage is applied to the selected word line, the first to m-th page buffers (PB1 to PBm) transmit the data to be stored (DATA) received by the data input / output circuit 124 to the selected memory cell via bit lines (BL1 to BLm). The memory cell of the selected page is programmed according to the transmitted data (DATA). The memory cell connected to the bit line to which a programming enable voltage (e.g., ground voltage) is applied has an elevated threshold voltage. The threshold voltage of the memory cell connected to the bit line to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification, the first to m-th page buffers (PB1 to PBm) read the data (DATA) stored in the memory cell from the selected memory cell via bit lines (BL1 to BLm).

[0097] During a read operation, the read and write circuit 123 can read data (DATA) from the memory cell of the selected page via the bit line (BL) and store the read data (DATA) in the first to m-th page buffers (PB1 to PBm).

[0098] During an erase operation, the read and write circuitry 123 can cause the bit lines (BLs) to float. In an embodiment, the read and write circuitry 123 may include column select circuitry.

[0099] The data input / output circuit 124 is connected to the first to m-th page buffers (PB1 to PBm) via data lines (DL). The data input / output circuit 124 operates in response to the control logic 130.

[0100] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data (DATA). During programming operations, the data input / output circuit 124 receives data (DATA) to be stored from an external controller (not shown). During reading operations, the data input / output circuit 124 outputs data (DATA) from the first to the m-th page buffers (PB1 to PBm) included in the read and write circuit 123 to the external controller.

[0101] During a read or verification operation, the sensing circuit 125 can generate a reference current in response to the enable bit (VRYBIT) signal generated by the control logic 130, and can output a pass signal or a failure signal to the control logic 130 by comparing the sensed voltage (VPB) received from the read and write circuit 123 with the reference voltage generated by the reference current.

[0102] Control logic 130 can be connected to address decoder 121, voltage generation unit 122, read and write circuitry 123, data input / output circuitry 124, and sensing circuitry 125. Control logic 130 can be configured to control the overall operation of memory device 100. Control logic 130 can operate in response to commands (CMDs) transmitted from external devices or requests (REQs) received from the memory controller.

[0103] Control logic 130 can generate various signals to control peripheral circuit 120 in response to commands (CMD) and addresses (ADDR). For example, control logic 130 can generate an operation signal (OPSIG), an address (ADDR), read and write circuit control signals (PBSIGNALS), and an enable bit (VRYBIT) in response to commands (CMD) and addresses (ADDR). Control logic 130 can output the operation signal (OPSIG) to the voltage generation unit 122, the address (ADDR) to the address decoder 121, the read and write control signals to the read and write circuit 123, and the enable bit (VRYBIT) to the sensing circuit 125. Furthermore, control logic 130 can determine whether the verification operation has passed or failed in response to a pass / fail signal (PASS / FAIL) output from the sensing circuit 125.

[0104] Figure 3 It is used for explanation Figure 1 A diagram illustrating the structure and operation of a memory device.

[0105] Reference Figure 3 The memory device may include a first storage region 150a and a second storage region 150b. The first storage region 150a may include first to fourth zones (Zone_1 to Zone_4) for which sequential write operations are performed. Data corresponding to consecutive logical addresses may be stored in each zone. An optimal write size (OWS) may be set for each zone. The optimal write size (OWS) may be the maximum data size that can be programmed into the zone in a single programming operation.

[0106] The second storage area 150b may include first to fourth zone buffers (Zone Buffer_1 to Zone Buffer_4) corresponding to the first to fourth zones (Zone_1 to Zone_4), respectively. Compared to memory cells included in zones, each memory cell in a zone buffer can store fewer data bits. Because each memory cell in a zone buffer stores fewer data bits than each memory cell in a zone, the zone buffer, despite its smaller capacity, can achieve faster read and write speeds and higher reliability.

[0107] In one embodiment, the data corresponding to the Optimal Write Size (OWS) stored in the write buffer 210 can be programmed into an open area among multiple areas included in the first storage area 150a. An open area can be one of the multiple areas that is activated for writing data.

[0108] When the size of the data stored in write buffer 210 is less than the optimal write size (OWS), the data stored in write buffer 210 may not be programmed into the first storage area 150a or the second storage area 150b and may remain in write buffer 210 until the size of the data stored in write buffer 210 is greater than or equal to the optimal write size (OWS). However, even if the size of the data stored in write buffer 210 is less than the optimal write size (OWS), when a synchronization request is received to synchronize the storage device and the host, the data stored in write buffer 210 may be programmed into the area buffer corresponding to the open area.

[0109] That is, data smaller than the Optimal Write Size (OWS) can be temporarily programmed into the area buffer. Afterwards, the data programmed into the area buffer can be reloaded into the write buffer 210, and can be programmed into the open area along with the data newly flushed from the host to the write buffer 210 as data corresponding to the Optimal Write Size (OWS).

[0110] Figure 4 It is a diagram used to illustrate information managed by the host and storage devices to support write operations corresponding to the optimal write size.

[0111] Reference Figure 4 Host management information may include OWS_PER_ZONE, Flushed_CNT, Buffered_CNT, and Target_Flush.

[0112] OWS_PER_ZONE can be the optimal write size for an open zone. The optimal write size can be the maximum amount of data that can be written to an open zone in a single programming operation. The host can obtain the OWS_PER_ZONE from the storage zone information received from the storage device.

[0113] Flushed_CNT is the amount of data with a preset size that was previously flushed to the storage device, and can represent the historical size of the data that was previously flushed to the storage device. Flushed_CNT can have values ​​from 0 (zero) to OWS_PER_ZONE-1.

[0114] Buffered_CNT is the amount of data with a preset size stored in the host buffer, representing the size of the buffer data.

[0115] Target_Flush is the amount of data of a preset size to be flushed to the storage device, representing the target size of the data to be flushed to the storage device.

[0116] Information for storage device management may include OWS_PER_ZONE and WB_CNT.

[0117] WB_CNT is the amount of data with a preset size stored in the write buffer, representing the size of the data stored in the write buffer.

[0118] according to Figure 4 In this embodiment, Target_Flush can be determined before performing a flush. The initial value of Target_Flush can be set based on OWS_PER_ZONE and Flushed_CNT. The value of Target_Flush can then be adjusted based on a comparison between Buffered_CNT and the initial value of Target_Flush. After determining the value of Target_Flush, when the value of Target_Flush is greater than 0 (zero) or a synchronization event occurs, the host can flush the data stored in the host buffer to the storage device. The host can update Flushed_CNT after the flush.

[0119] The storage device can program data stored in the write buffer into an open area or into the corresponding area buffer based on the comparison result of WB_CNT and OWS_PER_ZONE. For example, when WB_CNT is greater than or equal to OWS_PER_ZONE, the storage device can program data stored in the write buffer into an open area. When WB_CNT is less than OWS_PER_ZONE and the synchronization event condition is met, the storage device can program data stored in the write buffer into the area buffer.

[0120] Figure 5 This is a diagram used to illustrate the programming operations of a region according to one embodiment.

[0121] Reference Figure 5 Flushed_CNT can be initially set to 0. The range of Flushed_CNT can be from 0 to OWS_PER_ZONE-1. The first to third data items, each with a unit size of 4Kbye, can be stored in the host buffer. Therefore, Buffered_CNT can be 3. Figure 5 In this context, OWS_PER_ZONE can be 12. The unit size of the data, the amount of data stored in the host buffer, and the optimal write size of the open area are not limited to this embodiment.

[0122] Data from the fourth to the thirteenth can be newly stored in the host buffer. Buffered_CNT can be updated from 3 to 13.

[0123] Target_Flush can be initially set to 12 based on OWS_PER_ZONE and Flushed_CNT. Target_Flush is determined to be 12 based on a comparison of the initial values ​​of Buffered_CNT and Target_Flush. Since Target_Flush is greater than 0, the flushing condition is met. The first through twelfth data corresponding to Target_Flush can be flushed from the host to the storage device's write buffer. After flushing, Flushed_CNT can be updated from 0 to 0. Because WB_CNT is the same as OWS_PER_ZONE, the first through twelfth data flushed to the write buffer can be programmed into the open area.

[0124] Figure 5 This illustrates the typical host refresh operation and storage device programming operation. The host can adjust the size of the data to be refreshed by considering the size of data previously refreshed to the storage device. The storage device can receive data from the host corresponding to the optimal write size, thus allowing programming operations to be performed directly on the open area without holding the data refreshed from the host in the write buffer. This reduces the maintenance and management costs of the write buffer and improves the write performance of the storage device.

[0125] Figure 6A This is a diagram illustrating the programming operation of a zone buffer according to one embodiment.

[0126] Reference Figure 6A Flushed_CNT can be initially set to 0. The range of Flushed_CNT can be from 0 to OWS_PER_ZONE-1. The first to third data items, each with a unit size of 4Kbye, can be stored in the host buffer. Therefore, Buffered_CNT can be 3. Figure 6A In this context, OWS_PER_ZONE can be 12. The unit size of the data, the amount of data stored in the host buffer, and the optimal write size of the open area are not limited to this embodiment.

[0127] Target_Flush can be initially set to 12 based on OWS_PER_ZONE and Flushed_CNT. Based on the comparison of the initial values ​​of Buffered_CNT and Target_Flush, Target_Flush can be determined to be 0. Although Target_Flush is not greater than 0, the flush condition can be satisfied due to a synchronization event that synchronizes the storage device and the host. The first to third data corresponding to Buffered_CNT can be flushed from the host to the storage device's write buffer. After flushing, Flushed_CNT can be updated from 0 to 3. Since WB_CNT is less than OWS_PER_ZONE, the first to third data flushed to the write buffer can be programmed into the zone buffer corresponding to the open zone. Buffered_CNT can be updated from 3 to 0.

[0128] Figure 6A This illustrates the host flush operation and storage device programming operation in the event of a synchronization event. When a synchronization event occurs, the data stored in the host should be programmed into the memory device regardless of the value of Target_Flush. Therefore, even if the size of the data flushed from the host is less than the optimal write size, the data should still be programmed, and data stored in the write buffer can be temporarily programmed into the area buffer. This is because if data smaller than the optimal write size is programmed into an open area, the continuity of sequential write operations may be disrupted. Furthermore, since the area buffer stores fewer data bits per memory cell compared to an area, faster read and write operations can be performed, and the response to synchronization events can be faster.

[0129] Figure 6B This is a diagram illustrating the operation of programming data stored in a zone buffer into a zone according to one embodiment.

[0130] Reference Figure 6A and Figure 6B After a synchronization event, the first to third data stored in the zone buffer can be reloaded into the write buffer.

[0131] Data from the fourth to the thirteenth can be newly stored in the host buffer. Buffered_CNT can be updated from 0 to 10.

[0132] Target_Flush can be initially set to 9 based on OWS_PER_ZONE and Flushed_CNT. Based on the comparison between Buffered_CNT and the initial value of Target_Flush, Target_Flush can be determined to be 9. Since Target_Flush is greater than 0, the flushing condition is met. The fourth to twelfth data corresponding to Target_Flush can be flushed from the host to the write buffer of the storage device. After flushing, Flushed_CNT can be updated from 3 to 0.

[0133] Since WB_CNT is the same as OWS_PER_ZONE, the first to third data loaded into the write buffer and the fourth to twelfth data flushed into the write buffer can be programmed into the open area.

[0134] By reference Figure 6A and Figure 6B The illustrated embodiment can maintain sequential write operations for data programmed to correspond to the optimal write size of the open area, even in the event of a synchronization event.

[0135] Figure 7 This is a flowchart illustrating a method of operating a host according to one embodiment.

[0136] Reference Figure 7 In step S701, the host can receive storage area information from the storage device, including the optimal write size of the open area.

[0137] In step S703, the host can determine the target size of the data to be refreshed based on the optimal write size, the size of the data to be refreshed to the storage device, and the size of the data stored in the host buffer.

[0138] In step S705, the host can refresh the data corresponding to the target size in the data stored in the host buffer to the storage device.

[0139] In step S707, the host can update the historical size of the data previously refreshed to the storage device.

[0140] Figure 8 This is a flowchart illustrating a method of operating a host according to one embodiment.

[0141] Reference Figure 8 In step S801, the host can sense the occurrence of a synchronization event that synchronizes the host and the memory device.

[0142] In step S803, the host can refresh the data stored in the host buffer to the storage device.

[0143] In step S805, the host can update the historical size of the data previously refreshed to the storage device.

[0144] Figure 9 This is a flowchart illustrating an operation method of a storage device according to one embodiment.

[0145] Reference Figure 9 In step S901, the storage device may provide the host with storage area information including the optimal write size of the open area.

[0146] In step S903, the storage device may store the data refreshed from the host in the write buffer.

[0147] In step S905, the storage device may program the data stored in the write buffer into the open area or the area buffer based on a comparison of the size of the data stored in the write buffer and the optimal write size, as well as whether a synchronization request has been received.

[0148] Figure 10 This is a flowchart illustrating an operation method of a storage device according to one embodiment.

[0149] Reference Figure 10 In step S1001, the storage device may provide the host with storage area information including the optimal write size of the open area.

[0150] In step S1003, the storage device may store the data refreshed from the host in the write buffer.

[0151] In step S1005, the storage device can determine whether the size of the data stored in the write buffer is greater than or equal to the optimal write size. As a result of the determination, if the size of the data stored in the write buffer is greater than or equal to the optimal write size, step S1007 is executed; if the size of the data stored in the write buffer is less than the optimal write size, step S1009 is executed.

[0152] In step S1007, the storage device can program the data corresponding to the optimal write size from the data stored in the write buffer into the open area.

[0153] In step S1009, the storage device can determine whether it has received a synchronization request from the host. If a synchronization request is received from the host, step S1011 is executed; otherwise, the operation is terminated.

[0154] In step S1011, the storage device can program the data stored in the write buffer into the area buffer corresponding to the open area.

[0155] Figure 11 This is a flowchart illustrating an operation method of a storage device according to one embodiment.

[0156] Reference Figure 11 In step S1101, the storage device can load the data stored in the area buffer into the write buffer.

[0157] In step S1103, the storage device may store the data refreshed from the host in the write buffer.

[0158] In step S1105, the storage device may program data corresponding to the optimal write size from the data stored in the write buffer into the open area. The data stored in the write buffer may include data loaded from the area buffer and data newly refreshed from the host.

[0159] Figure 12 It is used for explanation Figure 1 A diagram of another embodiment of the memory controller.

[0160] Reference Figure 12 The memory controller 1000 is connected to the host and the memory device. The memory controller 1000 is configured to access the memory device in response to requests from the host. For example, the memory controller 1000 is configured to control write, read, erase, and background operations on the memory device. The memory controller 1000 is configured to provide an interface between the memory device and the host. The memory controller 1000 is configured to drive firmware for controlling the memory device.

[0161] The memory controller 1000 may include a processor unit 1010, a memory buffer unit 1020, an error correction unit (ECC) 1030, a host interface 1040, a buffer control circuit 1050, a memory interface 1060, and a bus 1070.

[0162] Bus 1070 can be configured to provide a channel between components of memory controller 1000.

[0163] The processor unit 1010 can control the overall operation of the memory controller 1000 and perform logical operations. The processor unit 1010 can communicate with an external host via the host interface 1040 and with the memory device via the memory interface 1060. Furthermore, the processor unit 1010 can communicate with the memory buffer unit 1020 via the buffer control unit 1050. The processor unit 1010 can control the operation of the storage device by using the memory buffer unit 1020 as operational memory, cache memory, or buffer memory.

[0164] Processor unit 1010 can perform the functions of a Flash Translation Layer (FTL). Processor unit 1010 can translate logical block addresses (LBAs) provided by the host into physical block addresses (PBAs) through the FTL. The FTL can receive logical block addresses (LBAs) using a mapping table and translate them into physical block addresses (PBAs). Depending on the mapping unit, there are various address mapping methods for the FTL. Typical address mapping methods include page mapping, block mapping, and hybrid mapping.

[0165] Processor unit 1010 is configured to randomize data received from the host. For example, processor unit 1010 may use a randomization seed to randomize data received from the host. The randomized data may be provided to a memory device as data to be stored and programmed into a memory cell array.

[0166] Processor unit 1010 is configured to derandomize data received from the memory device during a read operation. For example, processor unit 1010 may use a derandomization seed to derandomize data received from the memory device. The derandomized data will then be output to the host.

[0167] In this embodiment, the processor unit 1010 may perform randomization and derandomization via driver software or firmware.

[0168] The memory buffer unit 1020 can be used as the operating memory, cache memory, or buffer memory of the processor unit 1010. The memory buffer unit 1020 can store code and commands executed by the processor unit 1010. The memory buffer unit 1020 can store data processed by the processor unit 1010. The memory buffer unit 1020 may include SRAM (static RAM) or DRAM (dynamic RAM).

[0169] Error correction unit 1030 can perform error correction. Error correction unit 1030 can perform error correction encoding (ECC encoding) based on data to be written to the memory device via memory interface 1060. The error-corrected data can be transmitted to the memory device via memory interface 1060. Error correction unit 1030 can perform error correction decoding (ECC decoding) on ​​data received from the memory device via memory interface 1060. For example, error correction unit 1030 can be included as a component of memory interface 1060.

[0170] The host interface 1040 can communicate with an external host under the control of the processor unit 1010. The host interface 1040 can be configured to utilize technologies such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed ​​Interchip Interconnect), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnect), PCIe (PCI express), NVMe (NonVolatile Memory Express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), and RDIMM (Registered Dual In-line Memory Module). It communicates using at least one of the following communication methods: DIMM (Load Reduced DIMM) and LRDIMM (Load Reduced DIMM).

[0171] The buffer control unit 1050 is configured to control the memory buffer unit 1020 under the control of the processor unit 1010.

[0172] The memory interface 1060 is configured to communicate with the memory device under the control of the processor unit 1010. The memory interface 1060 can transmit commands, addresses, and data to the memory device via channels.

[0173] For example, the memory controller 1000 may not include the memory buffer unit 1020 and the buffer control unit 1050.

[0174] For example, processor unit 1010 can use code to control the operation of memory controller 1000. Processor unit 1010 can load code from a non-volatile memory device (e.g., read-only memory) disposed within memory controller 1000. As another example, processor unit 1010 can load code from a memory device via memory interface 1060.

[0175] For example, the bus 1070 of the memory controller 1000 can be divided into a control bus and a data bus. The data bus can be configured to transmit data within the memory controller 1000, and the control bus can be configured to transmit control information such as commands and addresses within the memory controller 1000. The data bus and the control bus are separate and can operate independently without interference. The data bus can be connected to the host interface 1040, the buffer control unit 1050, the error correction unit 1030, and the memory interface 1060. The control bus can be connected to the host interface 1040, the processor unit 1010, the buffer control unit 1050, the memory buffer unit 1020, and the memory interface 1060.

[0176] Figure 13 This is a block diagram illustrating a memory card system using a storage device according to an embodiment of the present invention.

[0177] Reference Figure 13 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0178] Memory controller 2100 is connected to memory device 2200. Memory controller 2100 is configured to access memory device 2200. For example, memory controller 2100 may be configured to control read, write, erase, and background operations of memory device 2200. Memory controller 2100 is configured to provide an interface between memory device 2200 and a host. Memory controller 2100 is configured to drive firmware for controlling memory device 2200. Memory controller 2100 may be configured to reference... Figure 1 The memory controller 200 described is implemented in the same way.

[0179] For example, the memory controller 2100 may include components such as RAM (random access memory), a processing unit, a host interface, a memory interface, and an error correction unit.

[0180] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) according to specific communication standards. For example, the memory controller 2100 can be configured to communicate with external devices via at least one of various communication standards such as USB (Universal Serial Bus), MMC (MultiMedia Card), eMMC (embedded MMC), PCI (Peripheral Component Interconnect), PCI-E (PCIexpress), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (Small Computer System Interface), ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, and NVMe. For example, the connector 2300 can be defined by at least one of the aforementioned communication standards.

[0181] For example, the memory device 2200 can be configured as a variety of non-volatile memory devices such as EEPROM (Electrically Erasable and Programmable ROM), NAND flash memory, NOR flash memory, PRAM (Phase-change RAM), ReRAM (Resistive RAM), FRAM (Ferroelectric RAM), and STT-MRAM (Spin Transfer Torque Magnetic RAM).

[0182] The memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), CF card, smart media card (SM, SMC), Memory Stick, multimedia card (MMC, RS-MMC, MMCmicro, eMMC), SD card (SD, miniSD, microSD, SDHC), or Universal Flash Memory (UFS).

[0183] Figure 14 This is a block diagram illustrating a solid state drive (SSD) system that utilizes a storage device according to an embodiment of the present invention.

[0184] Reference Figure 14 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 transmits signals (SIG) to and receives signals (SIG) from the host 3100 via a signal connector 3001, and receives power (PWR) via a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memory modules 3221-322n, an auxiliary power supply unit 3230, and a cache memory 3240.

[0185] According to an embodiment of the present invention, the SSD controller 3210 can perform reference... Figure 1 The functions of the memory controller 200 are described.

[0186] SSD controller 3210 can control multiple flash memory modules 3221-322n in response to a signal (SIG) received from host 3100. For example, the signal (SIG) can be a signal based on the interface between host 3100 and SSD 3200. For example, a signal (SIG) can be defined by at least one of the following interfaces: USB (Universal Serial Bus), MMC (MultiMediaCard), eMMC (embedded MMC), PCI (Peripheral Component Interconnect), PCI-E (PCI express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (Small Computer System Interface), ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), Wi-Fi, Bluetooth, and NVMe.

[0187] Auxiliary power supply unit 3230 is connected to host 3100 via power connector 3002. Auxiliary power supply unit 3230 can receive power (PWR) from host 3100 and charge it. When the power supply from host 3100 is unreliable, auxiliary power supply unit 3230 can supply power to SSD 3200. For example, auxiliary power supply unit 3230 can be located inside or outside SSD 3200. For example, auxiliary power supply unit 3230 can also be located on the motherboard to supply auxiliary power to SSD 3200.

[0188] Buffer memory 3240 operates as a buffer memory for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memory modules 3221-322n, or buffer memory 3240 may temporarily store metadata (e.g., mapping tables) of flash memory modules 3221-322n. Buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0189] Figure 15 This is a block diagram illustrating a user system using a storage device according to an embodiment of the present invention.

[0190] Reference Figure 15 The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0191] Application processor 4100 can drive components, operating systems (OS), or user programs included in user system 4000. For example, application processor 4100 may include controllers, interfaces, and graphics engines that control components included in user system 4000. Application processor 4100 may be provided as a system-on-a-chip (SoC).

[0192] The memory module 4200 can operate as the main memory, operating memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged based on POP (Package on Package) and provided as a single semiconductor package.

[0193] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communication), WCDMA (Wideband CDMA), CDMA-2000, TDMA (Time Division Multiple Access), LTE (Long Term Evolution), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, network module 4300 can be included in application processor 4100.

[0194] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can transfer data stored in storage module 4400 to application processor 4100. For example, storage module 4400 can be implemented as a non-volatile semiconductor memory device such as PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), NAND flash memory, NOR flash memory, or three-dimensional NAND flash memory. For example, storage module 4400 can be provided as a memory card for user system 4000 or a removable drive for external drives.

[0195] For example, storage module 4400 may include multiple non-volatile memory devices, and the multiple non-volatile memory devices may be configured with reference to... Figure 1 The memory device 100 described herein operates in the same manner. The memory module 4400 can operate in the same manner as the referenced... Figure 1 The storage device 50 described herein operates in the same manner.

[0196] User interface 4500 may include an interface for inputting data or commands to application processor 4100 or outputting data to external devices. For example, user interface 4500 may include user input interfaces such as keyboards, keypads, buttons, touch panels, touchscreens, touchpads, touch balls, cameras, microphones, gyroscope sensors, vibration sensors, and piezoelectric elements. User interface 4500 may include user output interfaces such as LCD (Liquid Crystal Display), OLED (Organic Light Emitting Diode) displays, AMOLED (Active Matrix OLED) displays, LEDs, speakers, and monitors.

Claims

1. A computing system comprising: a storage device including a plurality of zones; and a host that receives, from the storage device, storage area information including an optimal write size of an open zone among the plurality of zones, calculates a history size by accumulating values of data previously flushed to the storage device until a history size reaches the optimal write size, determines a target size of data to be flushed to the storage device based on the optimal write size, the history size, and a size of buffer data of the host, and flushes data of the buffer data corresponding to the target size to the storage device.

2. The computing system according to claim 1, wherein the host includes: a host buffer that stores the buffer data; and a flush control unit that determines the target size based on the optimal write size, the history size, and the size of the buffer data, flushes data of the buffer data corresponding to the target size to the storage device, and updates the history size, wherein the history size is initialized each time the history size reaches the optimal write size.

3. The computing system according to claim 2, wherein the flush control unit sets the target size based on the history size and the optimal write size, and adjusts the target size based on a comparison result of the target size and the size of the buffer data.

4. The computing system according to claim 3, wherein the flush control unit sets a value obtained by subtracting the history size from the optimal write size as an initial value of the target size.

5. The computing system according to claim 4, wherein when the size of the buffer data is smaller than the target size, the flush control unit initializes the value of the target size, when the size of the buffer data is equal to the target size, the flush control unit maintains the value of the target size, and when the size of the buffer data is larger than the target size, the flush control unit adjusts the value of the target size within the size of the buffer data to a value obtained by adding an integer multiple of the optimal write size to the initial value of the target size.

6. The computing system according to claim 2, wherein the flush control unit provides a synchronization request to the storage device in response to a synchronization event that synchronizes the host and the storage device, and the flush control unit flushes the buffer data to the storage device.

7. The computing system according to claim 2, wherein the flush control unit is controlled by a log-structured file system.

8. The computing system according to claim 1, wherein the storage device includes: a memory device including the plurality of zones; and a memory controller that stores data flushed from the host and programs it to the open zone.

9. The computing system according to claim 8, wherein the memory device includes a plurality of zone buffers, each of the plurality of zone buffers corresponding to each of the plurality of zones, The plurality of zone buffers include memory units that store a smaller number of data bits per memory unit than memory units included in the plurality of zones.

10. The computing system of claim 9, wherein, the memory controller includes: a write buffer that stores data flushed from the host; and a memory operation control unit that programs data stored in the write buffer into the open zone or a zone buffer corresponding to the open zone.

11. The computing system of claim 10, wherein, the memory operation control unit programs data stored in the write buffer into the open zone or the zone buffer based on a comparison result of the optimal write size and a size of data stored in the write buffer.

12. The computing system of claim 11, wherein, when the size of data stored in the write buffer is greater than or equal to the optimal write size, the memory operation control unit programs data corresponding to the optimal write size among data stored in the write buffer into the open zone.

13. The computing system of claim 11, wherein, the memory operation control unit receives a synchronization request from the host, and when the size of data stored in the write buffer is less than the optimal write size, the memory operation control unit programs data stored in the write buffer into the zone buffer.

14. The computing system of claim 13, wherein, the memory operation control unit loads data stored in the zone buffer into the write buffer and programs data corresponding to the optimal write size among write buffer data into the open zone, the write buffer data includes data loaded from the zone buffer into the write buffer and data newly flushed from the host.

15. An operation method of a host that is an operation method of a host that controls a storage device including a plurality of zones, the operation method of a host including: receiving, from the storage device, storage area information including an optimal write size of an open zone among the plurality of zones; calculating a history size by accumulating values of data previously flushed to the storage device until before the history size reaches the optimal write size; determining a target size of data to be flushed to the storage device based on the optimal write size, the history size, and a size of buffer data of the host; and flushing data corresponding to the target size among the buffer data to the storage device.

16. The operation method of a host of claim 15, wherein, the step of determining the target size includes: setting the target size based on the optimal write size and the history size; and adjusting the target size based on a comparison result of the target size and the size of the buffer data.

17. The operation method of a host of claim 16, wherein, ​ In the step of determining the target size, a value obtained by subtracting the history size from the optimal write size is set as an initial value of the target size.

18. The operating method of a host according to claim 17, wherein, In the step of adjusting the target size, when the size of the buffer data is smaller than the target size, a value of the target size is initialized, when the size of the buffer data is equal to the target size, a value of the target size is maintained, and when the size of the buffer data is greater than the target size, a value of the target size is adjusted within a range of the size of the buffer data to a value obtained by adding an integer multiple of the optimal write size to the initial value of the target size.

19. The operating method of a host according to claim 15, further comprising the steps of: providing a synchronization request to the storage device in response to a synchronization event that synchronizes the host and the storage device; and flushing the buffer data to the storage device.

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