A Dual-Clock Multi-Core Embedded Concurrent Timing Simulation Method and Device

Abstract

The present invention relates to the field of computer application technologies, and specifically discloses a dual-clock multi-core embedded concurrent timing simulation method and apparatus. The method includes: determining the core rate of each core in a multi-core embedded system and simulation events to be simulated; determining the global virtual clock rate of a global virtual clock according to the core rates of all cores; dividing the global virtual clock rate by the core rate to obtain the core clock rate ratio of each core's local virtual clock relative to the global virtual clock; and sequentially determining whether each core needs to execute simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and the core clock rate ratios of each core, so as to simulate the simulation events through the cores that need to execute simulation in each global virtual clock cycle. The present invention solves the problem of core speed mismatch and simulation error caused by different core processor frequencies.

Description

Technical Field

[0001] This application relates to the field of computer application technologies, and in particular, to a dual-clock multi-core embedded concurrent timing simulation method and apparatus. Background Technique

[0002] Embedded systems are widely used in all aspects of human life. With the rapid growth of the computing power requirements of embedded systems, the performance of single-core processors gradually cannot support the real-time requirements of the system, and multi-core processors are increasingly applied to safety-critical embedded systems. In safety-critical embedded systems, the execution of various tasks in the system has strict time constraints. Timing anomalies will have a destructive impact on the system, resulting in serious losses of life and property. Safety-critical embedded systems need to fully demonstrate the timing correctness. Currently, most of the simulation tools for multi-core embedded systems use the same global clock as the clock for all cores, without considering the problem of kernel speed mismatch caused by different kernel processor frequencies, resulting in simulation errors. At the same time, the simulation of multi-core embedded systems also faces the problem of judging the order of occurrence of events. The time difference between two cores with the same frequency observing the occurrence of the same event is one cycle. Due to the accumulation of synchronization errors and digitalization errors, relying on the time difference of one global virtual clock cycle for the occurrence of events, the time sequence of different events cannot be accurately represented. For cores with different frequencies observing the same event, the error of the obtained time result will be even greater. The existence of the above problems leads to large errors in the simulation process. For some events, it is impossible to accurately judge the order of their occurrence, and the simulation analysis conclusions are unreliable. Summary of the Invention

[0003] The main purpose of this application is to provide a dual-clock multi-core embedded concurrent timing simulation method and apparatus to solve the problem of simulation errors caused by the failure to consider the kernel speed mismatch caused by different kernel processor frequencies in the prior art.

[0004] According to the first aspect of the embodiments of this application, a dual-clock multi-core embedded concurrent timing simulation method is provided, including:

[0005] Determine the kernel rate of each kernel in the multi-core embedded system and the simulation events to be simulated;

[0006] Determine the global virtual clock rate of the global virtual clock according to the kernel rates of all kernels;

[0007] Divide the global virtual clock rate by the kernel rate to obtain the kernel clock rate ratio of each kernel's local virtual clock relative to the global virtual clock;

[0008] According to the ratio between the current cycle number of the global virtual clock and the clock rate ratios of each kernel, it is determined in sequence whether each kernel needs to perform simulation in each global virtual clock cycle, so as to simulate the simulation event through the kernel that needs to perform simulation in each global virtual clock cycle.

[0009] Further, the simulation method further includes:

[0010] Obtain the release jitter time of each simulation event and a preset start release time, and obtain the clock cycle length of the global virtual clock according to the global virtual clock rate;

[0011] According to the start release time and the release jitter time, determine the release time when the simulation event releases the simulation job;

[0012] According to the release time and the clock cycle length, determine the global virtual clock cycle release node corresponding to the release time. When the global virtual clock reaches the global virtual clock cycle release node, the simulation event releases the simulation job, so that the kernel executes the simulation job when simulating the simulation event.

[0013] Further, before determining in sequence whether each kernel needs to perform simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and the clock rate ratios of each kernel, it includes:

[0014] Obtain the total simulation duration required for all kernels to perform simulation;

[0015] Determine the total number of global clock cycles of the simulation by taking the ratio of the total simulation duration to the global virtual clock rate. If the current cycle number of the global virtual clock is less than the total number of global clock cycles of the simulation, then determine in sequence whether each kernel needs to perform simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and the clock rate ratios of each kernel.

[0016] Further, when the kernel executes the simulation job, the local virtual clock is used to advance the execution of the simulation job.

[0017] Further, the advancing the execution of the simulation job by using the local virtual clock includes:

[0018] Obtain the execution time jitter of each simulation event, a preset execution time, and the kernel acceleration ratio of the kernel;

[0019] According to the execution time jitter and the preset execution time, determine the expected execution time for the kernel to execute the simulation job;

[0020] Determine the actual execution time for the kernel to execute the simulation job according to the expected execution time and the kernel speedup ratio;

[0021] Convert the actual execution time into the number of cycles of the local virtual clock according to the kernel rate. Then, when the kernel executes the simulation job, every time the local virtual clock advances one cycle, subtract one from the converted number of cycles of the local virtual clock. When the converted number of cycles of the local virtual clock is reduced to zero, the kernel has completed the simulation job.

[0022] Further, in the process of simulating the simulation events by the kernels that need to execute the simulation in each global virtual clock cycle, the method further includes:

[0023] Obtain a preset event occurrence time recording rule, and record the occurrence time and completion time of the simulation events based on the preset event occurrence time recording rule.

[0024] Further, the recording of the occurrence time and completion time of the simulation events based on the preset event occurrence time recording rule includes:

[0025] Set the first cycle of the local virtual clocks of all kernels to start at the same moment, and record the occurrence time and completion time of the simulation events using the global virtual clock cycle. The recorded occurrence time of the simulation event is the global virtual clock cycle corresponding to the start of the local virtual clock, and the recorded completion time of the simulation event occurs in the global virtual clock cycle corresponding to the start of the next local virtual clock.

[0026] Further, the determination of the global virtual clock rate of the global virtual clock according to the kernel rates of all kernels includes:

[0027] Determine the least common multiple of all the kernel rates, and determine the value that is an integer multiple of the least common multiple as the global virtual clock rate.

[0028] Further, after determining the value that is an integer multiple of the least common multiple as the global virtual clock rate, if the ratio obtained by dividing the global virtual clock rate by the kernel rate is an integer, then the determination of whether each kernel needs to execute the simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and each kernel clock rate ratio includes:

[0029] In each global virtual clock cycle, when the ratio between the current cycle number of the global virtual clock and several kernel clock rate ratios that are integers is an integer, determine the kernel to which the kernel clock rate ratio belongs as the kernel that needs to execute the simulation.

[0030] According to the second aspect of the embodiments of the present application, a dual-clock multi-core embedded concurrent timing simulation device is provided, including:

[0031] A first determination module, configured to determine the core rate of each core in the multi-core embedded system and the simulation events to be simulated;

[0032] A second determination module, configured to determine the global virtual clock rate of the global virtual clock according to the core rates of all cores;

[0033] An acquisition module, configured to divide the global virtual clock rate by the core rate to obtain the core clock rate ratio of each core's local virtual clock relative to the global virtual clock;

[0034] A simulation operation module, configured to sequentially determine whether each core needs to execute simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and each core clock rate ratio, so as to simulate the simulation events through the cores that need to execute simulation in each global virtual clock cycle.

[0035] Compared with the prior art, the technical solution of the present application at least has the following technical effects:

[0036] When simulating a multi-core embedded system, the present invention fully considers the problem of core speed mismatch caused by different core processor frequencies, and can simulate a multi-core embedded system with different core frequencies. During simulation, according to the core clock rate ratio obtained from different core rates and the global virtual clock rate, when the multiple relationship between the current cycle number of the global virtual clock and the core clock rate ratio is an integer multiple, the core starts to simulate, otherwise the core does not perform any operation in this global virtual clock cycle, solving the core speed matching error caused by different core frequencies.

[0037] Secondly, aiming at the problem that it is difficult to judge the chronological order of events occurring on different cores of a multi-core processor, an event occurrence time recording method is proposed. This method records the occurrence time and completion time of simulation events according to a preset event occurrence time recording rule, ensuring that the chronological order of all events can be judged, reducing the observation error to one global virtual clock cycle, and being able to accurately represent the chronological order of different events, and the simulation analysis conclusion is accurate and reliable. Description of the Drawings

[0038] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation to the present application. In the drawings:

[0039] Figure 1Schematic flowchart of a dual-clock multi-core embedded concurrent timing simulation method provided by the first embodiment of the present invention;

[0040] Figure 2 For Figure 1 Schematic flowchart of the simulation method before step S14 in

[0041] Figure 3 Schematic flowchart of the simulation event releasing the simulation job in the first embodiment of the present invention;

[0042] Figure 4 Schematic diagram of the execution process of each core advancing the simulation job using a local virtual clock in the first embodiment of the present invention;

[0043] Figure 5 Schematic structural diagram of a dual-clock multi-core embedded concurrent timing simulation device provided by the second embodiment of the present invention;

[0044] Figure 6 Schematic flowchart of a dual-clock multi-core embedded concurrent timing simulation method provided by the third embodiment of the present invention;

[0045] Figure 7 Task release job flowchart provided by the third embodiment of the present invention.

[0046] Among them, the above-mentioned drawings include the following reference numerals:

[0047] 10. First determination module; 20. Second determination module; 30. Acquisition module; 40. Simulation operation module. Detailed implementation manners

[0048] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0049] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary implementation manners according to the present application. As used herein, unless otherwise clearly specified in the context, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "include" and / or "comprise" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0050] Unless otherwise specifically stated, the relative arrangements, numerical expressions, and numerical values of the components and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that for the sake of convenience of description, the dimensions of the various parts shown in the drawings are not drawn in actual proportional relationship. Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and devices should be regarded as part of the specification. In all the examples shown and discussed here, any specific value should be construed as merely exemplary and not as a limitation. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0051] According to a first embodiment of the present application, a dual-clock multi-core embedded concurrent timing simulation method is provided. Please refer to Figure 1 , which includes the following steps:

[0052] Step S11: Determine the core rate of each core within the multi-core embedded system and the simulation events to be simulated. For example, express the rate of core γ i as f i . Here, the core rate may be the frequency of the core.

[0053] Step S12: Determine the global virtual clock rate f g of the global virtual clock according to the core rates of all cores.

[0054] Step S13: Divide the global virtual clock rate f g by the core rate f i to obtain the core clock rate ratio s i of each core's local virtual clock relative to the global virtual clock, that is, s i = f g / f i .

[0055] Step S14: According to the ratio between the current cycle number of the global virtual clock and the core clock rate ratios of each core, sequentially determine whether each core needs to perform simulation in each global virtual clock cycle, so as to simulate the simulation events through the cores that need to perform simulation in each global virtual clock cycle.

[0056] Please refer to Figure 2 . Before step S14 sequentially determines whether each core needs to perform simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and the core clock rate ratios of each core, it includes the following method steps:

[0057] Step S21: Obtain the total simulation duration required for simulating all cores.

[0058] Step S22: Determine the total number of global clock cycles of the simulation by taking the ratio of the total simulation duration to the global virtual clock rate. If the current global virtual clock cycle number is less than the total number of global clock cycles of the simulation, it indicates that the simulation has not ended, that is, there are still cores that have not been simulated. If the simulation has not ended, then according to the ratio between the current global virtual clock cycle number and the clock rate ratios of each core, it is determined in turn whether each core needs to perform simulation in each global virtual clock cycle.

[0059] Please refer to Figure 3 , if the simulation has not ended, before step S14 determines in turn whether each core needs to perform simulation in each global virtual clock cycle according to the ratio between the current global virtual clock cycle number and the clock rate ratios of each core, first release the simulation jobs of the simulation events (such as interrupts and tasks) according to the current global virtual clock cycle number, which specifically includes the steps of the following method:

[0060] Step S31: Obtain the release jitter time of each simulation event and the preset start release time, and obtain the clock cycle length p of the global virtual clock according to the global virtual clock rate g , the clock cycle length

[0061] Step S32: Determine the release time when the simulation event releases the simulation job according to the start release time and the release jitter time;

[0062] Step S33: Determine the global virtual clock cycle release node corresponding to the release time according to the release time and the clock cycle length. When the global virtual clock reaches the global virtual clock cycle release node, the simulation event releases the simulation job so that the core executes the simulation job when simulating the simulation event.

[0063] To make the embodiments of the present invention clearer, the above steps S31 - S33 are further described below by taking the release of a job by a periodic task as a simulation event as an example. Assume that the period of the periodic task τ i is T i , the start release time is srt i , the release jitter is rj i , the periodic task τ i uses the global variable rc i to record the number of job releases. Before starting the simulation, rc i is initialized to 0, and the arrival time calculation formula of the periodic task is used to calculate the moment rt1 when τ i releases the job for the first time, rt1 = srt + j, where j ~ U(-rj i , rj i), which means that element j follows the range U(-rj i , rj i ), and then calculate the global virtual clock cycle gt corresponding to the release moment, The global virtual clock cycle corresponding to the first release of the task When the global virtual clock reaches this cycle, the periodic task τ i releases its first job (i.e., the first simulation job), and then rc i increases by one. The system calculates the time rt2 for the next release of the task's job as rt2 = (srt + T i ), where j ~ U(-rj i , rj i ), and calculates the global virtual clock cycle corresponding to the second job release When the global virtual clock reaches gt2, the task releases its second job, and rc i increases by one, and then repeats the above process until the simulation ends.

[0064] When the kernel executes the simulation job, the execution of the simulation job is advanced through the local virtual clock of the kernel. Among them, for advancing the execution of the simulation job through the local virtual clock of the kernel, please refer to Figure 4 , including the following steps:

[0065] Step S41: Obtain the execution time jitter of each simulation event, the preset execution time, and the kernel acceleration ratio of the kernel;

[0066] Step S42: Determine the expected execution time for the kernel to execute the simulation job according to the execution time jitter and the preset execution time;

[0067] Step S43: Determine the actual execution time for the kernel to execute the simulation job according to the expected execution time and the kernel acceleration ratio;

[0068] Step S44: Convert the actual execution time into the number of cycles of the local virtual clock according to the kernel rate. Then, when the kernel executes the simulation job, whenever the local virtual clock advances one cycle, the converted number of cycles of the local virtual clock is decreased by one. When the converted number of cycles of the local virtual clock is decreased to zero, the kernel finishes executing the simulation job. After all kernels have finished executing the simulation job (i.e., all kernels have finished executing the simulation), the current cycle number of the global virtual clock is incremented by one until the current cycle number of the global virtual clock is greater than the total number of global clock cycles of the simulation to end the simulation.

[0069] In the embodiment of the present invention, taking the process of the kernel advancing the execution when releasing the kth simulation job of task τ i as an example to further illustrate the content of the above steps S41 - step S44, task τ when releasing the kth simulation jobi When releasing the k-th job According to the execution time jitter et i And the preset task execution time C i Determine the execution time of the job Because the frequencies and speeds of the processor cores are different, the execution times of the same task on different cores are also different. The kernel speedup ratio sr is used to represent the difference in the speeds of the processor cores. The larger the speedup ratio, the faster the kernel processing speed. After the job is assigned to the core γ n According to the kernel speedup ratio sr n Calculate the actual execution time of the job, which is equal to Convert the job execution time to the number of cycles lt of the local virtual clock k , When the job Is executing on the core γ n Whenever the local virtual clock of γ n Advances one cycle forward, The remaining number of execution cycles lt of k Decreases by one. When lt k Is equal to 0, it indicates that the job Execution is completed. The execution process of the interruption is similar to the job execution process and will not be elaborated here.

[0070] In the process of each core executing the simulation operation flow for the simulation events to be simulated in the system simulation model, the simulation method provided by the present invention further includes: obtaining a preset event occurrence time recording rule, and based on the preset event occurrence time recording rule, recording the occurrence time and completion time of the simulation events, specifically including:

[0071] Set the first cycle of the local virtual clocks of all cores to start at the same moment, and ensure that all simulation events occur at the start of each local virtual clock. Use the global virtual clock cycle to record the occurrence time and completion time of the simulation events. The recorded occurrence time of the simulation event is the global virtual clock cycle corresponding to the start of the local virtual clock, and the recorded completion time of the simulation event occurs at the global virtual clock cycle corresponding to the start of the next local virtual clock.

[0072] In step S12, determining the global virtual clock rate of the global virtual clock according to the kernel rates of all cores includes:

[0073] Determine the least common multiple of all kernel rates, and determine the value that is an integer multiple of the least common multiple as the global virtual clock rate. In the embodiment of the present invention, the global virtual clock rate f g Is equal to the least common multiple of all kernel rates (that is, the value that is one time of the least common multiple), that is, f g= LCM(f1,..., f n ). The obtained core clock rate ratio s i is an integer, i.e., s i = f g / f i

[0074] At this time, in step S14, according to the ratio between the current cycle number of the global virtual clock and each core clock rate ratio, it is sequentially determined whether each core needs to perform simulation in each global virtual clock cycle, including:

[0075] In each global virtual clock cycle, when the ratio between the current cycle number of the global virtual clock and one or more core clock rate ratios as an integer is an integer, the one or more cores to which the one or more core clock rate ratios belong are determined as the cores that need to perform simulation. Only when the current cycle number of the global virtual clock is an integer multiple of the core rate ratio of the core, the core performs simulation in the current global virtual clock cycle where it is located. The core that does not meet this condition does not perform any operation in this cycle and waits for the next cycle to arrive until it can be simulated. After all cores have been simulated, the simulation ends.

[0076] It can be seen that when the present invention simulates a multi-core embedded system, it fully considers the problem of core speed mismatch caused by different core processor frequencies, and can simulate a multi-core embedded system with different core frequencies. During simulation, according to the core clock rate ratio obtained from different core rates and the global virtual clock rate, when the multiple relationship between the current cycle number of the global virtual clock and the core clock rate ratio is an integer multiple, the core starts to simulate, otherwise the core does not perform any operation in this global virtual clock cycle, solving the core speed matching error caused by different core frequencies.

[0077] Secondly, aiming at the problem that it is difficult to judge the sequence of event occurrence times on different cores of a multi-core processor, an event occurrence time recording method is proposed. This method records the occurrence time and completion time of simulation events according to a preset event occurrence time recording rule, ensuring that the sequence of all events can be judged, reducing the observation error to one global virtual clock cycle, being able to accurately represent the time sequence of different events, and the simulation analysis conclusion being accurate and reliable.

[0078] The second embodiment of the present application provides a dual-clock multi-core embedded concurrent timing simulation device. Please refer to Figure 5 , including:

[0079] The first determination module 10 is used to determine the core rate of each core in the multi-core embedded system and the simulation events to be simulated;

[0080] The second determination module 20 is configured to determine the global virtual clock rate of the global virtual clock according to the core rates of all cores;

[0081] The obtaining module 30 is configured to divide the global virtual clock rate by the core rate to obtain the core clock rate ratio of each core's local virtual clock relative to the global virtual clock;

[0082] The simulation running module 40 is configured to sequentially determine whether each core needs to execute simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and the core clock rate ratios of each core, so as to simulate simulation events through the cores that need to execute simulation in each global virtual clock cycle.

[0083] In the embodiment of the present application, the simulation running module 40 further executes the steps of the following method:

[0084] Step S31: Obtain the release jitter time of each simulation event and the preset start release time, and obtain the clock cycle length p of the global virtual clock according to the global virtual clock rate g , the clock cycle length

[0085] Step S32: Determine the release time when the simulation event releases the simulation job according to the start release time and the release jitter time;

[0086] Step S33: Determine the global virtual clock cycle release node corresponding to the release time according to the release time and the clock cycle length. When the global virtual clock reaches the global virtual clock cycle release node, the simulation event releases the simulation job, so that the core executes the simulation job when simulating the simulation event.

[0087] Before the simulation running module 40 sequentially determines whether each core needs to execute simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and the core clock rate ratios of each core, the simulation running module 40 further executes the steps of the following method:

[0088] Step S21: Obtain the total simulation duration required for all cores to perform simulation;

[0089] Step S22: Determine the total number of global clock cycles of the simulation by taking the ratio of the total simulation duration to the global virtual clock rate. If the current cycle number of the global virtual clock is less than the total number of global clock cycles of the simulation, the simulation running module 40 sequentially determines whether each core needs to execute simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and the core clock rate ratios of each core.

[0090] When the simulation operation module 40 causes the kernel to execute a simulation job and advances the execution of the simulation job through the local virtual clock of the kernel, the specific steps of the method for the simulation operation module 40 to advance the execution of the simulation job through the local virtual clock of the kernel are as follows:

[0091] Step S41: Obtain the execution time jitter of each simulation event, the preset execution time, and the kernel acceleration ratio of the kernel;

[0092] Step S42: Determine the expected execution time for the kernel to execute the simulation job according to the execution time jitter and the preset execution time;

[0093] Step S43: Determine the actual execution time for the kernel to execute the simulation job according to the expected execution time and the kernel acceleration ratio;

[0094] Step S44: Convert the actual execution time into the number of cycles of the local virtual clock according to the kernel rate. When the kernel executes the simulation job, every time the local virtual clock advances one cycle, the converted number of cycles of the local virtual clock is decreased by one. When the converted number of cycles of the local virtual clock is decreased to zero, the kernel has completed the simulation job. After all kernels have completed the simulation job (that is, all kernels have completed the simulation), the current cycle number of the global virtual clock is incremented by one until the current cycle number of the global virtual clock is greater than the total number of global clock cycles of the simulation, and then the simulation ends.

[0095] During the process of the simulation operation module 40 simulating simulation events through the kernels that need to execute the simulation in each global virtual clock cycle, the following method steps are also executed:

[0096] Obtain the preset event occurrence time recording rule, and record the occurrence time and completion time of the simulation event based on the preset event occurrence time recording rule.

[0097] Among them, recording the occurrence time and completion time of the simulation event based on the preset event occurrence time recording rule includes: setting the first cycle of the local virtual clocks of all kernels to start at the same moment, using the global virtual clock cycle to record the occurrence time and completion time of the simulation event. The recorded occurrence time of the simulation event is the global virtual clock cycle corresponding to the start of the local virtual clock, and the recorded completion time of the simulation event occurs in the global virtual clock cycle corresponding to the start of the next local virtual clock.

[0098] When the second determination module 20 determines the global virtual clock rate of the global virtual clock according to the kernel rates of all kernels, it determines the least common multiple of all kernel rates and determines the value that is an integer multiple of the least common multiple as the global virtual clock rate.

[0099] After the second determination module 20 determines the value that is an integer multiple of the least common multiple as the global virtual clock rate, the acquisition module 30 obtains that the ratio of the global virtual clock rate to the kernel rate is an integer. At this time, when the simulation operation module 40 determines whether each kernel needs to perform simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and each kernel clock rate ratio, in each global virtual clock cycle, when the ratio between the current cycle number of the global virtual clock and several kernel clock rate ratios that are integers is an integer, the kernel to which the kernel clock rate ratio belongs is determined as the kernel that needs to perform simulation.

[0100] Therefore, the device provided by the present invention can simulate a multi-core embedded system with different kernel frequencies, solves the kernel speed matching error caused by different kernel frequencies, and proposes an event occurrence time recording method for the problem that it is difficult to judge the sequence of event occurrence times on different kernels of a multi-core processor, ensuring that the sequence of all event occurrences can be judged and reducing the observation error to one global virtual clock cycle.

[0101] To make the present invention clearer and more understandable, the third embodiment of the present application combines the attached Figures 6 - 7 to provide an application embodiment, so as to specifically illustrate the specific implementation process of the concurrent timing simulation of a dual-clock multi-core embedded system.

[0102] Please refer to Figure 6 , taking simulation events as interrupts and tasks as examples, the present invention embodiment provides a method for implementing a dual-clock multi-core embedded concurrent timing simulation, and the method steps are as follows:

[0103] Step 1: Define the system model and set the rate of each kernel of the system. The rate of kernel γ i is expressed as f i , and the rate here can be the frequency of the kernel;

[0104] Step 2: Calculate the rate f g of the global virtual clock of the simulation system. The rate of the global virtual clock is equal to the least common multiple of the rates of all kernels, that is, f g = LCM(f1,..., f n ); and calculate the cycle length of the global virtual clock g

[0105]

[0106] Step 3: Calculate the rate ratio of the local virtual clock of each kernel to the global virtual clock. The rate ratio of the local virtual clock of kernel γ i to the global virtual clock is expressed as s i , which is equal to the global virtual clock rate divided by the kernel rate, that is, s i=f g / f i ;

[0107] Step 4: Calculate the total number of global clock cycles a according to the total simulation time t, a = t / f g ;

[0108] Step 5: Before starting the simulation, set the current period of the global virtual clock C g To 0, set the current cycle C1 of each core's local virtual clock to 0;

[0109] Step 6: During the simulation, at the beginning of the global virtual clock cycle, first determine whether the simulation is finished. g >a when the simulation ends. If the simulation has not ended, first calculate the current cycle C of the global virtual clock. g Release interrupts and tasks, and determine whether the kernel is emulated in turn. When the number of global virtual clock cycles is an integer multiple of the kernel rate ratio, that is, C g mods i = 0, the kernel starts emulation, otherwise the kernel does not perform any operation in this global virtual clock cycle. When all kernels are executed, the global virtual clock current cycle C g Add 1.

[0110] See also Figure 7 , the release time of interrupts and tasks is determined according to the global virtual clock. Assuming that the periodic task τ i The period is T i , the start release time is srt i , the release jitter is rj i , periodic task τ i Using the global variable rc i Record the number of release jobs, rc before starting simulation i Initialize to 0 and use the periodic task arrival time calculation formula to calculate τ i The time rt1 of the first release operation, rt1 = srt + j, where j ~ U (-rj i ,rj i ), which means that the element j is subject to the range U(-rj i ,rj i ), and then calculate the global virtual clock period gt corresponding to the release time, The global virtual clock cycle corresponding to the first release of the task When the global virtual clock reaches this cycle, task τ i Release its first job, then rc i The value of srt is increased by 1, and the system calculates the time when the task releases the next job rt2 = (srt + T i )+j, where j~U(-rji , rj i ), calculate the global virtual clock cycle corresponding to the release of the second job When the global virtual clock reaches gt2, the task releases the second job, and rc i increases by one, and then repeats the above process until the simulation ends.

[0111] The release methods of sporadic tasks and random tasks are basically the same as those of periodic tasks. A global variable is used to maintain the release count of the task. After the release of the previous job, the release time of the next job and the corresponding global virtual clock cycle are calculated. The calculation method of the global virtual clock cycle is the same as that of periodic tasks, only the calculation method of the release time is different. For example, assume that the sporadic task or random task τ i The starting release time is srt i , and the release jitter is rj i , task τ i uses the global variable rc i to record the number of released jobs. Before starting the simulation, rc i is initialized to 0. For task τ i The moment of the first job release is rt1, rt1 = srt + j, where j ~ U(-rj i , rj i ), and then calculate the global virtual clock cycle gt corresponding to the release moment. The global virtual clock cycle corresponding to the first job release of the task The interrupt release process is the same as the task release process.

[0112] In order to be able to compare the order of event occurrences on different cores, the simulation is based on the following assumptions: The first cycle of all core local virtual clocks starts at the same moment; The occurrence times of all events are recorded using the global virtual clock; All events occur at the beginning of each local virtual clock. Interrupts and job releases occur at the global virtual clock cycle corresponding to the start of the local virtual clock, and interrupts and job completions occur at the global virtual clock cycle corresponding to the start of the next local virtual clock.

[0113] After tasks and interrupts are assigned to different cores by the global scheduler, they are managed by the core local scheduler, and the core local virtual clock is used to advance the execution of jobs and interrupts. For task τ i When releasing the kth job According to the execution time jitter et i and the task execution time C i Determine the execution time of the job Because the frequencies and speeds of processor cores are different, the execution time of the same task on different cores will also be different. The kernel acceleration ratio sr is used to represent the difference in the speeds of processor cores. The larger the acceleration ratio, the faster the kernel processing speed. When a job is assigned to core γ n After that, according to the kernel acceleration ratio sr n Calculate the actual execution time of the job, which is equal to Convert the job execution time to the number of cycles lt of the local virtual clock k , When the job is executing on core γ n Whenever the local virtual clock of γ n advances one cycle forward, The remaining number of execution cycles lt k decreases by one. When lt k equals 0, it indicates that the job has completed execution. Similar to the simulation of job execution time, the simulation of other constraints of the job also uses the local virtual clock to drive. When the job is assigned to the core, first divide the time related to execution such as the message demand time, message generation time, and global variable modification time of the job by the acceleration ratio of the core to calculate the actual time required for simulation on the core, and then convert each time to the number of cycles of the local virtual clock of the core. When the job is executed by the core, the local virtual clock is incremented by one, and the time related to job execution is decremented by one. When it is decremented to 0, corresponding actions are executed according to the execution situation of the system. The execution process of the interrupt is similar to the job execution process.

[0114] In summary, the present invention discloses a dual-clock multi-core embedded concurrent timing simulation method. It includes six steps: defining the system model, setting the rate of each core of the system, calculating the rate of the global virtual clock of the simulation system, calculating the rate ratio of the local virtual clock of each core to the global virtual clock, determining the total number of global clock cycles of the simulation, initializing the global virtual clock and the local virtual clock, and simulating the operation. The present invention can simulate a multi-core embedded system with different core frequencies, solves the kernel speed matching error caused by different core frequencies, and proposes a method for recording the occurrence time of events for the problem that it is difficult to judge the order of occurrence time of events on different cores of a multi-core processor, ensuring that the order of occurrence of all events can be judged and reducing the observation error to one global virtual clock cycle.

[0115] For ease of description, spatial relative terms such as "above", "over", "on the upper surface", "upper" etc. may be used herein to describe the spatial positional relationship of one device or feature to other devices or features as shown in the figures. It should be understood that the spatial relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the drawing is inverted, the device described as "above" or "over" other devices or structures will then be positioned "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both orientations of "above" and "below". The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and corresponding interpretations should be made to the spatial relative descriptions used herein.

[0116] In addition, it should be noted that the use of terms such as "first", "second" etc. to define components is only for the convenience of differentiating the corresponding components. Without additional statements, the above terms have no special meanings, and thus should not be construed as limiting the protection scope of the present application.

[0117] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A dual-clock multi-core embedded concurrent timing simulation method, characterized in that Including: Determine the core rate of each core within the multi-core embedded system and the simulation events to be simulated; Determine the global virtual clock rate of the global virtual clock according to the core rates of all cores; Divide the global virtual clock rate by the core rate to obtain the core clock rate ratio of each core's local virtual clock relative to the global virtual clock; According to the ratio between the current cycle number of the global virtual clock and each core clock rate ratio, sequentially determine whether each core needs to execute simulation within each global virtual clock cycle, so as to simulate the simulation events through the cores that need to execute simulation within each global virtual clock cycle; Before sequentially determining whether each core needs to execute simulation within each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and each core clock rate ratio, it includes: Obtain the total simulation duration required for all cores to perform simulation; Determine the total number of global clock cycles of the simulation by taking the ratio of the total simulation duration to the global virtual clock rate. If the current cycle number of the global virtual clock is less than the total number of global clock cycles of the simulation, then sequentially determine whether each core needs to execute simulation within each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and each core clock rate ratio; When the core executes the simulation job, advance the execution of the simulation job through the local virtual clock; The advancing the execution of the simulation job through the local virtual clock includes: Obtain the execution time jitter of each simulation event, the preset execution time, and the core speedup ratio of the core; Determine the expected execution time for the core to execute the simulation job according to the execution time jitter and the preset execution time; Determine the actual execution time for the core to execute the simulation job according to the expected execution time and the core speedup ratio; Convert the actual execution time to the number of cycles of the local virtual clock according to the core rate. Then, when the core executes the simulation job, every time the local virtual clock advances one cycle, subtract one from the converted number of cycles of the local virtual clock. When the converted number of cycles of the local virtual clock is reduced to zero, the core finishes executing the simulation job.

2. The dual-clock multi-core embedded concurrent timing simulation method according to claim 1, characterized in that, The method further includes: Obtain the release jitter time of each simulation event and the preset start release time, and obtain the clock cycle length of the global virtual clock according to the global virtual clock rate; Determine the release time for the simulation event to release the simulation job according to the start release time and the release jitter time; Determine the global virtual clock cycle release node corresponding to the release time according to the release time and the clock cycle length. When the global virtual clock reaches the global virtual clock cycle release node, the simulation event releases the simulation job, so that the core executes the simulation job when simulating the simulation event.

3. The dual-clock multi-core embedded concurrent timing simulation method according to claim 1, wherein During the process of simulating the simulation events through the cores that need to execute simulation within each global virtual clock cycle, the method further includes: Obtain the preset event occurrence time recording rule, and based on the preset event occurrence time recording rule, record the occurrence time and completion time of the simulation event.

4. The dual-clock multi-core embedded concurrent timing simulation method according to claim 3, characterized in that, The recording of the occurrence time and completion time of the simulation event based on the preset event occurrence time recording rule includes: Set the first cycle of the local virtual clocks of all cores to start at the same moment, and use the global virtual clock cycle to record the occurrence time and completion time of the simulation event. The recorded occurrence time of the simulation event is the global virtual clock cycle corresponding to the start of the local virtual clock, and the recorded completion time of the simulation event occurs at the global virtual clock cycle corresponding to the start of the next local virtual clock.

5. The dual-clock multi-core embedded concurrent timing simulation method according to claim 1, characterized in that The determining of the global virtual clock rate of the global virtual clock according to the core rates of all cores includes: Determine the least common multiple of all the core rates, and determine the value of an integer multiple of the least common multiple as the global virtual clock rate.

6. The dual-clock multi-core embedded concurrent timing simulation method according to claim 5, wherein, After determining the value of an integer multiple of the least common multiple as the global virtual clock rate, if the ratio obtained by dividing the global virtual clock rate by the core rate is an integer, then the determination of whether each core needs to perform simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and each core clock rate ratio includes: In each global virtual clock cycle, when the ratio between the current cycle number of the global virtual clock and several core clock rate ratios that are integers is an integer, determine the core to which the core clock rate ratio belongs as the core that needs to perform simulation.

7. A dual-clock multi-core embedded concurrent timing simulation device, characterized in that, Includes: The first determination module (10) is used to determine the core rate of each core in the multi-core embedded system and the simulation event to be simulated; The second determination module (20) is used to determine the global virtual clock rate of the global virtual clock according to the core rates of all cores; The acquisition module (30) is used to divide the global virtual clock rate by the core rate to obtain the core clock rate ratio of each core's local virtual clock relative to the global virtual clock; The simulation operation module (40) is used to determine whether each core needs to perform simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and each core clock rate ratio, so as to perform simulation on the simulation event through the cores that need to perform simulation in each global virtual clock cycle; Before determining whether each core needs to perform simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and each core clock rate ratio, it includes: Obtain the total simulation duration required for all cores to perform simulation; Determine the ratio of the total simulation duration to the global virtual clock rate as the total global clock cycle number of the simulation. If the current cycle number of the global virtual clock is less than the total global clock cycle number of the simulation, then determine whether each core needs to perform simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and each core clock rate ratio. When the kernel executes a simulation job, it advances the execution of the simulation job through the local virtual clock; advancing the execution of the simulation job through the local virtual clock includes: Obtaining the execution time jitter of each simulation event, the preset execution time, and the kernel speedup ratio of the kernel; determining the expected execution time for the kernel to execute the simulation job according to the execution time jitter and the preset execution time; Determining the actual execution time for the kernel to execute the simulation job according to the expected execution time and the kernel speedup ratio; Converting the actual execution time into the number of cycles of the local virtual clock according to the kernel rate. Then, when the kernel executes the simulation job, every time the local virtual clock advances one cycle, the converted number of cycles of the local virtual clock is decremented by one. When the converted number of cycles of the local virtual clock is decremented to zero, the kernel has completed the execution of the simulation job.

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