A System-Level Digital Circuit Upgrade and Optimization Method and Device

Abstract

The present invention provides a method and device for upgrading and optimizing a system-level digital circuit, belonging to the technical field of circuit design. The method includes: generating a component list and a netlist according to the schematic diagram of the digital system to be optimized, and determining the chip model used for the optimized design according to the input and output levels, the number of components, and the source of the integrated chip; performing VHDL language modeling on the minimum logic units of various components in the component list according to the types of the digital systems to be optimized, and converting the netlist with components as the main body into a netlist with minimum logic units as the main body; changing the resistor-capacitor element circuit that cannot be modeled using VHDL language into a digital delay circuit description, and changing the monostable circuit into a digital trigger circuit description; calculating the resource occupation number of the functional modules, and merging or splitting the functional modules according to the chip storage capacity and the total resource occupation number of the functional modules, so as to quickly realize the resource allocation of multiple chips.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit design, and more specifically, relates to a system-level digital circuit upgrade and optimization method and device. Background Art

[0002] In the early design of electronic devices, medium and small-scale circuits were used. Such devices are still within their service life. As the usage time increases, the reliability of the related circuit boards decreases and the failure rate increases; with the consumption of spare parts and the elimination of some components, the maintenance of the devices becomes very difficult.

[0003] With the development of microelectronics technology, digital integrated circuits themselves have developed from early medium and small-scale integrated circuits to very large-scale integrated circuits (VLSIC, with more than tens of thousands of gates) and many application-specific integrated circuits with specific functions. Currently, field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) widely used are adopted to upgrade and design early digital systems, greatly improving the miniaturization, integration and reliability of electronic products, thus solving the problem of the source of spare parts in equipment maintenance.

[0004] According to the steps of digital circuit design, it is necessary to manually complete the schematic diagram or VHDL language modeling first, without making full use of the existing technical basis of the digital system (schematic diagram) to be optimized, and there are technical defects such as large workload and easy error, resulting in low efficiency. Summary of the Invention

[0005] Aiming at the defects of the existing technology, the purpose of the present invention is to provide a system-level digital circuit upgrade and optimization method and device, which utilize the existing technical basis to realize the automated design of digital system upgrade and optimization, aiming to solve the problem of low efficiency in the upgrade and optimization of existing digital systems; when the chip supply channels for upgrade and optimization are blocked, the system-level digital system upgrade and optimization method provided by the present invention can quickly complete the redesign or transplantation of digital systems.

[0006] To achieve the above purpose, on the one hand, the present invention provides a system-level digital circuit upgrade and optimization method, including the following steps:

[0007] S1: Generate a component list and a netlist according to the schematic diagram of the digital system to be upgraded and optimized, and determine the chip sequence for optimization design according to the input and output levels and the number of components of each component; wherein, the netlist is used to record the input and output connection relationships between components;

[0008] S2: Perform VHDL language modeling on the minimum logic units of each component in the component list, and calculate the resource requirements for each minimum logic unit; wherein, the resource requirements include macro cells, CLBs and the number of pins;

[0009] S3: Convert the netlist with components as the main body into a netlist with minimum logic units as the main body using VHDL language description of minimum logic units; among them, the input netlist name is used to represent the input connection relationship of minimum logic units.

[0010] S4: Modify the resistor-capacitor element circuit that cannot be modeled using VHDL language into a digital delay circuit description, and change the monostable circuit to a digital trigger circuit description, and update the database of the workpiece list.

[0011] S5: Combine the input netlist name of the minimum logic unit and the implemented functions of the minimum logic unit, divide the updated database into functional modules, and calculate the resource occupation of each functional module; among them, the functional module is designed with minimum logic units that implement the same operation into one module.

[0012] S6: When the storage capacity of the chip used for the optimized design is greater than the total resource occupation of a single functional module, then merge multiple functional modules; if a single functional module design requires multiple chips, then determine the required number of chips N according to the total resource occupation of the functional module and the storage capacity of the chip. Starting from the input pin number of 1 / N of the functional module for each chip, with the same netlist name having priority, expand and search according to the network topology diagram drawn based on the netlist with minimum logic units as the unit until reaching the output end of the digital system to be optimized for design, and then add additional pins generated by functional module cutting on each designed chip.

[0013] Further preferably, after S6, it further includes:

[0014] S7: According to the numbers of the chips used for the optimized design, generate VHDL description files for each chip based on the VHDL description of the components in the functional module and the netlist with minimum logic units as the main body, and provide the external pin numbers of the chips. Compile the VHDL description files using FPGA or CPLD to generate configuration files for chip (power-on) configuration.

[0015] S8: Provide test stimuli according to the input of the upgraded and optimized digital system, and perform simulation step by step according to the numbers of the chips. The output of the upper-level chip is used as the input stimulus of the lower-level chip until the digital output level.

[0016] Further preferably, the chip sequence is an FPGA or CPLD chip sequence.

[0017] Further preferably, the chip resource occupation rate does not exceed 70%.

[0018] Further preferably, the number of merged functional modules in S6 is the ratio of 70% of the chip storage capacity divided by the total resource occupation of a single functional module.

[0019] If a single functional module design requires multiple chips, the total number of resources occupied by the functional module is divided by 70% of the storage capacity of the chip to determine the required number of chips N.

[0020] On the other hand, the present invention provides a system-level digital circuit upgrade and optimization device, including:

[0021] A data construction system for generating a component list and a netlist according to the schematic diagram of the digital system to be upgraded and optimized, and determining the chip sequence adopted for the optimized design according to the input and output levels and the number of components of each component; wherein, the netlist is used to record the input and output connection relationships between components;

[0022] A logic unit language modeling system for performing VHDL language modeling on the minimum logic unit of each component in the component list and calculating the number of resources required for each minimum logic unit; wherein, the required number of resources includes macro cells, CLBs, and the number of pins;

[0023] A netlist conversion system for converting a netlist with components as the main body into a netlist with minimum logic units as the main body by using the VHDL language description of the minimum logic unit; wherein, the input net name is used to represent the input connection relationship of the minimum logic unit;

[0024] A circuit description system that does not use VHDL language modeling for converting the resistor-capacitor element circuit that cannot be modeled in VHDL into a digital delay circuit description, and converting the monostable circuit into a digital trigger circuit description, and updating the database of the workpiece list;

[0025] A functional module construction system for dividing the updated database into functional modules by combining the input net name of the minimum logic unit and the implemented function of the minimum logic unit, and calculating the number of resources occupied by each functional module; wherein, the functional module is designed with the minimum logic units that implement the same operation into one module construction;

[0026] When the storage capacity of the chip used for the optimized design is greater than the total number of resources occupied by a single functional module, multiple functional modules are merged; if a single functional module design requires multiple chips, the total number of resources occupied by the functional module is divided by 70% of the storage capacity of the chip to determine the required number of chips. For each chip, starting from the 1 / N input pin number of the functional module, with the same type of net name having priority, expand and search according to the network topology diagram drawn based on the netlist with the minimum logic unit as the unit until reaching the output end of the digital system to be optimized for design, and at the same time add the additional pins generated by the functional module cutting.

[0027] Further preferably, the system-level digital circuit upgrade and optimization device further includes:

[0028] A configuration file generation system is used to optimize the numbers of various chips used in the design. Based on the VHDL descriptions of components in the optimization design functional module and the netlist with the minimum logic unit as the main body, it generates the VHDL description files of each chip, and provides the external pin numbers of the chips. It uses FPGA or CPLD to compile the VHDL description files to generate configuration files for the (power-on) configuration of the chips used in the optimization design;

[0029] A test stimulus system is used to provide test stimuli according to the inputs of the digital system, and perform simulations step by step according to the numbers of the chips. The outputs of the upper-level chips are used as the input stimuli for the lower-level chips until the output stage of the digital system.

[0030] Further preferably, the chip sequence is an FPGA or CPLD chip sequence.

[0031] Further preferably, the chip resource occupancy rate does not exceed 70%.

[0032] Further preferably, when the storage capacity of the chips used in the optimization design is greater than the total occupied resources of a single functional module, the number of merged functional modules is the ratio of 70% of the chip storage capacity divided by the total occupied resources of a single functional module;

[0033] If a single functional module design requires multiple chips, the number of required chips N is determined by dividing the total occupied resources of the functional module by 70% of the chip storage capacity.

[0034] Generally speaking, compared with the prior art, the above technical solutions conceived by the present invention have the following beneficial effects:

[0035] The present invention provides a method and device for upgrading and optimizing system-level digital circuits. Among them, the digital system schematic diagram is utilized to the greatest extent to generate a component list and a netlist characterizing the features of input and output signals. By describing the minimum logic units of each component in VHDL language, a VHDL language description of the system is automatically established according to the netlist; combining the input network names of the minimum logic units and the implemented functions of the minimum logic units, the replaced database is divided into functional modules. Herein, the functional modules are designed by grouping the minimum logic units that implement the same operation into one module (this technical feature is not disclosed in the prior art. The prior art usually takes components as the main body and designs according to the input and output sequence of the digital system schematic diagram). Subsequently, an automatic allocation algorithm is adopted to merge or split the functional modules (when the storage capacity of the current chip in the determined optimized chip sequence is greater than the total resources occupied by a single functional module, multiple functional modules are merged; if the design of a single functional module requires multiple chips, the number of required chips N is determined according to the total resources occupied by the functional module and the storage capacity of the chip. Starting from the input pin number of 1 / N of the functional module for each chip, with the same network names having priority, an extended search is performed according to the network topology diagram drawn based on the netlist with the minimum logic unit as the unit until the output end of the digital system to be optimized for design, and additional pins generated by the functional module cutting are added to each designed chip), which can quickly realize the resource allocation of multiple chips.

[0036] For the method and device for upgrading and optimizing system-level digital circuits provided by the present invention, since the functional modules are designed by grouping the minimum logic units that implement the same operation into one module, therefore, regardless of subsequent functional module splitting or merging, when some functional modules in the system digital circuit fail or need to be upgraded, the same functional modules can be directly used for replacement or upgrade, and the upgrading and transformation of the system-level digital circuit can be quickly and accurately realized. Description of the Drawings

[0037] Figure 1 is the flowchart of the system-level digital circuit optimization method provided by the embodiment of the present invention;

[0038] Figure 2 is the flowchart of the functional module merging algorithm provided by the embodiment of the present invention;

[0039] Figure 3 is the flowchart of the functional module splitting algorithm provided by the embodiment of the present invention. Detailed Embodiments

[0040] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0041] On the one hand, as Figure 1 shown, the present invention provides a method for upgrading and optimizing a system-level digital circuit, including the following steps:

[0042] Step 1: Organize the schematic diagram of the digital system to be upgraded and optimized to generate a component list and a netlist; and determine the FPGA or CPLD chip sequence for the optimization design according to the input and output levels and the number of components of each component; the netlist is used to record the signal connection relationships between components;

[0043] Step 2: Model the minimum logic units of each component in the component list using VHDL language, and give the resource requirements for each minimum logic unit; the resource requirements include macro cells, CLBs, and the number of pins;

[0044] Step 3: Take the minimum logic units of each component as units, and use the VHDL language description of the minimum logic units to convert the netlist with components as units into a netlist with minimum logic units as units; that is, use the VHDL language description of the minimum logic units to verify the input and output relationships of the components, ensure that there is a reliable data source for the input pins of the components, and for the convenience of subsequent functional module division, each component is described by multiple minimum logic units, that is, a new component name is assigned to each minimum logic unit, and the database is updated at the same time; among them, each minimum logic unit input has a specific input network name (input signal name), and generally there is only one output for one network;

[0045] Step 4: Use a digital delay circuit description for the resistor-capacitor element circuit that cannot be modeled using VHDL language; use a digital trigger circuit description for the monostable circuit, and update the database;

[0046] Step 5: Based on the updated database, perform functional module division: Divide the updated database according to the input network names of the minimum logic units or with the assistance of humans, and automatically calculate the resource occupation of each functional module; among them, a functional module is designed with the minimum logic units that perform the same operation into one module;

[0047] Step 6: When the storage capacity of the chip used for the optimization design is greater than the total resource occupation of a single functional module, then automatically merge two or more functional modules according to the ratio of the two to ensure the maximum use of chip resources, as Figure 2 shown;

[0048] Step 7: If a single functional module occupies more than two FPGA and CPLD chip resources, calculate the total resource occupation of the function (macro cells, CLBs, and the number of pins), and determine the required number of chips N by dividing the total resource occupation of the functional module by the storage capacity of the chip, as Figure 3As shown in the figure; starting from the number of input pins of the function module 1 / N, with the same type of network name having priority, expand and search the network topology diagram drawn according to the netlist until the output end. At the same time, add the additional pins generated by the module cutting to the part where the function module has been cut, and continue the module division under the condition that the chip resources are sufficient; repeat step 7 until the division of the function module is completed; considering the need for function expansion and debugging, the chip resource occupancy rate does not exceed 70%.

[0049] Step 8: Generate the VHDL description file of the chip according to the VHDL description and netlist of the function module components according to the numbers of the chips used in the optimized design, and give the external pin numbers; and use FPGA or CPLD to compile the VHDL description file to generate the configuration file.

[0050] Step 9: Provide test stimuli according to the digital system input, and perform simulation level by level according to the chip numbers. The output of the upper-level chip is used as the input stimulus of the lower-level chip until the system output level.

[0051] On the other hand, the present invention provides a system-level digital circuit upgrade and optimization device, including:

[0052] A data construction system, used to generate a component list and a netlist according to the digital system schematic diagram, and determine the chip sequence according to the input and output electrical levels and the number of components of each component; wherein, the netlist is used to record the input and output connection relationships between components.

[0053] A logic unit language modeling system, used to perform VHDL language modeling on the minimum logic unit of each component in the component list, and calculate the resource numbers required for each minimum logic unit; wherein, the required resource numbers include macro cells, CLBs, and the number of pins.

[0054] A netlist conversion system, used to convert the component-based netlist into a minimum logic unit-based netlist by using the VHDL language description of the minimum logic unit; wherein, the input network name is used to represent the input connection relationship of the minimum logic unit.

[0055] A circuit description system that does not perform VHDL language modeling, used to change the resistor-capacitor element circuit that cannot be modeled by VHDL into a digital delay circuit description, and change the monostable circuit into a digital trigger circuit description, and update the database of the workpiece list.

[0056] A function module construction system, used to divide the updated database into function modules by combining the input network name of the minimum logic unit and the implemented function of the minimum logic unit, and calculate the resource occupancy of each function module; wherein, the function module is designed by combining the minimum logic units that implement the same operation into one module.

[0057] When the storage capacity of the chip used for the optimized design is greater than the total resources occupied by a single functional module, multiple functional modules are merged; if the design of a single functional module requires multiple chips, the number of required chips is determined by dividing the total resources occupied by the functional module by 70% of the storage capacity of the chip. For each chip, starting from the input pin number of 1 / N of the functional module, with the same network name having priority, the network topology diagram drawn according to the netlist with the smallest logic unit as the unit is expanded and searched until the output end of the digital system to be optimized for design, and additional pins generated by the cutting of the functional module are added at the same time.

[0058] Further preferably, the system-level digital circuit upgrade and optimization device further includes:

[0059] A configuration file generation system, which is used to generate a VHDL description file for each chip according to the numbers of the chips used for the optimized design, based on the VHDL description of the components in the functional module and the netlist with the smallest logic unit as the main body, and provide the external pin numbers of the chips. The VHDL description file is compiled using FPGA or CPLD to generate a configuration file for the (power-on) configuration of the chips;

[0060] A test stimulus system, which is used to provide test stimuli according to the input of the digital system, and perform simulations step by step according to the numbers of the chips. The output of the upper-level chip is used as the input stimulus of the lower-level chip until the digital output level.

[0061] Further preferably, the chip sequence is an FPGA or CPLD chip sequence.

[0062] Further preferably, the chip resource occupancy rate does not exceed 70%.

[0063] Further preferably, when the storage capacity of the current chip in the determined optimized chip sequence is greater than the total resources occupied by a single functional module, the number of merged functional modules is the ratio of 70% of the storage capacity of the chip to the total resources occupied by a single functional module;

[0064] If the design of a single functional module requires multiple chips, the number of required chips N is determined by dividing the total resources occupied by the functional module by 70% of the storage capacity of the chip.

[0065] In summary, compared with the prior art, the present invention has the following advantages:

[0066] The present invention provides a method and device for upgrading and optimizing system-level digital circuits. Among them, the digital system schematic diagram is utilized to the greatest extent to generate a component list and a netlist that characterizes the input and output signal characteristics. By describing the minimum logic unit of each component in VHDL language, a VHDL language description of the system is automatically established according to the netlist; the replaced database is divided into functional modules in combination with the input network name of the minimum logic unit and the implemented function of the minimum logic unit. Among them, the functional module is designed with the minimum logic units that implement the same operation into one module (this technical feature is not disclosed in the prior art. The prior art usually takes components as the main body and designs according to the input and output sequence of the digital system schematic diagram). Subsequently, an automatic allocation algorithm is adopted to merge or split the functional modules (when the storage capacity of the current chip in the determined optimized chip sequence is greater than the total resources occupied by a single functional module, multiple functional modules are merged; if the design of a single functional module requires multiple chips, the number of required chips N is determined according to the total resources occupied by the functional module and the storage capacity of the chip. For each chip, starting from the input pin number of 1 / N of the functional module, with the same type of network name taking precedence, the network topology diagram drawn according to the netlist with the minimum logic unit as the unit is expanded and searched until the output end of the digital system to be optimized for design, and additional pins generated by the cutting of the functional module are added), which can quickly realize the resource allocation of multiple chips.

[0067] For the method and device for upgrading and optimizing system-level digital circuits provided by the present invention, since the functional module is designed with the minimum logic units that implement the same operation into one module, therefore, whether it is the subsequent splitting or merging of the functional modules, when some functional modules in the system digital circuit fail or are upgraded, the same functional module can be directly used for replacement or upgrade, and the upgrading and transformation of the system-level digital circuit can be quickly and accurately realized.

[0068] Those skilled in the art can easily understand that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for upgrading and optimizing system-level digital circuits, characterized in that, it includes the following steps: S1: Generate a component list and a netlist according to the schematic diagram of the digital system to be upgraded and optimized, and determine the chip sequence for the optimized design according to the input and output levels and the number of components; among them, the netlist is used to record the input and output connection relationships between components; S2: Model the minimum logic units of each component in the component list using VHDL language, and calculate the resource requirements for each minimum logic unit; among them, the required resources include macro cells, CLBs, and the number of pins; S3: Convert the netlist with components as the main body into a netlist with minimum logic units as the main body using the VHDL language description of the minimum logic units; among them, the input net name is used to represent the input connection relationship of the minimum logic units; S4: Change the resistor-capacitor component circuit that cannot be modeled using VHDL language into a digital delay circuit description, change the monostable circuit into a digital trigger circuit description, and update the database of the workpiece list; S5: Combine the input net name of the minimum logic unit and the implemented functions of the minimum logic unit, divide the updated database into functional modules, and calculate the resource occupancy of each functional module; among them, the functional module is designed with the minimum logic units that implement the same operation into one module; S6: When the storage capacity of the chip used for the optimized design is greater than the total resource occupancy of a single functional module, then merge multiple functional modules; if the design of a single functional module requires multiple chips, then determine the required number of chips N according to the total resource occupancy of the functional module and the storage capacity of the chip. For each chip, starting from the 1 / N input pin number of the functional module, with the same type of net name being given priority, expand and search according to the network topology diagram drawn based on the netlist with minimum logic units as the unit until reaching the output end of the digital system to be optimized for design, and then add the additional pins generated by the functional module cutting on each designed chip.

2. The method for upgrading and optimizing system-level digital circuits according to claim 1, characterized in that, after S6, it further includes: S7: According to the numbers of the chips used for the optimized design, generate VHDL description files for each chip based on the VHDL descriptions of the components in the functional module and the netlist with minimum logic units as the main body, and provide the external pin numbers of the chips. Use FPGA or CPLD development software to compile the VHDL description files to generate configuration files for chip configuration; S8: Provide test stimuli according to the input of the digital system to be upgraded and optimized, and perform simulations step by step according to the numbers of the chips. The output of the upper-level chip is used as the input stimulus for the lower-level chip until reaching the output level of the digital system.

3. The method for upgrading and optimizing system-level digital circuits according to claim 1 or 2, characterized in that, the chip sequence is an FPGA or CPLD chip sequence.

4. The method for upgrading and optimizing system-level digital circuits according to claim 3, characterized in that, the resource occupancy rate of the chip does not exceed 70%.

5. The method for upgrading and optimizing system-level digital circuits according to claim 4, characterized in that, The number of combined functional modules in S6 is the ratio of 70% of the chip storage capacity divided by the total resource occupancy of a single functional module; If a single functional module design requires multiple chips, then the total resource occupancy of the functional module is divided by 70% of the chip storage capacity to determine the required number of chips N.

6. A system-level digital circuit upgrade and optimization device, characterized in that, it includes: A data construction system for generating a component list and a netlist according to the schematic diagram of the digital system to be upgraded and optimized, and determining the chip sequence for the optimized design based on the input and output levels and the number of components of each component; among them, the netlist is used to record the input and output connection relationships between components; A logic unit language modeling system for performing VHDL language modeling on the minimum logic unit of each component in the component list and calculating the resource requirements for each minimum logic unit; among them, the required resources include macro cells, CLBs, and the number of pins; A netlist conversion system for converting the component-based netlist into a minimum logic unit-based netlist using the VHDL language description of the minimum logic unit; among them, the input net name is used to represent the input connection relationship of the minimum logic unit; A circuit description system for non-VHDL language modeling, which changes the resistor-capacitor element circuit that cannot be modeled in VHDL into a digital delay circuit description, changes the monostable circuit into a digital trigger circuit description, and updates the database of the work list; A functional module construction system for dividing the updated database into functional modules by combining the input net name of the minimum logic unit and the implemented function of the minimum logic unit, and calculating the resource occupancy of each functional module; among them, the functional module is designed by combining the minimum logic units that perform the same operation into one module; When the chip storage capacity used for the optimized design is greater than the total resource occupancy of a single functional module, multiple functional modules are combined; if a single functional module design requires multiple chips, then the total resource occupancy of the functional module is divided by 70% of the chip storage capacity to determine the required number of chips. For each chip, starting from the 1 / N input pin number of the functional module, with the same type of net name being prioritized, expand the search according to the network topology diagram drawn based on the minimum logic unit-based netlist until reaching the output end of the digital system to be optimized for design, and at the same time add the additional pins generated by the functional module cutting.

7. The system-level digital circuit upgrade and optimization device according to claim 6, characterized in that, it further includes: A configuration file generation system for generating VHDL description files for each chip according to the numbers of the chips in the chip sequence, based on the VHDL descriptions of the components in the optimized design functional modules and the minimum logic unit-based netlist, and providing the external pin numbers of the chips, and using FPGA or CPLD development software to compile the VHDL description files to generate configuration files for configuring the chips used in the optimized design; A test stimulus system for providing test stimuli according to the input of the digital system, performing simulations step by step according to the numbers of the chips, and using the output of the upper-level chip as the input stimulus for the lower-level chip until the digital output level.

8. The system-level digital circuit upgrade and optimization device according to claim 6 or 7, characterized in that, the chip sequence is an FPGA or CPLD chip sequence.

9. The system-level digital circuit upgrade and optimization device according to claim 8, characterized in that, the chip resource occupancy rate does not exceed 70%.

10. The system-level digital circuit upgrade and optimization device according to claim 9, characterized in that, when the chip storage capacity used for the optimized design is greater than the total occupied resources of a single functional module, the number of merged functional modules is the ratio of 70% of the chip storage capacity divided by the total occupied resources of a single functional module; if a single functional module design requires multiple chips, the number of required chips N is determined by dividing the total occupied resources of the functional module by 70% of the chip storage capacity.

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