Delay adjustment circuit

Abstract

This application relates to delay adjustment circuits. An amplifier (e.g., a differential amplifier) ​​may function similarly to a variable capacitor (e.g., due to the Miller effect) to control the delay of signals between buffer (e.g., a transition driver) stages. The gain of the amplifier can be adjusted by changing the current passing through it, which alters the apparent capacitance experienced by the signal lines (due to the Miller effect). The capacitance of each amplifier may be the intrinsic capacitance of the input transistors that make up the amplifier, or it may be a discrete capacitor. In some instances, two differential stages may be inserted into a four-phase timing system (e.g., one on the 0 and 180° phases, and another on the 90 and 270° phases) and may be differentially controlled to control the inter-phase delay.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 351,421, entitled “Delay Adjustment Circuits,” filed June 18, 2021, by Maksim Kuzmenka et al., which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field involves delay adjustment circuits. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states and can store any one of those states. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. For example, non-volatile memories such as FeRAM can maintain their stored logic state for a long time, even without external power. Volatile memory devices such as DRAM may lose their stored state when disconnected from external power. Summary of the Invention

[0006] Describe a device. The device may include a signal line and circuitry configured to provide a load on the signal line, the circuitry including: an amplifier having an input coupled to the signal line, the amplifier having an impedance between the input and a node of the amplifier, the amplifier having a gain at the node relative to the input; and a sub-circuit coupled to the amplifier and configured to control the gain of the amplifier.

[0007] Describe a device. The device may include: a set of signal lines extending from a first end to a second end, the set of signal lines being configured to distribute signals of a multiphase clock; and circuitry coupled to the set of signal lines, the circuitry being configured to provide a load on the set of signal lines, the circuitry including: a set of amplifiers having a set of inputs coupled to the set of signal lines, the set of amplifiers having respective gains at nodes of the set of amplifiers relative to respective inputs of the set of inputs; and a sub-circuit coupled to the set of amplifiers, the sub-circuit being configured to control the respective gains of the set of amplifiers.

[0008] Describe a method. The method may include: establishing a delay of a signal on a signal line coupled to the input of an amplifier by setting a gain of an amplifier between a node of an amplifier and the input of the amplifier, the amplifier having an impedance between the input and the node; determining to change the delay of the signal on the signal line; and adjusting the delay of the signal on the signal line by changing the gain of the amplifier. Attached Figure Description

[0009] Figure 1 Examples of systems supporting delay adjustment circuits according to the examples disclosed herein are shown.

[0010] Figure 2 An example of a memory die supporting delay adjustment circuitry according to the examples disclosed herein is shown.

[0011] Figures 3A-3B Examples of circuits and associated timing diagrams supporting delay adjustment circuits according to the examples disclosed herein are shown.

[0012] Figures 4A-4C Examples of circuits and associated timing diagrams supporting delay adjustment circuits according to the examples disclosed herein are shown.

[0013] Figure 5 Examples of circuits supporting delay adjustment circuits according to the examples disclosed herein are shown.

[0014] Figure 6 Examples of circuits supporting delay adjustment circuits according to the examples disclosed herein are shown.

[0015] Figures 7A-7C Examples of circuits and associated timing diagrams supporting delay adjustment circuits according to the examples disclosed herein are shown.

[0016] Figure 8 A block diagram illustrating a memory device supporting delay adjustment circuitry based on the examples disclosed herein.

[0017] Figure 9A flowchart is shown, illustrating a method for supporting delay adjustment circuitry based on the examples disclosed herein. Detailed Implementation

[0018] Four-phase timing is used in many memory systems because each phase can operate at about half the speed of a typical two-phase timing system. Operating at these lower speeds allows for a smaller number of buffers (e.g., adapter drivers) to propagate the clock signal, and therefore makes it more stable relative to process, voltage, and temperature variations. However, four-phase timing can present challenges. For example, some phases may become out of sync with other phases (e.g., delayed or offset), which can lead to timing problems. Mitigating these phase offset issues can be difficult.

[0019] Apparatus and methods are provided in which an amplifier (e.g., a differential amplifier) ​​may function similarly to a variable capacitor (e.g., due to the Miller effect) to control the delay of signals between buffer (e.g., a transition driver) stages. The gain of the amplifier can be adjusted by changing the current passing through the amplifier, which alters the apparent capacitance experienced by the signal lines (due to the Miller effect). The capacitance of each amplifier may be the intrinsic capacitance of the input transistors that make up the amplifier, or it may be a discrete capacitor. In some instances, two differential stages may be inserted into a four-phase timing system (e.g., one on the 0 and 180° phases, and another on the 90 and 270° phases) and may be differentially controlled to control the inter-phase delay.

[0020] First, as referenced Figure 1 and 2 The features of this disclosure are described in the context of the system and the bare die. (See references...) Figure 3A-7C The features of this disclosure are described in the context of the circuits and timing diagrams described herein. Further details are provided by reference to [reference needed]. Figure 8 and 9 The device diagrams and flowcharts describing the delay adjustment circuitry illustrate and describe these and other features of this disclosure with reference to the device diagrams and flowcharts.

[0021] Figure 1 An example of a system 100 supporting delay adjustment circuitry according to the examples disclosed herein is shown. System 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 and the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0022] System 100 may include portions of electronic devices, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, internet-connected devices, vehicle controllers, etc. Memory device 110 may be a component of the system operable to store data from one or more other components of system 100.

[0023] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory to execute processes, such as in a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or other fixed or portable electronic device, and other instances. In some instances, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0024] Memory device 110 may be a separate device or component operable to provide physical memory address / space available for use or reference by system 100. In some instances, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals, various pin configurations for transmitting signals, various form factors for the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0025] Memory device 110 may be operable to store data of components of host device 105. In some instances, memory device 110 may act as a secondary or subordinate device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). These commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0026] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device 105 may be coupled to each other using bus 135.

[0027] Processor 125 may provide control or other functionality operable for at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In these examples, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, and other examples. In some examples, external memory controller 120 may be implemented by or be part of processor 125.

[0028] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.

[0029] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tesserials, one or more segments), wherein each memory cell is operable to store at least one bit of data. Memory device 110 including two or more memory dies 160 may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0030] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and are operable to receive, transmit, or execute commands, data, or control information associated with components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controller 120, the one or more memory dies 160, or the processor 125. In some instances, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with a local memory controller 165 of the memory die 160.

[0031] A local memory controller 165 (e.g., local to memory die 160) may include circuitry, logic, or components operable to control the operation of memory die 160. In some instances, the local memory controller 165 may be operable to communicate with a device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include a device memory controller 155, and either the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165 or both may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating the received signals, an encoder for encoding or modulating the signals to be transmitted, or various other circuitry or controllers operable to support the operation of the described device memory controller 155 or the local memory controller 165 or both.

[0032] The device memory controller 155 or the local memory controller 165 can be used to determine the amount of delay to be added to one or more signals, and based on its control, to add delay to the circuitry of the signals. For example, the signals can be input to the controller, which can determine the amount of delay to be added to one or more of the signals, and the controller's output can provide feedback to the delay control circuitry.

[0033] External memory controller 120 may be operable to enable the transfer of one or more of the information, data, or commands between components of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 may translate or interpret the communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120, or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125 or other components of system 100 or host device 105. Although external memory controller 120 is depicted as being external to memory device 110, in some instances, external memory controller 120, or the functionality described herein, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0034] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths operable to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be operable to act as part of a channel.

[0035] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, signaling may be transmitted via channel 115 using single data rate (SDR) signaling or dual data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0036] Figure 2 An example of a memory die 200 supporting delay adjustment circuitry according to the examples disclosed herein is shown. The memory die 200 may be a reference. Figure 1 Examples of the described memory die 160. In some instances, the memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. The memory die 200 may include one or more memory cells 205, each of which may be programmable to store different logical states (e.g., programmed to one of a set of two or more possible states). For example, the memory cell 205 may be operable to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, the memory cell 205 (e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, the memory cells 205 may be arranged in an array, such as referenced in [reference needed]. Figure 1 The memory array 170 is described.

[0037] Memory cell 205 may store charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor containing a dielectric material to store charge representing a programmable state. In other memory architectures, other memory devices and components are possible. For example, a nonlinear dielectric material may be used. Memory cell 205 may include logic memory components such as capacitor 230, and switching components 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. Nodes of capacitor 230 may be coupled to a voltage source 240, which may be a cell board reference voltage, such as Vpl, or ground, such as Vss.

[0038] The memory die 200 may include one or more access lines (e.g., one or more word lines 210 and one or more digital lines 215) arranged in a pattern such as a grid pattern. The access lines may be conductive lines coupled to memory cells 205 and used to perform access operations on memory cells 205. In some instances, word lines 210 may be referred to as row lines. In some instances, digital lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, or bit lines may be interchanged without affecting understanding or operation. Memory cells 205 may be located at the intersection of word lines 210 and digital lines 215.

[0039] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting one or more access lines, such as word line 210 or digital line 215. A single memory cell 205 can be accessed at its intersection point by biasing word line 210 and digital line 215 (e.g., by applying voltage to word line 210 or digital line 215). The intersection point of word line 210 and digital line 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of memory cell 205.

[0040] The access memory unit 205 can be controlled via row decoder 220 or column decoder 225. For example, row decoder 220 can receive a row address from local memory controller 260 and activate word line 210 based on the received row address. Column decoder 225 can receive a column address from local memory controller 260 and activate digital line 215 based on the received column address.

[0041] The selection or deselection of memory cell 205 can be achieved by activating or deactivating switch assembly 235 using word line 210. Capacitor 230 can be coupled to digital line 215 using switch assembly 235. For example, when switch assembly 235 is deactivated, capacitor 230 can be isolated from digital line 215, and when switch assembly 235 is activated, capacitor 230 can be coupled to digital line 215.

[0042] Sensing component 245 may be operable to detect the state (e.g., charge) stored on capacitor 230 of memory cell 205 and determine the logic state of memory cell 205 based on the stored state. Sensing component 245 may include one or more sensing amplifiers to amplify or otherwise convert signals generated by accessing memory cell 205. Sensing component 245 may compare the signal detected from memory cell 205 with reference 250 (e.g., reference voltage). The detected logic state of memory cell 205 may be provided as an output of sensing component 245 (e.g., provided to input / output 255) and may indicate the detected logic state to another component of the memory device including memory die 200.

[0043] The local memory controller 260 can control access to the memory cell 205 via various components (e.g., row decoder 220, column decoder 225, sensing component 245). The local memory controller 260 can be a reference. Figure 1Examples of local memory controller 165 described. In some instances, one or more of row decoder 220, column decoder 225, and sensing components 245 may be cooperatively located with local memory controller 260. Local memory controller 260 may be operable to receive one or more commands or data from one or more different memory controllers (e.g., external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transfer data from memory die 200 to host device 105 based on the performance of said one or more operations. Local memory controller 260 may generate row signals and column address signals to activate target word line 210 and target digital line 215. Local memory controller 260 may also generate and control various voltages or currents used during operation of memory die 200. Generally speaking, the amplitude, shape, or duration of the applied voltage or current discussed in this article may vary and may differ for the various operations discussed in the process of operating the memory die 200.

[0044] The local memory controller 260 can be used to determine the amount of delay to be added to one or more signals, and based on its control, a circuit system can add delay to the signals. For example, signals can be input to the local memory controller 260, which can determine the amount of delay to be added to one or more of the signals, and the output of the local memory controller 260 can provide feedback to the delay control circuit system.

[0045] The local memory controller 260 may be operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from the host device 105). The local memory controller 260 may be operable to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0046] Figure 3A and 3B An example of a circuit 300 supporting delay adjustment circuitry according to an example disclosed herein and an associated timing diagram 301 are shown. Circuit 300 can be used in a memory device (e.g., as shown in reference 1). Figure 1The described memory device 110 provides a load on signal line 305, thereby causing a delay in the signal P (e.g., a clock signal) on signal line 305 as the signal passes through buffer 310. In some instances, circuitry 300 may be included on the memory die (e.g., as referenced). Figure 1 The memory die 160 described is located on the memory die. In other instances, all or part of the circuitry 300 may be located outside the memory die. The circuitry 300 may include an amplifier 315 and a sub-circuit 320.

[0047] The input 325 of amplifier 315 may be coupled to signal line 305. Amplifier 315 may have an output node 330, wherein there is an impedance between output node 330 and input 325. The impedance may include capacitor 328. The capacitance may be provided by one or more discrete capacitors coupled between output node 330 and input 325, or may be intrinsic capacitance of one or more devices of amplifier 315, or a combination thereof. Amplifier 315 may have a gain at output node 330 relative to input 325. The gain may be the ratio of the power or amplitude of the signal generated at output node 330 to the power or amplitude of the corresponding signal at input 325.

[0048] The amplifier may include an input device (e.g., transistor 335) coupled to input 325 of amplifier 315. Capacitor 328 may include the intrinsic capacitance of the input device. In some instances, transistor 335 may be a field-effect transistor (FET). The gate of transistor 335 may be coupled to signal line 305. In some instances, transistor 335 may be configured in a common-source configuration, wherein input 325 of the amplifier is coupled to the gate of the transistor.

[0049] A first node 340 (e.g., drain) of transistor 335 may be coupled to a voltage source via a load 345 (e.g., a resistor). This first node 340 may be the output node of an amplifier. The transistor may include impedance between the first node 340 and the gate. The impedance of transistor 335 may include the intrinsic capacitance of transistor 335 between the first node 340 and the gate. The impedance of amplifier 315 between output node 330 and input 325 may include the impedance of transistor 335. The gain of amplifier 315 may include the gain of transistor 335 between the first node 340 and the gate. The circuit may be configured such that the delay of a signal on signal line 305 can be controlled by adjusting the gain of transistor 335.

[0050] Sub-circuit 320 may be coupled to amplifier 315 to control the gain of amplifier 315. In some cases, the gain of an amplifier (e.g., a transistor) may depend on the amount of current supplied to the amplifier (e.g., the transistor) to pass through it. In some instances, sub-circuit 320 may include transistor 350 that supplies current to amplifier 315 (e.g., as a current source). Figure 3A In one example, transistor 350 and transistor 335 are coupled in a current source configuration: a first node 355 (e.g., drain) of transistor 350 is coupled to a second node 341 (e.g., source) of transistor 335, and a second node 356 (e.g., source) of transistor 350 is coupled to ground. The gate of transistor 350 may receive a bias voltage on a control line 370, which controls the amount of current flowing through transistor 350 to provide current to transistor 335 of amplifier 315. In some examples, the bias voltage may be varied to control the amount of current provided to transistor 335. Furthermore, by changing the amount of current provided to transistor 335, transistor 350 can control the gain of transistor 335.

[0051] The Miller effect is a phenomenon in an inverting voltage amplifier (e.g., transistor 335) where the equivalent input capacitance (e.g., experienced as by signal line 305) increases due to the amplification of the effect attributable to the capacitance between the amplifier's input and output terminals. The actual increase in input capacitance attributable to the Miller effect is given by the following equation:

[0052] C M =C(1+A) v ),

[0053] Where -A v The voltage gain (A) of the inverting amplifier v (positive), and C is the feedback (e.g., intrinsic) capacitor. Because the intrinsic capacitance C remains constant, the amplifier's capacitance C... M (As the signal line traverses) and the amplifier gain A v It is directly proportional. Therefore, the capacitance C can be changed or controlled by changing the gain. M (As the signal line goes through).

[0054] Remember this, Figure 3B This demonstrates how the bias voltage of transistor 350 can be used to control the delay of signal P on signal line 305. The top part of the diagram (labeled "P") in The figure can represent the signal P measured on the input 360 side of the buffer 310, and the bottom part of the figure (labeled "P") can represent the signal P measured on the input 360 side of the buffer 310. out ") can represent the signal P measured on the output side 365 of the buffer 310. Thus, P in and P outThe signal P before and after propagation via buffer 310 can be depicted. In the example shown, the signal can be at a low voltage (V). L ) and high voltage (V H The buffer 310 can move up and down between V. The buffer 310 may have a trigger output transition (e.g., from V...). L To V H (and vice versa) V L and V H A specific value between (e.g., value V) tr The trigger or breakpoint at ().

[0055] Figure 3B The diagram illustrates two cases where different bias values ​​B1 and B2 are applied to transistor 350 via control line 370. Different bias values ​​result in different amounts of current being supplied to transistor 355, which may produce different corresponding gains A1 and A2 in transistor 355. According to the Miller effect, different gains A1 and A2 can produce different corresponding capacitances C in the load. M(1) and C M(2) (For example, as experienced by signal line 305), this may affect the slew rate or slope of the signal on signal line 305.

[0056] When the bias voltage is B1, input signal 380 and output signal 385 can be generated (input and output signals 380 and 385 are in...). Figure 3B (Drawn as a solid line in the middle). The input signal 380 (and the subsequent output signal 385) can be initially at V. L Then it turns upwards to V. H And it dropped back to V L (For example, as a clock signal). Input signal 380 may begin at time t1 from V with a general slope S. L Transition to V H The slope S can depend on the capacitance C. M(1) As the input signal 380 increases, it can become equal to V at time t2. tr This can trigger the buffer 310 to propagate upwards, causing the output signal 385 to start from V L To V H The transition. Input signal 380 can then begin at time t4 from V with the same slope S. H Shift back to V L When the input signal 380 becomes equal to V at time t5. tr At this time, the buffer 310 can be triggered to propagate downwards, thereby causing the output signal 385 to start from V H To V L The transformation.

[0057] When the bias voltage is changed to B2, input signal 390 and output signal 395 are generated. Input and output signals 390 and 395 are similar to input and output signals 380 and 385 associated with B1, with a few exceptions (in... Figure 3B (Depicted by dashed lines). For example, similar to input signal 380, input signal 390 can start at time t1 from V L Transition to V H And at time t4, from V H Transition to V L However, this is attributed to different capacitances C. M(2) Because of this, the slope S is less than that of the input signal 380. Therefore, the input signal 390 can become equal to V at time t3, which is later than time t2. tr This causes the upward transition in output signal 395 to be delayed (relative to output signal 385) by Δt = t3 - t2. A similar delay can occur in the downward transition, which begins at time t4, causing the downward transition in output signal 395 to begin at a delayed time t6, resulting in the same delay Δt. Therefore, output signal 395 can be delayed by Δt relative to output signal 385.

[0058] As can be seen, changing the bias voltage or gain of the amplifier can cause the delay to increase or decrease, depending on the value of the bias voltage. In other words, the delay of signal P can be adjusted by adjusting the value of the bias voltage applied to transistor 350. Thus, the delay that signal P may experience as the signal propagates through signal line 305 of buffer 310 can be changed by changing the gain of amplifier 315, which can be changed by adjusting the current supplied to amplifier 315, which can be changed by changing the bias voltage applied to transistor 350 (which acts as the current source for amplifier 315).

[0059] In some instances, a circuit 300 with a set of associated signal lines 305 (e.g., multiphase clock signal lines) can be utilized. For example, a single circuit 300 can be coupled to a corresponding signal line 305, and the delay of the corresponding signal can be controlled using the bias voltage of each circuit 300. In some instances, two or more control lines 370 in the circuit 300 can be coupled together to provide the same bias voltage to the corresponding circuit. This allows the delay of more than one signal to be controlled using a single bias voltage.

[0060] Figures 4A-4CAn example of a circuit 400 supporting delay adjustment circuitry according to an example disclosed herein and an associated timing diagram 401 are shown. Circuit 400 can be used to provide a load on a set of signal lines 405, thereby causing a delay relative to each other for one or more signals (e.g., multiphase clock signals) as the signals pass through buffer 410. In some instances, circuit 400 may be included in a memory die (e.g., as referenced). Figure 1 The memory die 160 described is located on the memory die. In other instances, all or part of the circuitry 400 may be located outside the memory die. The circuitry 400 may include a set of amplifiers 415 (e.g., amplifiers 415-a and 415-b) and sub-circuit 420.

[0061] In some instances, the signals may represent multiphase clock signals. For example, the group of signal lines 405 may be configured to distribute signals for a multiphase clock (e.g., a four-phase clock). In some instances, the signal lines 405 may distribute signals representing phases 0, 90, 180, and 270 of the four-phase clock (e.g., P0, P180, P270, and P280).

[0062] Figure 4B This describes the timing of the phase signals (P0, P90, P180, and P270) of a four-phase clock and the clock signal (Clk) from which they can be derived. In an ideal four-phase clock, each of the phase signals (P0, P90, P180, and P270) is 90 degrees out of phase with the preceding phase signal. For example, P270 is 90 degrees out of phase with P180, P180 is 90 degrees out of phase with P90, P90 is 90 degrees out of phase with P0, and P0 is 90 degrees out of phase with P270, as illustrated. The clock signal (Clk) can be derived by triggering a transition (e.g., from low to high, or vice versa) when a rising edge is detected on any of the phase signals. For example, at time t1, Clk can transition to high based on the rising edge of P0; and at time t2, Clk can transition to low based on the rising edge of P90. This up-down transition of Clk can continue in a similar manner as rising edges of P180 and P270 are encountered at t3 and t4, respectively. This process itself can be repeated whenever rising edges of P0, P90, P180, and P270 are encountered again (e.g., at times t5, t6, t7, and t8).

[0063] One advantage of this method is that a clock signal with approximately 50% duty cycles can be derived, which can have a clock rate as fast as twice that associated with any of the phase signals. However, a potential problem is that one or more of the phase signals may become out of phase relative to the other signals. For example, if P0 and P180 are not 90 degrees out of phase relative to the phase signals P90 and P270, the derived clock signal may be skewed (e.g., not having 50% duty cycles), resulting in, for example... Figure 4C The clock signals Clk-1 or Clk-2 shown in the diagram. This problem can be alleviated using circuit 400.

[0064] Return to Figure 4A The group of signal lines 405 may extend from the first end 425 to the second end 430. A group of buffers 410 (e.g., a transition driver) may be coupled to the group of signal lines 405 to boost the signal as it propagates from the first end 425 to the second end 430. Each buffer 410 may be coupled to more than one signal line.

[0065] like Figure 4C As shown, each buffer 410 may include a differential amplifier 435 having two inputs 411 and 412 and two outputs 413 and 414. The inputs and outputs may be coupled to signal lines 405 between first and second terminals 425 and 430. In some instances, the inputs and outputs of each differential amplifier 435 may correspond to phases out of phase with respect to each other. For example, inputs 411 and 412 may be coupled to P0. in and P180 in The signal lines are coupled, and outputs 413 and 414 can be connected to associated P0. out and P180 out Signal line coupling. The bias voltage applied to differential amplifier 435 can supply a constant current source to differential amplifier 435. Signals in inputs 411 and 412 can travel on a signal trace from one of the sources and thus have a degraded slew rate, while differential amplifier 435 can output buffered differential signals with a higher slew rate than inputs 411 and 412 at outputs 413 and 414.

[0066] Buffer 410 may employ current-mode logic (CML), where the current from a current generator (e.g., transistor 440) may switch between two alternative paths depending on whether it represents logic zero or logic one. In some instances, the generator may be connected to the two sources of a pair of differential FETs (e.g., transistors 442-a and 442-b), with the two paths serving as their two drains (e.g., outputs 413 and 414).

[0067] See also Figure 3AAs discussed, a single circuit (e.g., a single circuit 300) can be coupled to a corresponding signal line (e.g., signal line 405), and the corresponding bias voltage of the circuit can be used to control the delay of the corresponding signal. In some instances, the control lines 370 of two or more circuits can be coupled together to provide the same bias voltage to the corresponding circuit. In some instances, instead of coupling control lines together, or in combination, a single current source can provide current to more than one transistor. This also allows the use of a single bias voltage to control the delay of signals on more than one signal line.

[0068] In some instances, amplifier 415 may be formed by a pair of amplifiers (e.g., amplifier 315) configured to be coupled to different signal lines. For example, each amplifier 415 may include a pair of transistors 335-a and 335-b coupled to a corresponding signal line 405. See also... Figure 3A The amplifier 415, transistors 335-a and 335-b, can be coupled to a voltage source via corresponding loads 345-a and 345-b (e.g., resistors), and may include corresponding capacitors 328-a and 328-b between the output node and the input of the transistors. In some instances, transistors 335-a and 335-b may be coupled together in a differential arrangement (e.g., by coupling the source nodes of the transistors together). In those cases, amplifier 415 may be a differential amplifier. Similar to subcircuit 320, subcircuit 420 may include transistor 350 configured to supply current to amplifier 415. Transistor 350 may be coupled to both transistors 335-a and 335-b to supply current thereto. In this arrangement, a bias voltage applied to transistor 350 via control line 370 can simultaneously control the amount of current supplied to both transistors 335-a and 335-b, which can control the delay of the associated signal. In some instances, amplifier 415 may be coupled to signal lines having signals that are inverted from each other (e.g., amplifier 415-a may be coupled to signals P0 and P180, and amplifier 415-b may be coupled to signals P90 and P270), so that inverted signals can be delayed by the same amount by the amplifier.

[0069] Subcircuit 420 may include multiple transistors 350, each associated with a different amplifier 415. For example, subcircuit 420 may include transistors 350-a and 350-b for supplying current to amplifiers 415-a and 415-b, respectively. The bias voltages (e.g., Bias0 and Bias90) of transistors 350 can be manipulated individually to adjust the delay of signal pairs (e.g., signals P0 / P180 and P90 / P270) relative to each other. Thus, for example, if phasing signals 90 and 270 are out of phase relative to phasing signals 0 and 180, they can be brought back into phase by adjusting one of the bias voltages. In some cases, the signals may be measured and the bias voltages set accordingly during the manufacture of the memory device. In other cases, the signals may be monitored periodically and the bias voltages set accordingly during use. Monitoring the signals and / or manipulating the bias voltages may be done manually or in any other way by a controller (e.g., device memory controller 155 or local memory controller 165).

[0070] Figure 5 An example of circuit 500 supporting delay adjustment circuitry according to the examples disclosed herein is shown. Circuit 500 is similar to circuit 400, except that in circuit 500, differential amplifier 415 can be differentially controlled by sub-circuit 520. In some instances, two transistors 350-a and 350-b can be coupled together in a differential arrangement (e.g., by coupling the source nodes of the transistors together). The differential circuitry can be controlled by differential signals (e.g., V_ctrl_p and V_ctrl_n) on control lines 370-a and 370-b of transistors 350-a and 350-b. One advantage of this approach is that the current supplied to amplifier 415 by sub-circuit 520 can be primarily sensitive to the difference between control voltages (e.g., V_ctrl_p and V_ctrl_n), rather than their absolute values.

[0071] In some instances, resistor 525 and the second set of transistors 560-a and 560-b may be coupled between transistors 350-a and 350-b in a second differential arrangement. In some instances, the control lines 570 of the second set of transistors 560-a and 560-b may be connected together. Resistor 525 determines the sensitivity of the second set of transistors 560-a and 560-b to the control voltages (e.g., V_ctrl_p and V_ctrl_n) of transistors 350-a and 350-b. If resistor 525 is at or near 0Ω (e.g., closed circuit), the sensitivity can be high, and the subcircuit can function as a classic differential amplifier. If resistor 525 is at a large value (e.g., open circuit), the control voltages (e.g., V_ctrl_p and V_ctrl_n) of transistors 350-a and 350-b may have little or no effect on the tail current supplied to amplifier 415.

[0072] Using differential signals to control the amplifier produces good power supply rejection ratio and common-mode noise rejection for the control voltage. However, if one of the control voltages (e.g., v_ctrl_p) is close to zero, parasitic signal paths between the inputs of the differential amplifier 415 (e.g., between the gates of transistors 335-a and 335-b) can persist, and the equivalent input capacitance (even without considering Miller capacitance) can be relatively large. Therefore, this circuit can only be used over a relatively narrow delay adjustment range.

[0073] Figure 6 An example of a circuit supporting a delay adjustment circuit according to the examples disclosed herein is shown. Circuit 600 can be configured to provide separate current to each of the transistors in the amplifier. This remedies some of the problems discussed in reference circuit 500. Circuit 600 can be similar to circuit 500, except that in each amplifier 615, the coupling between transistors 335-a and 335-b can be removed, and transistors 350-a and 350-b of sub-circuit 620 can each be divided into two separate transistors (e.g., replaced by said two separate transistors) providing separate current to each transistor 335-a and 335-b. For example, transistor 350-a can be replaced by transistors 350-a1 and 350-a2, which can be individually coupled to transistors 335-a and 335-b of the first amplifier 615-a, respectively. Similarly, transistor 350-b can be replaced by transistors 350-b1 and 350-b2, which can be individually coupled to transistors 335-a and 335-b of amplifier 615-b (second amplifier 615-b), respectively.

[0074] These changes effectively isolate the transistors 335 of each amplifier 615 from each other, thereby removing parasitic paths between the inputs of the differential amplifier (e.g., between the gates of transistors 335-a and 335-b). Therefore, the capacitance of the amplifier 615, attributed to the Miller effect, can become dominant, even if one of the control voltages (e.g., V_ctrl_p and V_ctrl_n) is close to zero. Thus, circuit 600 can be used over a wide delay adjustment range. In some instances, a delay fine-tuning range of + / -10 psec can be achieved with a single stage of circuit 600. Additional delay fine-tuning can be added in subsequent stages.

[0075] Figures 7A-7C An example of a circuit 700 supporting delay adjustment circuitry according to the examples disclosed herein and an associated timing diagram are shown. Circuit 700 may be implemented as referenced. Figure 1-6Aspects of the system described herein. For example, circuit 700 may include a set of amplifiers 715 and sub-circuits 720, which may be similar to or include any of the amplifiers and sub-circuits discussed herein. Circuit 700 may further include a second circuit 780.

[0076] In some instances, feedback can be used to provide correction (e.g., alignment) for delays already added to a signal. For example, the amount of delay caused to occur on a multiphase clock signal can be used to help correct for the amount of delay continuing to be added to the signal (e.g., in a locked-loop type configuration). A second circuit 780 can provide this feedback. The second circuit 780 can control the bias of the delay control sub-circuit 720 (e.g., Bias0 and Bias90) based on amplifier 715.

[0077] Amplifier 715 may be coupled to a set of signal lines 405 associated with a set of signals (e.g., quad-phase clock signals P0, P180, P90, and P270) on the input side 736 of the same set of buffers 410. The load caused by amplifier 715 on signal lines 405 may cause one or more of the signals to be delayed relative to the rest of the signals as they propagate through the set of buffers 410, as discussed herein. That is, a set of inverted signals (e.g., signal P0) on the output side 737 of buffer 410 out / P180 out Or P90 out / P270 out The set of inverted signals (e.g., signal P0) on the input side 736 of buffer 410 are relative to the set of inverted signals on the input side 736 of buffer 410. in / P180 in Or P90 in / P270 in There may be a delay.

[0078] Feedback circuit 780 may be coupled to the group signal line 405 on the output side 737 of buffer 410 to obtain the group of delayed signals (e.g., signal P0). out P180 out P90 out and P270 out The feedback circuit 780 may include a circuit system capable of deriving a clock signal based on the delayed signal. Figure 7A In one example, the circuit system may contain multiple NAND gates that are coupled to and to each other with different combinations of signal lines 405 on the output side 737 of buffer 410 to generate signals Clk1 and Clk2 representing the derived clock signal and its inverted form based on a delayed four-phase clock signal. Figure 7B Depicted in signal P0 out P180 out P90out and P270 out Examples of clock signals Clk1 and Clk2 that can be obtained when the ideal four-phase clock signal is depicted. The derived clock signals Clk1 and Clk2 can be used to determine or adjust the bias voltage of sub-circuit 720 (e.g., Bias0 and Bias90).

[0079] In some instances, the derived clock signals Clk1 and Clk2 can each pass through an RC circuit to obtain an integral signal for each. For example, the derived clock signal Clk1 can pass through an RC circuit containing capacitor C1 and resistor R5 to obtain a first integral signal Int1, and the derived clock signal Clk2 can pass through an RC circuit containing capacitor C2 and resistor R6 to obtain a second integral signal Int2. The integral signals Int1 and Int2 reflect the duty cycle of the clock signals Clk1 and Clk2. For an ideal clock, for example... Figure 7B As shown, the duty cycles of signals Clk1 and Clk2 can both be approximately 50%. When this is the case, the integral signals Int1 and Int2 can be at approximately the same level, such as... Figure 7B As depicted in the text.

[0080] If the operating cycles of signals Clk1 and Clk2 are different from each other, then one of the group of inverted signals in the four-phase signal set may be out of sync with respect to the group of inverted signals. For example, Figure 7C Describe when the inverted signal P0 out / P180 out With inverted signal P90 out / P270 out Examples of clock signals Clk1 and Clk2 available when asynchronous. As shown, the phase-inverted signal P90 is also included. out and P270 out The inverted signal P0 relative to the fixed phase out and P180 out The shifting makes the working cycles of the derived clock signals Clk1 and Clk2 significantly different from each other. This can cause the integration signals Int1 and Int2 to be at different levels, such as... Figure 7C As depicted in the text.

[0081] Integral signals Int1 and Int2 can be used to determine the amount of bias to be applied to transistor 350 of subcircuit 720. In some instances, integral signals Int1 and Int2 may be or provide bias signals (e.g., Bias0 and Bias90). For example, integral signals Int1 and Int2 may be input to operational amplifier 785, and the output of operational amplifier 785 may be coupled to control line 370 of transistor 350. If the clock is at or near 50% duty cycle, the bias applied to transistor 350 associated with the set of inverted signals (e.g., signals P0 / P180 and P90 / P270) may be substantially the same, such that the set of inverted signals are not delayed relative to each other. However, if the clock is not at or near 50% of its duty cycle, the bias applied to one transistor 350 can be higher than the bias applied to the other transistors 350, so that the associated inverted signal group (e.g., inverted signal group P0 / P180 or P90 / P270) can be delayed relative to the other inverted signal groups to bring the clock's duty cycle back to approximately 50%.

[0082] In some instances, a controller (e.g., device memory controller 155 or local memory controller 165) may be used in place of or in combination with operational amplifier 785: integration signals Int1 and Int2 may be input to the controller, which may determine the amount of one or more delays to be added to the signals, and the output of the controller may control the input of control line 370 of transistor 350 via a control circuit system.

[0083] Figure 8 A block diagram 800 illustrates a memory device 820 supporting delay adjustment circuitry according to an example disclosed herein. The memory device 820 may be as described in the reference... Figures 1 to 7C Examples of aspects of the described memory device. Memory device 820 or its various components may be examples of constructs for performing various aspects of the delay adjustment circuitry described herein. For example, memory device 820 may include a delay manager 825, a determiner component 830, a current manager 835, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0084] Delay manager 825 may be configured or otherwise supported to establish a delay of a signal on a signal line coupled to the input by setting the amplifier gain between the amplifier's node and the amplifier's input, the amplifier having an impedance between the input and the node. Determiner component 830 may be configured or otherwise supported to determine a change in the delay of a signal on the signal line. Delay manager 825 may be configured or otherwise supported to adjust the delay of a signal on the signal line by changing the amplifier gain.

[0085] In some instances, to support changes in amplifier gain, the current manager 835 can be configured or otherwise support components for adjusting the current supplied to the amplifier.

[0086] In some instances, the delay manager 825 may be configured or otherwise support components for: establishing a second delay of a second signal on the second signal line by setting a second gain of the second amplifier at a second node relative to the second input, in conjunction with the delay of a signal on a second signal line coupled to a second input of a second amplifier, wherein the second amplifier has a second impedance between the second input and the second node. In some instances, the delay manager 825 may be configured or otherwise support components for: adjusting a second delay of a second signal on the second signal line by changing a second gain of the second amplifier, in conjunction with the delay of a signal on the adjustment signal line.

[0087] In some instances, to support changes in amplifier gain, the current manager 835 may be configured or otherwise support components for adjusting the current supplied to the amplifier. In some instances, to support changes in the second gain of the second amplifier, the current manager 835 may be configured or otherwise support components for adjusting the second current supplied to the second amplifier.

[0088] In some instances, to support adjusting the current supplied to the amplifier and adjusting the second current supplied to the second amplifier, the current manager 835 may be configured or otherwise support components for adjusting the bias voltage of the third input of the transistor coupled to the amplifier and the second amplifier.

[0089] Figure 9 A flowchart illustrating a method 900 supporting delay adjustment circuitry according to an example disclosed herein is provided. Operation of method 900 may be implemented by a memory device or its components as described herein. For example, it may be implemented by a device as described in the references... Figures 1 to 8 The described memory device performs the operation of method 900. In some instances, the memory device may execute an instruction set to control the functional elements of the device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0090] At 905, the method may include establishing a delay of a signal on a signal line coupled to the input by setting the amplifier gain between the amplifier's node and the amplifier's input, the amplifier having an impedance between the input and the node. Operation of 905 may be performed according to examples as disclosed herein. In some examples, aspects of operation of 905 may be as described in references... Figure 8The described delay manager 825 is executed.

[0091] At 910, the method may include determining a delay in the signal on the signal line. The operation at 910 may be performed according to examples disclosed herein. In some instances, it may be performed by reference to... Figure 8 The described determinant component 830 performs the operation of 910.

[0092] At 915, the method may include adjusting the delay of the signal on the signal line by changing the gain of the amplifier. Operation of 915 may be performed according to examples disclosed herein. In some instances, aspects of operation of 915 may be as described in references... Figure 8 The described current manager 835 is executed.

[0093] In some instances, the device as described herein may perform one or more methods, such as method 900. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: establishing a delay of a signal on a signal line coupled to the input by setting the gain of the amplifier between a node of the amplifier and the input of the amplifier, the amplifier having an impedance between the input and the node; determining to change the delay of the signal on the signal line; and adjusting the delay of the signal on the signal line by changing the gain of the amplifier.

[0094] In some instances of the methods 900 and devices described herein, changing the gain of an amplifier may include operations, features, circuitry, logic, components, or instructions for adjusting the current supplied to the amplifier.

[0095] Some examples of the method 900 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: establishing a second delay of a second signal on the second signal line by setting a second gain of the second amplifier at a second node relative to the second input, in conjunction with establishing a delay of a signal on a second signal line coupled to a second input of the second amplifier, the second amplifier having a second impedance between the second input and the second node; and adjusting the second delay of the second signal on the second signal line by changing a second gain of the second amplifier, in conjunction with adjusting the delay of a signal on the signal line.

[0096] In some instances of the method 900 and apparatus described herein, changing the gain of an amplifier may include operations, features, circuitry, logic, components, or instructions for adjusting the current supplied to the amplifier, and changing the second gain of a second amplifier may include operations, features, circuitry, logic, components, or instructions for adjusting the second current supplied to the second amplifier.

[0097] In some instances of the method 900 and apparatus described herein, adjusting the current supplied to the amplifier and adjusting the second current supplied to the second amplifier may include operations, features, circuitry, logic, components, or instructions for adjusting the bias voltage of a third input to a transistor coupled to the amplifier and the second amplifier.

[0098] It should be noted that the methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0099] Describe a device. The device may include a signal line and circuitry configured to provide a load on the signal line. The circuitry may include an amplifier having an input coupled to the signal line, the amplifier having an impedance between the input and a node of the amplifier, the amplifier having a gain at the node relative to the input; and a sub-circuit coupled to the amplifier and configured to control the gain of the amplifier.

[0100] In some instances of the device, the impedance may include the intrinsic capacitance of the amplifier's input device. In some instances of the device, the input device may include a transistor.

[0101] In some instances of the device, the impedance may include a capacitor coupled between the nodes of the input and the amplifier.

[0102] In some instances of the device, the sub-circuit may include a transistor configured to supply current to an amplifier to control the amplifier's gain. In some instances of the device, the transistor may include a second input configured to receive a bias voltage to control the current supplied by the transistor to the amplifier.

[0103] In some instances of the device, the circuit may be configured to delay the signal on the amplifier's gain signal line.

[0104] Describe a device. The device may include a set of signal lines extending from a first end to a second end, the set of signal lines being configured to distribute signals of a multiphase clock; and circuitry coupled to the set of signal lines, the circuitry being configured to provide a load on the set of signal lines. The circuitry may include a set of amplifiers having a set of inputs coupled to the set of signal lines, the set of amplifiers having corresponding gains at nodes of the set of amplifiers relative to corresponding inputs of the set of inputs; and sub-circuitry coupled to the set of amplifiers, the sub-circuitry being configured to control the corresponding gains of the set of amplifiers.

[0105] In some instances, the device may include a set of buffers coupled to the set of signal lines between first and second terminals, the set of buffers being configured to buffer signals of a multiphase clock; the circuit coupled to the set of signal lines between the first terminal and the set of buffers; and a second circuit having a second set of inputs coupled to the set of signal lines between the set of buffers and the second terminal, the second circuit being coupled to a sub-circuit and configured to control the sub-circuit based on signals detected on the second set of inputs. In some instances of the device, the second circuit may be configured to control the bias current of the sub-circuit based on an amount of overlap of signal values ​​corresponding to different phases of the multiphase clock.

[0106] In some instances of the device, the sub-circuit may include a corresponding transistor coupled to the group amplifier, the corresponding transistor being configured to provide a corresponding current to the group amplifier to control a corresponding gain of the group amplifier. In some instances of the device, each of the group amplifiers may include a first transistor having a first gate coupled to a first input of the group input, and a second transistor having a second gate coupled to a second input of the group input, wherein the corresponding transistor associated with each of the group amplifiers may include a third transistor coupled in series with the first transistor and a fourth transistor coupled in series with the second transistor.

[0107] In some instances of the device, the circuit may include a set of differential stages, each differential stage containing a corresponding plurality of amplifiers of the group amplifiers. In some instances of the device, the sub-circuit may include a set of tail current sources coupled to the group of differential stages. In some instances of the device, the sub-circuit may be further configured to differentially control the current supplied to the corresponding plurality of amplifiers of the differential stages in the group of differential stages.

[0108] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, the signal may represent a bus of signals, which may have various bit widths.

[0109] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" refer to the relationship between components that support the flow of signals between them. Components are considered to be electronically connected (or electrically contacted, connected, or coupled) to each other if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacted, connected, or coupled) to each other can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0110] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently be transmitted between components via conductive paths, while in a closed-circuit relationship, signals can be transmitted between components via conductive paths. When a component, such as a controller, couples other components together, the components begin to allow signals to flow between the other components via conductive paths that were previously not permitted.

[0111] The term "isolation" refers to a relationship between components where signals are currently not allowed to flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between them using previously permitted conductive paths.

[0112] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0113] The open component or transistor discussed herein may represent a FET and includes a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can make the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0114] The description herein, illustrated with reference to the accompanying drawings, describes example configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described embodiments.

[0115] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a second reference numeral following the reference numeral with a strikethrough, distinguishing them from each other. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, but not to the second reference numeral.

[0116] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functionality can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described herein can be implemented in software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located in various locations, including distributed implementations such that portions of the functionality are implemented in different physical locations.

[0117] For example, the various illustrative blocks and modules described herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor; however, alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a combination of multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0118] As used herein, the word "or" in a list of items contained in the claims (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a set of closing conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0119] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any medium that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available medium accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used in this article, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0120] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: signal line; as well as A circuit configured to provide a load on the signal line, the circuit comprising: An amplifier having an input coupled to the signal line, the amplifier having an impedance between the input and a node of the amplifier, and the amplifier having a gain at the node relative to the input; as well as A sub-circuit, coupled to the amplifier and configured to control the gain of the amplifier. The circuit is configured to delay the signal on the signal line based on the gain of the amplifier.

2. The device of claim 1, wherein the impedance includes the intrinsic capacitance of the input device of the amplifier.

3. The device of claim 2, wherein the input device comprises a transistor.

4. The device of claim 1, wherein the impedance includes a capacitor coupled between the input and the node of the amplifier.

5. The device of claim 1, wherein the sub-circuit includes a transistor configured to provide current to the amplifier to control the gain of the amplifier.

6. The device of claim 5, wherein the transistor has a second input configured to receive a bias voltage to control the current supplied by the transistor to the amplifier.

7. An apparatus comprising: A set of signal lines extending from a first end to a second end, the set of signal lines being configured to distribute signals of a multiphase clock. as well as A circuit coupled to the group of signal lines, the circuit being configured to provide a load on the group of signal lines, the circuit comprising: A set of amplifiers having a set of inputs coupled to the set of signal lines, the set of amplifiers having corresponding gains at nodes of the set of amplifiers relative to the corresponding inputs of the set of inputs; and A sub-circuit, coupled to the group amplifier, is configured to control the corresponding gain of the group amplifier. The circuitry is configured to delay the signals on the corresponding signal lines in the group signal lines based on the corresponding gain of the group amplifier.

8. The device according to claim 7, further comprising: A set of buffers coupled to the set of signal lines between the first and second terminals, the set of buffers being configured to buffer the signal of the multiphase clock, the circuit being coupled to the set of signal lines between the first terminal and the set of buffers; as well as A second circuit having a second set of inputs coupled to the group signal lines between the group buffer and the second terminal, the second circuit being coupled to the sub-circuit and configured to control the sub-circuit based on signals detected on the second set of inputs.

9. The device of claim 8, wherein the second circuit is configured to control the bias current of the sub-circuit based on the serializer replica circuit output.

10. The device of claim 7, wherein the sub-circuit includes a corresponding transistor coupled to the group amplifier, the corresponding transistor being configured to provide a corresponding current to the group amplifier to control a corresponding gain of the group amplifier.

11. The device according to claim 10, wherein: Each of the group amplifiers includes a first transistor having a first gate coupled to a first input of the group input, and a second transistor having a second gate coupled to a second input of the group input, and the corresponding transistor of the sub-circuit coupled to each of the group amplifiers includes a third transistor coupled in series with the first transistor and a fourth transistor coupled in series with the second transistor.

12. The device of claim 7, wherein the circuitry comprises a set of differential levels, each differential level comprising a corresponding plurality of amplifiers of the set of amplifiers.

13. The device of claim 12, wherein the sub-circuit includes a set of tail current sources coupled to the group differential level.

14. The device of claim 12, wherein the sub-circuit is further configured to differentially control the current supplied to the respective plurality of amplifiers of the differential level in the group differential level.

15. A method comprising: A delay of the signal on the signal line coupled to the input is established by setting the gain of the amplifier between the amplifier's node and the amplifier's input, the amplifier having an impedance between the input and the node; Determine to change the delay of the signal on the signal line; as well as The delay of the signal on the signal line is adjusted by changing the gain of the amplifier.

16. The method of claim 15, wherein changing the gain of the amplifier comprises: Adjust the current supplied to the amplifier.

17. The method of claim 15, further comprising: By combining the delay of the signal on the second signal line coupled to the second input of the second amplifier, a second delay of the second signal on the second signal line is established by setting a second gain of the second amplifier at the second node relative to the second input, the second amplifier having a second impedance between the second input and the second node; as well as By adjusting the delay of the signal on the signal line, the second delay of the second signal on the second signal line is adjusted by changing the second gain of the second amplifier.

18. The method of claim 17, wherein changing the gain of the amplifier comprises: Adjust the current supplied to the amplifier; and Changing the second gain of the second amplifier includes: Adjust the second current supplied to the second amplifier.

19. The method of claim 18, wherein adjusting the current supplied to the amplifier and adjusting the second current supplied to the second amplifier includes adjusting the bias voltage of a third input of a transistor coupled to the amplifier and the second amplifier.

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