Semiconductor integrated device and method of manufacturing the same

Abstract

The present invention provides a semiconductor integrated device and a manufacturing method thereof, which are applied to the field of semiconductor technology. Specifically, in the manufacturing method, by adopting the shallow trench isolation method in the BCD device, the breakdown voltage of the BCD device, especially the high-voltage device, is improved. Moreover, the present invention provides a method for synchronously producing SGT isolation devices and BCD power IC devices on the same chip, thereby avoiding the problem of relatively large parasitic Rs and Rc between the two devices caused by separately forming the two devices step by step and then bonding and connecting them in the prior art, and at the same time improving the performance matching degree between the SGT device and the BCD device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor integrated device and a manufacturing method thereof. Background Art

[0002] Power integrated ICs are widely used in fields such as power management, motor drive, automotive electronics, and industrial control. BCD refers to a process technology that integrates high-voltage power devices such as Bipolar, CMOS, and DMOS, as well as various resistors, capacitors, and diodes on the same chip. It has the characteristics of low cost, easy packaging, easy design, and a simpler peripheral chip, and has rapidly developed into the mainstream technology in the field of power ICs. The Bipolar bipolar transistor in the BCD technology has high analog accuracy and is mainly used in analog circuits. CMOS has high integration and is mainly used in logic circuits. DMOS has high power (high voltage) characteristics and is commonly used as a switch.

[0003] In the prior art, BCD devices often integrate high-voltage devices and low-voltage devices. For example, the high-voltage devices can be LDMOS devices, high-voltage JFET devices, etc., and the low-voltage devices can be low-voltage MOS devices, etc. The discrete-gate or shield-gate MOSFET is an improved type of UMOS device, which has a faster switching speed and lower switching loss compared to UMOS. According to the structure of the poly, it can be divided into upper and lower (UD SGT) and left and right (LR SGT). Among them, the SGT device utilizes the charge balance principle to reduce the on-resistance by appropriately increasing the doping concentration of the epitaxial layer; uses the shield gate to reduce Cgd / Ciss and improve the Dv / dt capability.

[0004] Currently, the SGT discrete devices and the BCD devices of PowerIC (power IC) on the market are generally produced separately and then encapsulated together to form a module. Therefore, in high-end application fields, the module formed by the above method has the following problems: 1. The SGT discrete device and the BCD Power IC device are connected by bonding wire, which will result in relatively large parasitic Rs and Rc; 2. The SGT discrete device and the BCD PowerIC device are produced asynchronously, so the performance matching degree between them is not high. Summary of the Invention

[0005] The purpose of the present invention is to provide a manufacturing method of a semiconductor integrated device, so as to propose a new manufacturing method for integrating SGT devices and BCD devices on the same chip, and at the same time propose a method for improving the breakdown voltage of the drift region of high-voltage devices by using shallow trench isolation in the BCD device region.

[0006] In a first aspect, to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor integrated device. Specifically, the manufacturing method may at least include the following steps:

[0007] Provide a semiconductor substrate, the semiconductor substrate includes an SGT device region, a low-voltage device region, and a high-voltage device region arranged side by side in sequence. The low-voltage device region includes a PMOS region and an NMOS region, the high-voltage device region includes an NLDMOS region and a PLDMOS region. A plurality of gate trenches, breakdown voltage trenches, a first oxide layer covering the inner walls of the gate trenches and the breakdown voltage trenches, and source polysilicon filling at least the gate trenches and the breakdown voltage trenches are formed in the semiconductor substrate corresponding to the SGT device region;

[0008] Mask the semiconductor substrate corresponding to the SGT device region, and perform an etching process on the exposed semiconductor substrate corresponding to the low-voltage device region and the high-voltage device region to form a plurality of shallow trenches in the semiconductor substrate;

[0009] Mask the semiconductor substrate corresponding to the low-voltage device region and the high-voltage device region, and etch back the source polysilicon and the first oxide layer in the gate trenches in the exposed SGT device region so that the etched-back source polysilicon and the first oxide layer only cover the bottom of the gate trenches;

[0010] Form an isolation material layer on the semiconductor substrate so that the isolation material layer at least fills the shallow trenches, thereby forming a shallow trench isolation structure for isolating each device structure in the SGT device region, the low-voltage device region, and the high-voltage device region.

[0011] Further, before forming the gate trenches and the breakdown voltage trenches, the manufacturing method proposed by the present invention may further include the following steps:

[0012] Perform a first ion implantation process on the semiconductor substrate corresponding to the PMOS region, the NMOS region, the NLDMOS region, and the PLDMOS region to form at least three first deep wells in the low-voltage device region and the high-voltage device region;

[0013] Perform a second ion implantation process on the semiconductor substrate corresponding to the first deep wells to form a plurality of high-voltage wells of a second conductivity type in the high-voltage device region; and,

[0014] After forming the shallow trench isolation structure, the manufacturing method further includes: performing a third ion implantation process on the semiconductor substrate to form a plurality of low-voltage wells of a third conductivity type in the low-voltage device region.

[0015] Further, the first deep well may be a P-type well, the high-voltage well of the second conductivity type may be an N-type high-voltage well, and the low-voltage well of the third conductivity type may be an N-type low-voltage well.

[0016] Further, after forming the N-type high-voltage well and before forming the gate trench and the withstand voltage trench, the manufacturing method provided by the present invention may further include forming a photoresist layer with an ONO stack structure on the entire surface of the semiconductor substrate.

[0017] Further, the step of forming the shallow trench in the manufacturing method provided by the present invention may include forming a first patterned photoresist on the semiconductor substrate to shield the SGT device region and expose a partial region of the semiconductor substrate corresponding to the low-voltage device region and the high-voltage device region, and using the first patterned photoresist as a mask to etch the semiconductor substrate to form a plurality of the shallow trenches.

[0018] Further, the step of back-etching the source polysilicon and the first oxide layer in the gate trench in the exposed SGT device region may include: removing the first patterned photoresist, forming a second photoresist layer to shield the withstand voltage trench in the SGT device region, the semiconductor substrate corresponding to the low-voltage device region and the high-voltage device region, and using the second patterned photoresist layer as a mask to etch the source polysilicon and the first oxide layer in the exposed gate trench in the SGT device region.

[0019] Further, the back-etching process may be a dry etching process.

[0020] Further, the step of forming the trench isolation structure in the manufacturing method provided by the present invention may include:

[0021] Removing the second patterned photoresist layer, and forming an isolation material layer on the semiconductor substrate. The isolation material layer at least fills the shallow trenches, and at the same time also extends and covers the surface of the back-etched source polysilicon and the first oxide layer to at least fill the back-etched gate trench.

[0022] Further, the material of the isolation material layer may include silicon dioxide.

[0023] In a second aspect, based on the same inventive concept, the present invention further provides a semiconductor integrated device, which may be specifically prepared by using the manufacturing method of the semiconductor integrated device as described above.

[0024] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0025] In a manufacturing method of a semiconductor integrated device provided by the present invention, by adopting a shallow trench isolation method in a BCD device, the breakdown voltage of the BCD device, especially high-voltage devices, is improved. Moreover, the present invention provides a method for synchronously producing SGT isolation devices and BCD power IC devices on the same chip, thereby avoiding the problem of relatively large parasitic Rs and Rc between the two devices caused by separately forming the two devices step by step and then bonding them together in the prior art. At the same time, the performance matching degree of the SGT device and the BCD device is also improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. is a schematic flow chart of a manufacturing method of a semiconductor integrated device according to an embodiment of the present invention;

[0027] Figures 2a to 2d FIG. is a schematic structural diagram of a manufacturing method of a semiconductor integrated device according to an embodiment of the present invention during its preparation process.

[0028] Among them, the reference numerals are as follows:

[0029] 100 - semiconductor substrate; 110 - epitaxial layer;

[0030] A - SGT device area; B - high-voltage device area;

[0031] C - low-voltage device area; 101 - gate trench;

[0032] 102 - breakdown voltage trench; 103 - shallow trench;

[0033] DPW - P-type deep well; LVNW - low-voltage N well;

[0034] HVNW - high-voltage N well; 120 - hard mask layer;

[0035] 130 - first oxide layer; 140 - extremely polysilicon material;

[0036] 150 - first patterned photoresist; 160 - second patterned photoresist layer;

[0037] 170 - isolation material layer; 251 - trench isolation structure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] As described in the background art, high-voltage devices and low-voltage devices are often integrated in a BCD device. For example, the high-voltage device can be an LDMOS device, a high-voltage JFET device, etc., and the low-voltage device can be a low-voltage MOS device, etc. The discrete-gate or shield-gate MOSFET is an improved UMOS device, which has a faster switching speed and lower switching loss compared to UMOS. According to the structure of the poly, it can be divided into upper and lower (UD SGT) and left and right (LR SGT). Among them, the SGT device utilizes the charge balance principle to appropriately increase the doping concentration of the epitaxial layer to reduce the on-resistance; and uses the shield gate to reduce Cgd / Ciss and improve the Dv / dt capability.

[0039] Currently, the SGT discrete devices and the BCD devices of Power IC (Power Integrated Circuit) on the market are generally produced separately and then packaged together to form a module. Therefore, in high-end application fields, there are the following problems with the module formed in the above manner: 1. The SGT discrete device and the Power IC device of BCD are connected by bonding wires, which will result in relatively large parasitic Rs and Rc; 2. The SGT discrete device and the Power IC device of BCD are not produced synchronously, so the performance matching degree between them is not high.

[0040] Therefore, the present invention provides a manufacturing method of a semiconductor integrated device, aiming to propose a new manufacturing method for integrating the SGT device and the BCD device on the same chip, and at the same time propose a method for improving the breakdown voltage resistance of the drift region of the high-voltage device by adopting shallow trench isolation in the BCD device region.

[0041] Reference Figure 1 shown Figure 1 is a schematic flow chart of the manufacturing method of the semiconductor integrated device provided in the embodiment of the present invention; wherein, the manufacturing method of the semiconductor integrated device may include the following steps:

[0042] Step S100, providing a semiconductor substrate, the semiconductor substrate includes an SGT device region, a low-voltage device region, and a high-voltage device region arranged side by side in sequence, the low-voltage device region includes a PMOS region and an NMOS region, the high-voltage device region includes an NLDMOS region and a PLDMOS region, and a plurality of gate trenches, breakdown voltage trenches, a first oxide layer covering the inner walls of the gate trenches and the breakdown voltage trenches, and source polysilicon filling at least the gate trenches and the breakdown voltage trenches are formed in the semiconductor substrate corresponding to the SGT device region;

[0043] Step S200, masking the semiconductor substrate corresponding to the SGT device region, and performing an etching process on the exposed semiconductor substrate corresponding to the low-voltage device region and the high-voltage device region to form a plurality of shallow trenches in the semiconductor substrate;

[0044] Step S300: Shield the semiconductor substrate corresponding to the low-voltage device region and the high-voltage device region, and perform etch-back to expose the source polysilicon and the first oxide layer in the gate trenches in the exposed SGT device region, so that the etched-back source polysilicon and the first oxide layer only cover the bottom of the gate trenches.

[0045] Step S400: Form an isolation material layer on the semiconductor substrate, so that the isolation material layer at least fills the shallow trenches, thereby forming a shallow trench isolation structure for isolating each device structure in the SGT device region, the low-voltage device region, and the high-voltage device region.

[0046] That is, in a manufacturing method of a semiconductor integrated device provided by the present invention, by adopting the shallow trench isolation method in the BCD device, the breakdown voltage of the BCD device, especially the high-voltage device, is improved. Moreover, the present invention provides a method for synchronously producing SGT discrete devices and BCD power IC devices on the same chip, thereby avoiding the problem of relatively large parasitic Rs and Rc between the two caused by separately forming the two devices step by step and then bonding them in the prior art, and at the same time improving the performance matching degree between the SGT device and the BCD device.

[0047] The following further describes in detail the semiconductor integrated device and its manufacturing method proposed by the present invention with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention. Many specific details are set forth in the following description in order to provide a thorough understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0048] As shown in this application and the claims, unless the context clearly indicates an exception, words such as "a", "an", "one", and / or "the" are not specifically singular and may also include plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of the clearly identified steps and elements, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements. When detailing the embodiments of the present invention, for the convenience of explanation, the cross-sectional views showing the device structure will be enlarged locally out of proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0049] Figures 2a to 2d It is a schematic structural diagram in the preparation process of the manufacturing method of the semiconductor integrated device in an embodiment of the present invention.

[0050] In step S100, specifically referring to Figure 2a as shown, a semiconductor substrate 100 is provided. The semiconductor substrate includes an SGT device region A, a low-voltage device region C, and a high-voltage device region B arranged side by side in sequence. Among them, the low-voltage device region C may include one or more PMOS regions and NMOS regions, that is, the low-voltage device region C is a device region containing multiple CMOS transistors, and the operating voltage of the CMOS transistors in this device region can be 5V; the high-voltage device region B may include one or more NLDMOS regions and PLDMOS regions, that is, the high-voltage device region B is a device region containing multiple LDMOS transistors.

[0051] In this embodiment, first, a semiconductor substrate needs to be provided, such as Figure 2a the semiconductor substrate 100 shown. The semiconductor substrate 100 can be any suitable substrate known in the art. For example, it can be at least one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, and also includes multi-layer structures composed of these semiconductors, etc., or it can also be a double-sided polished wafer (DSP), or a ceramic substrate such as alumina, a quartz or glass substrate, etc. Exemplarily, the semiconductor substrate 100 in this embodiment is, for example, a silicon wafer.

[0052] After that, an N-type doped epitaxial layer (Nepi) 110 can be formed on the surface of the N-type silicon substrate 100 by combining an epitaxial process and a doping process. Further, after forming the N-type doped epitaxial layer (Nepi) 110, the semiconductor substrate 100 can be subjected to multiple ion implantation steps to form multiple first deep wells (P-type deep wells) and other wells for forming high-voltage devices in the N-type doped epitaxial layer (Nepi) 110. For example, N-type well HVNW. The specific formation steps can be referred to as follows:

[0053] Step S101, perform a first ion implantation process on the semiconductor substrate 100 corresponding to the PMOS region, NMOS region, NLDMOS region, and PLDMOS region to form at least three P-type deep wells DPW in the low-voltage device region C and the high-voltage device region B;

[0054] Step S102, perform a second ion implantation process on the semiconductor substrate 100 corresponding to the P-type deep well DPW to form multiple high-voltage N wells HVNW in the high-voltage device region B.

[0055] In this embodiment, as can be seen from the above steps S101 and S102, the MOS transistors in the high-voltage device region B are differentiated by being formed in different N-type wells. This is prior art and will not be described in detail in this invention.

[0056] Further, after forming the N-well HVNW in the above step S102, the present invention may first form a hard mask layer 120 with a structure that can be an ONO stack structure on the surface of the semiconductor substrate 100. Among them, the ONO stack structure is a stacked structure of an oxide layer - a nitride layer and an oxide layer. Then, using this ONO stack structure 120 as a mask, multiple trenches, namely gate trenches 101 and breakdown voltage trenches 102, are formed in the semiconductor substrate 100 corresponding to the SGT device region by means of an etching process. Then, a first oxide layer 130 with a certain thickness, for example, a silicon dioxide layer, is formed on the inner walls of the gate trenches 101 and the breakdown voltage trenches 102. After that, the gate trenches 101 and the breakdown voltage trenches 102 formed with this first oxide layer 130 are filled with source polysilicon material 140.

[0057] In step S200, specifically referring to Figure 2b as shown, the semiconductor substrate 100 corresponding to the SGT device region A is masked, and an etching process is performed on the exposed semiconductor substrate 100 corresponding to the low-voltage device region C and the high-voltage device region B to form multiple shallow trenches 103 in the semiconductor substrate 100;

[0058] In this embodiment, after the above step S100, a first patterned photoresist 150 that masks the SGT device region A and exposes partial regions of the semiconductor substrate 100 corresponding to the low-voltage device region C and the high-voltage device region B can be first formed. Using this first patterned photoresist 150 as a mask, the semiconductor substrate 100 is etched to form multiple shallow trenches 103.

[0059] In step S300, specifically referring to Figure 2c as shown, the semiconductor substrate 100 corresponding to the low-voltage device region C and the high-voltage device region B is masked, and the source polysilicon 140 and the first oxide layer 130 in the gate trenches 101 in the exposed SGT device region A are etched back so that the etched-back source polysilicon 140 and the first oxide layer 130 only cover the bottom of the gate trenches 101.

[0060] In this embodiment, after performing the step S300, it is necessary to first remove the photoresist 150 of the first patterning, and form a second-patterned photoresist layer 160 on the semiconductor substrate 100 to shield the semiconductor substrate 100 corresponding to the breakdown voltage trench 102, the low-voltage device region C, and the high-voltage device region B in the SGT device region A. Using this second-patterned photoresist layer 160 as a mask, etch the source polysilicon 140 and the first oxide layer 130 in the gate trench 101 exposed in the SGT device region A, and only remove a part of the thickness of the first oxide layer 130 and the source polysilicon 140 in the gate trench 101, so that the etched source polysilicon 140 and the first oxide layer 130 only cover the bottom of the gate trench 101. Among them, the back-etching process can be a dry etching process.

[0061] As can be seen from the above steps, in the embodiment of the present invention, the SGT isolation device and the BCD power IC device can be synchronously produced on the same chip. Therefore, the manufacturing method proposed by the present invention can avoid the problem of relatively large parasitic Rs and Rc between the two caused by separately forming the two devices step by step and then bonding and connecting them in the prior art, and at the same time improve the performance matching degree of the SGT device and the BCD device.

[0062] It should be noted that in the embodiment of the present invention, no matter how the identifiers of the same film layer change, they are all identified by the same identifier. The purpose of this approach is to clearly identify each film layer and effectively distinguish it from other film layers. However, in other embodiments, it can also use different states of the same identifier, for example, 120, 120', 120", etc. to identify the states of the same film layer after different semiconductor process flows. The present invention does not make specific limitations on this.

[0063] In step S400, specifically refer to Figure 2c and Figure 2d As shown, form an isolation material layer 170 on the semiconductor substrate 100, so that the isolation material layer 170 at least fills the shallow trench 103, and further form a shallow trench isolation structure 251 for isolating each device structure in the SGT device region A, the low-voltage device region C, and the high-voltage device region B.

[0064] In this embodiment, the photoresist layer 160 of the second patterning is removed, and an isolation material layer 170 is formed on the semiconductor substrate 100. The isolation material layer 170 at least fills the shallow trench 103, and at the same time also extends to cover the surfaces of the etched-back source polysilicon 140 and the first oxide layer 130 to at least fill the etched-back gate trench 101. The material of the isolation material layer 170 may include silicon dioxide. Thereafter, a third ion implantation process may be performed on the semiconductor substrate 100 to form a plurality of low-voltage N wells LVNW in the low-voltage device region C.

[0065] In addition, based on the manufacturing method of the semiconductor integrated device described above, the present invention also provides a semiconductor integrated device. The specific formation process can refer to the above description, and the present invention will not be described in detail here.

[0066] In summary, in the manufacturing method of a semiconductor integrated device provided by the present invention, by adopting the shallow trench isolation method in the BCD device, the breakdown voltage of the BCD device, especially the high-voltage device, is improved. Moreover, the present invention provides a method for synchronously producing SGT isolation devices and BCD power IC devices on the same chip, thereby avoiding the problem of large parasitic Rs and Rc between the two caused by separately forming the two devices step by step and then bonding them in the prior art, and at the same time improving the performance matching degree of the SGT device and the BCD device.

[0067] It should be noted that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still belong to the scope of protection of the technical solution of the present invention.

[0068] It should also be understood that unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0069] It should also be recognized that the terminology described herein is only used to describe specific embodiments and is not intended to limit the scope of the present invention. It must be noted that the singular forms "a" and "an" used herein and in the appended claims include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "a device" means reference to one or more steps or devices and may include sub-steps and sub-devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly dictates otherwise. In addition, the implementation of the methods and / or devices in the embodiments of the present invention may include performing the selected tasks manually, automatically, or in combination.

Claims

1. A manufacturing method of a semiconductor integrated device, characterized in that, At least include the following steps: Provide a semiconductor substrate, the semiconductor substrate includes an SGT device region, a high-voltage device region, and a low-voltage device region arranged side by side in sequence. The low-voltage device region includes a PMOS region and an NMOS region. The high-voltage device region includes an NLDMOS region and a PLDMOS region. A plurality of gate trenches, breakdown trenches, a first oxide layer covering the inner walls of the gate trenches and the breakdown trenches, and source polysilicon filling at least the gate trenches and the breakdown trenches are formed in the semiconductor substrate corresponding to the SGT device region; Mask the semiconductor substrate corresponding to the SGT device region, and perform an etching process on the exposed semiconductor substrate corresponding to the low-voltage device region and the high-voltage device region to form a plurality of shallow trenches in the semiconductor substrate; Mask the semiconductor substrate corresponding to the low-voltage device region and the high-voltage device region, and etch back the source polysilicon and the first oxide layer in the gate trenches in the exposed SGT device region, so that the etched-back source polysilicon and the first oxide layer only cover the bottom of the gate trenches; Form an isolation material layer on the semiconductor substrate, so that the isolation material layer at least fills the shallow trenches, thereby forming a shallow trench isolation structure for isolating each device structure in the SGT device region, the low-voltage device region, and the high-voltage device region; 2. The manufacturing method of the semiconductor integrated device according to claim 1, characterized in that, Before forming the gate trenches and the breakdown trenches, the manufacturing method further includes: Perform a first ion implantation process on the semiconductor substrate corresponding to the PMOS region, the NMOS region, the NLDMOS region, and the PLDMOS region to form at least three first deep wells in the low-voltage device region and the high-voltage device region; Perform a second ion implantation process on the semiconductor substrate corresponding to the first deep wells to form a plurality of high-voltage wells of a second conductivity type in the high-voltage device region; and, After forming the shallow trench isolation structure, the manufacturing method further includes: performing a third ion implantation process on the semiconductor substrate to form a plurality of low-voltage wells of a third conductivity type in the low-voltage device region; 3. The manufacturing method of the semiconductor integrated device according to claim 2, characterized in that, The first deep well is a P-type well, the high-voltage well of the second conductivity type is an N-type high-voltage well, and the low-voltage well of the third conductivity type is an N-type low-voltage well; 4. The manufacturing method of a semiconductor integrated device according to claim 3, characterized in that, After forming the N-type high-voltage well and before forming the gate trenches and the breakdown trenches, the method further includes forming a photoresist layer with an ONO stacked structure on the entire surface of the semiconductor substrate; 5. The manufacturing method of the semiconductor integrated device according to claim 1, characterized in that, The step of forming the shallow trenches includes forming a first patterned photoresist on the semiconductor substrate that masks the SGT device region and exposes partial regions of the semiconductor substrate corresponding to the low-voltage device region and the high-voltage device region, and etching the semiconductor substrate with the first patterned photoresist as a mask to form a plurality of the shallow trenches.

6. The manufacturing method of the semiconductor integrated device according to claim 5, characterized in that, The step of back-etching the source polysilicon and the first oxide layer in the gate trench in the exposed SGT device region includes: removing the first patterned photoresist, forming a second patterned photoresist layer that masks the semiconductor substrate corresponding to the breakdown voltage trench, the low-voltage device region, and the high-voltage device region in the SGT device region, and using the second patterned photoresist layer as a mask to etch the source polysilicon and the first oxide layer in the exposed gate trench in the SGT device region.

7. The manufacturing method of the semiconductor integrated device according to claim 6, characterized in that, The back-etching process is a dry etching process.

8. The manufacturing method of the semiconductor integrated device according to claim 6, wherein, The step of forming the trench isolation structure includes: Removing the second patterned photoresist layer, and forming an isolation material layer on the semiconductor substrate, the isolation material layer at least fills the shallow trench, and at the same time also extends and covers the surface of the source polysilicon and the first oxide layer after back-etching to at least fill the gate trench after back-etching.

9. The method for manufacturing a semiconductor integrated device according to claim 1, wherein, The material of the isolation material layer includes silicon dioxide.

10. A semiconductor integrated device, characterized in that, Prepared by using the manufacturing method of the semiconductor integrated device according to any one of claims 1 to 9.

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