A multi-level cache management method, device and equipment and readable storage medium

Abstract

The application discloses a multi-level cache management method, device and equipment and a readable storage medium. The method comprises the following steps: after the I / O request data of a bottom cache layer in a multi-level cache is hit each time, the probability value of a corresponding upper cache layer is dynamically updated by using the hit information; when a target I / O request data in the upper cache layer needs to be evicted, a random number is generated; if the random number is smaller than the probability value, the LRU algorithm is used to select the target I / O request data; if the random number is greater than or equal to the probability value, the LFU algorithm is used to select the target I / O request data; and the target I / O request data is evicted. The application can flexibly match different access modes to adaptively reasonably schedule and replace the current I / O request data in the complex scene. That is, the application can dynamically combine the bottom cache layer and the upper cache layer to perform management, thereby realizing mutual cooperation of the multi-level cache layers and finally effectively improving the cache hit rate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer storage, in particular to a multi-level cache management method and device, equipment and a readable storage medium. BACKGROUND

[0002] With the continuous expansion of the scale of modern storage systems, middleware layers are increasingly used to cache computing data for possible future re-access. Caching plays a very important role in the entire system. In real-time systems, data passes through multiple cache layers before reaching the application. In fact, such a multi-level cache consisting of different cache middleware layers is very common in modern computer systems, for example, client-side cache and server-side cache can be considered to constitute a simple two-level or multi-level cache in a web application.

[0003] Generally, managing a multi-level cache is more difficult than a single-level cache, because the high-level cache close to the application side usually absorbs most requests, causing the access characteristics of the remaining requests in the bottom cache layer to change; the optimization goal in a multi-level cache is not only a certain cache layer, but also the entire multi-level cache system. Therefore, in a multi-level cache, how to ensure the mutual coordination between layers is particularly important. However, at present, the multi-level cache management cannot effectively guarantee the mutual coordination between layers.

[0004] To sum up, how to effectively solve the problems of multi-level cache management and multi-layer mutual coordination is a technical problem that the technical personnel in the field urgently need to solve. SUMMARY

[0005] The purpose of the present application is to provide a multi-level cache management method, device, equipment and readable storage medium to realize multi-level cache management and multi-layer mutual coordination, and improve the overall hit rate of the multi-level cache system.

[0006] To solve the above technical problems, the present application provides the following technical solutions:

[0007] A multi-level cache management method, comprising:

[0008] After each I / O request data hitting a bottom cache layer in a multi-level cache, the probability value of the corresponding upper cache layer is dynamically updated using the hit information;

[0009] When a target I / O request data in the upper cache layer needs to be evicted, a random number is generated;

[0010] If the random number is less than the probability value, the LRU algorithm is used to select the target I / O request data;

[0011] if the random number is greater than or equal to the probability value, selecting the target I / O request data by using an LFU algorithm;

[0012] evicting the target I / O request data.

[0013] Preferably, the step of dynamically updating the probability value of the corresponding upper cache layer by using the hit information comprises:

[0014] reading historical access information corresponding to the I / O request data by using the hit information;

[0015] determining an evicting algorithm to be used when the I / O request data is evicted by the upper cache layer by using the historical access information;

[0016] if the evicting algorithm is the LRU algorithm, reducing the probability value by using a formula

[0017] if the evicting algorithm is the LFU algorithm, increasing the probability value by using

[0018] wherein P is the probability value, P' is a new probability value, λ and d respectively correspond to a learning rate and a discount rate of the upper cache layer relative to the probability value, T is a logical time of the I / O request data hitting the bottom cache layer, and evict_time is a logical time of the I / O request data being evicted by the upper cache.

[0019] Preferably, the step of dynamically updating the probability value of the corresponding upper cache layer by using the hit information comprises:

[0020] if the upper cache layer is a top cache layer, dynamically updating the probability value corresponding to the top cache layer by using the hit information;

[0021] if the upper cache layer is an intermediate cache layer, dynamically updating the probability value corresponding to the top cache layer by using the hit information.

[0022] Preferably, the step of evicting the target I / O request data comprises:

[0023] evicting the target I / O request data to a region corresponding to the upper cache layer in the bottom cache layer; wherein different regions are set in the bottom cache layer corresponding to different upper cache layers.

[0024] Preferably, the step of caching a new I / O request data comprises:

[0025] storing the new I / O request data in an intermediate cache layer in the multi-level cache;

[0026] ​​acquiring an access frequency of the new I / O request data within a specified time length;

[0027] migrating the new I / O request data to a top-level cache layer by using the access frequency.

[0028] Preferably, migrating the new I / O request data to a top-level cache layer by using the access frequency comprises:

[0029] determining whether the access frequency is greater than a dynamically updated frequency threshold;

[0030] If yes, migrating the new I / O request data to the top-level cache layer.

[0031] Preferably, dynamically updating the frequency threshold comprises:

[0032] respectively establishing a first-in-first-out queue for each of the upper-level cache layers; wherein the number of records that the first-in-first-out queue can accommodate corresponds to the maximum I / O request data that the corresponding record cache layer can cache;

[0033] recording the access frequency of the I / O request data that is evicted in each of the first-in-first-out queues;

[0034] recalculating the average value of all access frequencies in the corresponding first-in-first-out queue each time an I / O request data is evicted, and comparing the average value with the size of the frequency threshold;

[0035] adjusting the frequency threshold according to the comparison result.

[0036] A multi-level cache management device comprises:

[0037] a probability value updating module configured to dynamically update the probability value of a corresponding upper-level cache layer by using hit information each time an I / O request data in a bottom-level cache layer of the multi-level cache is hit;

[0038] a random number generating module configured to generate a random number when a target I / O request data in the upper-level cache layer needs to be evicted;

[0039] an eviction confirmation module configured to select the target I / O request data by using an LRU algorithm if the random number is less than the probability value, and select the target I / O request data by using an LFU algorithm if the random number is greater than or equal to the probability value;

[0040] an eviction module configured to evict the target I / O request data.

[0041] An electronic device comprises:

[0042] a memory configured to store a computer program;

[0043] A processor for implementing the steps of the multi-level cache management method when executing the computer program.

[0044] A readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the steps of the multi-level cache management method.

[0045] By applying the method provided in the embodiments of the present application, the probability value of the corresponding upper cache layer is dynamically updated by using the hit information after the I / O request data of the bottom cache layer in the multi-level cache is hit each time. When a target I / O request data in the upper cache layer needs to be evicted, a random number is generated. If the random number is less than the probability value, the target I / O request data is selected by using the LRU algorithm. If the random number is greater than or equal to the probability value, the target I / O request data is selected by using the LFU algorithm. The target I / O request data is evicted.

[0046] In the present application, the probability value of the corresponding upper cache layer is dynamically updated by using the hit information after the I / O request data of the top cache is hit. The probability value determines which eviction algorithm is used to evict the data of the generated cache layer. Specifically, when the upper cache layer needs to evict a target I / O request data in the cache thereof, a random number is first generated. If the random number is less than the dynamically updated probability value, the target I / O request data is directly selected by using the LRU algorithm. If the random number is not less than the dynamically updated probability value, the target I / O request data is selected by using the LFU algorithm. After the target I / O request data is selected, it is evicted. As can be seen, in the present application, for the upper cache layer to evict the target I / O request data, the LFU algorithm or the LRU algorithm is not fixedly used, but the LFU algorithm or the LRU algorithm is dynamically selected by combining a random number and the dynamically updated probability value based on the hit of the bottom cache layer. In the face of I / O requests in complex scenarios, different access modes can be flexibly matched, so that the current I / O request data can be adaptively and reasonably scheduled and replaced. That is, the bottom cache layer and the upper cache layer can be dynamically combined for management in the present application, so that the multi-level cache layers are cooperated with each other, and the cache hit rate is finally effectively improved.

[0047] Correspondingly, the embodiments of the present application also provide a multi-level cache management device, equipment and readable storage medium corresponding to the above multi-level cache management method, which have the above technical effects, and will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0048] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a flowchart illustrating the implementation of a multi-level cache management method in an embodiment of this application.

[0050] Figure 2 This is a schematic diagram illustrating the implementation of a multi-level cache management method in an embodiment of this application;

[0051] Figure 3 This is a flowchart illustrating a specific implementation of a multi-level cache management method in this application.

[0052] Figure 4 This is a schematic diagram of the structure of a multi-level cache management device in an embodiment of this application;

[0053] Figure 5 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application;

[0054] Figure 6 This is a schematic diagram of the specific structure of an electronic device in an embodiment of this application. Detailed Implementation

[0055] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0056] Please refer to Figure 1 , Figure 1 This is a flowchart of a multi-level cache management method according to an embodiment of this application. The method includes the following steps:

[0057] S101. After each hit of I / O request data in the lower layer of the multi-level cache, the probability value of the corresponding upper layer cache is dynamically updated using the hit information.

[0058] In this context, the upper cache layer refers to the non-lower cache layer in a multi-level cache. For example, in a three-level cache, the upper cache layer corresponds to the top-level cache layer and the intermediate cache layers.

[0059] In this application, a probability value can be set for each upper cache layer in a multi-level cache, that is, a probability value P corresponds to each non-lower cache layer. For example, for a multi-level cache, a probability value P1 can be set for the top cache layer and a probability value P2 can be set for the intermediate cache layers.

[0060] When a low-level cache in a multi-level cache is hit, the probability value of the corresponding high-level cache is dynamically updated using the hit information. The hit information may include which high-level cache corresponds to the currently hit I / O request data, and the historical access information of that I / O request data. Each region of the low-level cache is managed separately according to the allocation characteristics of the high-level cache, and each cache queue uses the LRU algorithm for eviction.

[0061] The I / O request data can be the data requested in the I / O request, such as the detailed logical address and access size. Of course, the I / O request data can also be other data that can quickly respond to the I / O request, such as specific data content such as images, videos, or text.

[0062] In one specific embodiment of this application, dynamically updating the probability value of the corresponding upper-level cache layer using hit information includes:

[0063] Step 1: Using the hit information, read the historical access information corresponding to the I / O request data;

[0064] Step 2: Use historical access information to determine the corresponding eviction algorithm when I / O request data is evicted by the upper cache layer;

[0065] Step 3: If the eviction algorithm is the LRU algorithm, then use the formula... Reduce the probability value;

[0066] Step 4: If the expulsion algorithm is the LFU algorithm, then utilize... Increase the probability value;

[0067] Where P is the probability value, P' is the new probability value, λ and d correspond to the learning rate and discount rate of the upper cache layer relative to the probability value, respectively, T is the logical time when the I / O request data is hit in the lower cache layer, and evict_time is the logical time when the I / O request data is evicted by the upper cache.

[0068] For ease of description, the above four steps will be explained in combination below.

[0069] It's important to note that in this embodiment, the logical time is not a few seconds in the general sense, but rather determined by the number of I / O requests. For example, if the cache currently receives 6 I / O requests, then the logical time is 6.

[0070] Whenever a new I / O request causes a cache hit at the lowest level, the probability value of the corresponding upper-level cache needs to be updated. Specifically, this involves updating the probability value of the cache layer corresponding to the evicted cache in the historical access information of the I / O request. If one of the access characteristics in the historical access information of the corresponding hit I / O request regarding the I / O request used at the time of evicting is the most recent access time, i.e., the eviction algorithm is LRU, then the probability value is decreased, as shown in the formula: Where λ and d correspond to the learning rate and discount rate of each cache layer relative to the probability value, respectively, T represents the hit time of the current I / O request, and evict_time represents the specific time when the current I / O request is evicted by the upper cache layer.

[0071] Furthermore, to ensure that the probability value falls within the range of [0,1], the above value can be normalized using the following formula: It should be noted that P in this formula corresponds to the adjusted probability value.

[0072] If one of the access characteristics of the I / O request used at the time of eviction is access frequency in the historical access information recorded for the corresponding I / O request, i.e., the eviction algorithm is LFU algorithm, then the probability value is increased, as shown in the formula: Furthermore, to ensure that the probability value falls within the range of [0,1], the above value needs to be normalized. The specific formula is as follows: It should be noted that P in this formula corresponds to the adjusted probability value.

[0073] In one specific embodiment of this application, dynamically updating the probability value of the corresponding upper-level cache layer using hit information includes:

[0074] Case 1: If the upper cache layer is the top cache layer, then the hit information is dynamically updated to reflect the probability value of the top cache layer.

[0075] Scenario 2: If the upper cache layer is an intermediate cache layer, then the hit information will be dynamically updated to reflect the probability value of the top cache layer.

[0076] Please refer to Figure 2 , Figure 2 This is a schematic diagram illustrating the implementation of a multi-level cache management method in an embodiment of this application.

[0077] If the upper cache layer is specifically the top cache layer, then the P1 value of the top cache layer is dynamically updated; if the upper cache layer is specifically an intermediate cache layer, then the P2 value of the intermediate cache layer is dynamically updated. That is, the hit information may differ for different upper cache layers, such as the eviction algorithm used by different upper cache layers when eviction occurs.

[0078] In addition to the bottom cache layer, each of the upper cache layers maintains a probability value P∈[0,1]. The main function of this value is to determine, based on the magnitude of the P value, whether to replace an I / O request according to one of the access characteristics of the I / O request when the cache needs to remove an I / O request. The access characteristics of the I / O request mainly include the most recent access time and access frequency. Among them, according to different eviction algorithms, I / O requests with earlier access time or lower access frequency will be preferentially selected to be evicted from the cache.

[0079] S102. When it is necessary to evict a target I / O request data in the upper cache layer, generate a random number.

[0080] Specifically, when the number of existing I / O requests in the cache reaches the cache capacity, and a new I / O request data enters the upper cache layer, it is determined that a target I / O request data needs to be evicted from the upper cache layer. This target I / O request data is the I / O request data that needs to be evicted from the upper cache layer.

[0081] Specifically, a random number R can be generated within the range [0,1].

[0082] S103. If the random number is less than the probability value, the target I / O request data is selected using the LRU algorithm.

[0083] If R∈[0,P), then the I / O request with the earliest access time is selected and evicted from the cache. That is, the LRU algorithm is used to select the target I / O request data.

[0084] S104. If the random number is greater than or equal to the probability value, the target I / O request data is selected using the LFU algorithm.

[0085] If R∈[P,1], then the I / O request with the lowest access frequency is evicted from the cache. That is, the LFU algorithm is used to select the target I / O request data.

[0086] S105, Eject target I / O request data.

[0087] Once the target I / O request data is determined, it can be evicted from the current upper-level cache layer.

[0088] Specifically, for ease of statistics, during eviction, the target I / O request data can be directly evicted to the underlying cache layer.

[0089] In one specific embodiment of this application, evicting target I / O request data includes: evicting the target I / O request data to a region in the lower cache layer that corresponds to the upper cache layer; wherein, different regions are set in the lower cache layer for different upper cache layers.

[0090] Specifically, since the lowest-level cache has a large cache capacity, the cache space of the lower-level cache can be allocated as the eviction cache of the upper-level cache according to the capacity and number of upper-level cache layers. The role of the eviction cache is to place the I / O requests that are evicted from the upper-level cache into the corresponding area of ​​the lower-level cache, and record the specific time of eviction, the corresponding cache layer, and one of the access characteristics of the I / O request used when eviction, that is, to indicate which specific eviction algorithm was used when eviction occurred.

[0091] The underlying cache layer can be virtually partitioned, corresponding to different cache layers. Different regions receive I / O request data evicted from different upper cache layers. Within the same upper cache layer, the underlying cache region can be further subdivided into LRU and LFU regions, thus determining the specific storage location based on different eviction algorithms. Therefore, when I / O request data in the underlying cache layer is hit, the hit information can specifically indicate which region the I / O request data belongs to, thus clearly identifying the corresponding upper cache layer and eviction algorithm.

[0092] For example, if the hit I / O request data is in the LRU region of the top-level cache layer in the bottom-level cache layer, then based on its hit information, it can be determined that the upper-level cache layer corresponding to the I / O request data is the top-level cache layer, and the eviction algorithm when it is evicted is the LRU algorithm.

[0093] Applying the method provided in the embodiments of this application, after each hit of I / O request data in the lower layer of the multi-level cache, the probability value of the corresponding upper layer cache is dynamically updated using the hit information; when a target I / O request data in the upper layer cache needs to be evicted, a random number is generated; if the random number is less than the probability value, the target I / O request data is selected using the LRU algorithm; if the random number is greater than or equal to the probability value, the target I / O request data is selected using the LFU algorithm; and the target I / O request data is evicted.

[0094] In this application, when I / O request data in the top-level cache is hit, the probability value of the corresponding upper-level cache layer is dynamically updated using the hit information. This probability value determines the specific eviction algorithm used to generate the cache data. Specifically, when the upper-level cache layer needs to evict a target I / O request data, a random number is first generated. If the random number is less than the dynamically updated probability value, the target I / O request data is directly selected using the LRU algorithm; if the random number is not less than the dynamically updated probability value, the target I / O request data is selected using the LFU algorithm. After the target I / O request data is selected, it is evicted. Therefore, in this application, the upper-level cache layer does not fixedly use either the LFU or LRU algorithm to evict target I / O request data. Instead, it dynamically selects between the LFU and LRU algorithms by combining a random number and the dynamically updated probability value based on the hit situation of the lower-level cache layer. This allows for more flexible matching of different access patterns in complex I / O request scenarios, thus adaptively scheduling and replacing the current I / O request data. In other words, this application can dynamically combine the underlying cache layer with the previous cache layer for management, thereby achieving mutual collaboration among multiple cache layers and ultimately effectively improving the cache hit rate.

[0095] It should be noted that, based on the above embodiments, the embodiments of this application also provide corresponding improvement schemes. In the preferred / improved embodiments, the same or corresponding steps as in the above embodiments can be referred to each other, and the corresponding beneficial effects can also be referred to each other; however, these will not be elaborated upon in the preferred / improved embodiments herein.

[0096] In one specific embodiment of this application, caching new I / O request data includes:

[0097] Step 1: Store the new I / O request data in the intermediate cache layer of the multi-level cache;

[0098] Step 2: Obtain the access frequency of new I / O request data within a specified time period;

[0099] Step 3: Utilize access frequency to migrate new I / O request data to the top-level cache layer.

[0100] For ease of description, the above three steps will be combined below.

[0101] like Figure 2As shown, when new I / O request data arrives, it is directly stored in the intermediate cache of the multi-level cache. Then, after a period of time, based on the access behavior of the I / O request data in the intermediate cache layer, a decision is made on whether to promote it to the top-level cache layer. Other cache layers, except the bottom cache layer, are replaced based on the performance of I / O requests in different access characteristics, and historical access information of I / O requests is retained, taking advantage of the capacity of the bottom cache. The access behavior of I / O request data mainly refers to the frequency of access to the intermediate cache layer within a certain period. The access characteristics of I / O request data are mainly access locality and frequency, with locality reflected by the time of the most recent access to the I / O request data. The historical access information of I / O request data mainly records the layer location and time when the I / O request was evicted.

[0102] In one specific embodiment of this application, step three above utilizes access frequency to migrate new I / O request data to the corresponding cache layer, including:

[0103] Step 1: Determine if the access frequency is greater than the dynamic update frequency threshold;

[0104] Step 2: If so, migrate the new I / O request data to the top-level cache layer;

[0105] Step 3: If not, the new I / O request data will continue to be kept in the intermediate cache layer.

[0106] If the access frequency is greater than the frequency threshold, it indicates that the new I / O request data is high-frequency access data. In this case, it can be migrated to the top-level cache layer to improve the hit rate. If the access frequency is not greater than the frequency threshold, it indicates that the new I / O request data is not high-frequency access data. In this case, the new I / O request data should be retained.

[0107] For example, each new I / O request records its access frequency in the intermediate cache layer. Each time the same new I / O request hits the intermediate cache layer, the access frequency increases. Each time the access frequency increases, it is compared to a set frequency threshold. If the current access frequency exceeds the set threshold, the new I / O request is promoted to a higher-level cache, thus leveraging the performance advantages of the upper-level cache. If the access frequency of the I / O request never reaches the threshold, it is eventually evicted to a lower-level cache layer, such as the bottom-level cache layer.

[0108] In one specific embodiment of this application, dynamically updating the frequency threshold includes:

[0109] Step 1: Establish a first-in-first-out (FIFO) queue for each upper-level cache layer; the number of records that the FIFO queue can hold corresponds to the maximum I / O request data that the corresponding cache layer can cache.

[0110] Step 2: In each first-in-first-out queue, record the access frequency corresponding to the evicted I / O request data;

[0111] Step 3: Each time an I / O request is evicted, recalculate the average access frequency of all accesses in the corresponding first-in-first-out queue and compare it with the frequency threshold.

[0112] Step 4: Adjust the frequency threshold based on the comparison results.

[0113] For ease of description, the above four steps will be explained in combination below.

[0114] A first-in-first-out (FIFO) queue is established for each cache layer in the upper cache layer. Whenever the corresponding cache layer evicts an I / O request, the access frequency of that I / O request in that layer is placed into the corresponding FIFO queue. The number of records that the queue can hold is the maximum number of I / O requests that the corresponding cache layer can cache.

[0115] Each time a cache replacement requires evicting an I / O request, the average access frequency of all accesses in the queue can be recalculated and compared to a frequency threshold. Taking a three-tier caching system as an example, for the middle tier cache, if the average size of the corresponding queue... With frequency threshold θ f Relationship satisfaction This means that the upper caching layer is not leveraging the performance advantages of the upper layer, causing most I / O requests to be directly evicted from the cache at the intermediate layer. In this case, θ should be reduced. f The size; the corresponding upper-level cache if the average size of the corresponding queue. With frequency threshold θ f Relationship satisfaction This means that the intermediate caching layer is not effectively filtering requests for the upper-level cache. Most I / O requests are quickly elevated to the upper-level cache at the intermediate layer, but this doesn't result in more cache hits at the upper level, leading to cache pollution. In this case, θ should be increased. f Size.

[0116] Furthermore, to ensure that the frequency threshold variation remains stable within a suitable access level, whenever θ f When the value is increased or decreased to a certain level, it will stop changing, and the step size for each increase or decrease is 1, thus achieving a smooth change in the frequency threshold.

[0117] To help those skilled in the art better understand the multi-level cache management method provided in the embodiments of this application, the following detailed explanation of the multi-level cache management method is given in conjunction with specific application scenarios.

[0118] For details, please refer to Figure 3 When a new I / O request arrives, it may access any of the following cache layers: top-level cache, intermediate cache, or bottom-level cache. If the top-level cache is accessed, it can be processed normally. If the bottom-level cache is accessed, the corresponding I / O request data is promoted to the corresponding cache layer, and the probability value of the corresponding upper-level cache layer is updated. If the intermediate cache is accessed, the access frequency is compared to determine whether the I / O request data should be promoted to a higher cache layer or retained. Then, the frequency threshold is updated, and the access process ends.

[0119] Therefore, it can be seen that the multi-level cache management method provided in the embodiments of this application can coordinate and manage multiple cache layers to cope with more complex I / O scenarios.

[0120] Corresponding to the above method embodiments, this application also provides a multi-level cache management device. The multi-level cache management device described below can be referred to in correspondence with the multi-level cache management method described above.

[0121] See Figure 4 As shown, the device includes the following modules:

[0122] The probability value update module 101 is used to dynamically update the probability value of the corresponding upper cache layer after each hit of I / O request data of the lower cache layer in the multi-level cache.

[0123] The random number generation module 102 is used to generate random numbers when it is necessary to evict a target I / O request data in the upper cache layer;

[0124] The eviction confirmation module 103 is used to select the target I / O request data using the LRU algorithm if the random number is less than the probability value, and to select the target I / O request data using the LFU algorithm if the random number is greater than or equal to the probability value.

[0125] Eject module 104 is used to eject target I / O request data.

[0126] Using the apparatus provided in the embodiments of this application, after each hit of I / O request data in the lower cache layer of a multi-level cache, the probability value of the corresponding upper cache layer is dynamically updated using the hit information; when a target I / O request data in the upper cache layer needs to be evicted, a random number is generated; if the random number is less than the probability value, the target I / O request data is selected using the LRU algorithm; if the random number is greater than or equal to the probability value, the target I / O request data is selected using the LFU algorithm; and the target I / O request data is evicted.

[0127] In this application, when I / O request data in the top-level cache is hit, the probability value of the corresponding upper-level cache layer is dynamically updated using the hit information. This probability value determines the specific eviction algorithm used to generate the cache data. Specifically, when the upper-level cache layer needs to evict a target I / O request data, a random number is first generated. If the random number is less than the dynamically updated probability value, the target I / O request data is directly selected using the LRU algorithm; if the random number is not less than the dynamically updated probability value, the target I / O request data is selected using the LFU algorithm. After the target I / O request data is selected, it is evicted. Therefore, in this application, the upper-level cache layer does not fixedly use either the LFU or LRU algorithm to evict target I / O request data. Instead, it dynamically selects between the LFU and LRU algorithms by combining a random number and the dynamically updated probability value based on the hit situation of the lower-level cache layer. This allows for more flexible matching of different access patterns in complex I / O request scenarios, thus adaptively scheduling and replacing the current I / O request data. In other words, this application can dynamically combine the underlying cache layer with the previous cache layer for management, thereby achieving mutual collaboration among multiple cache layers and ultimately effectively improving the cache hit rate.

[0128] In one specific embodiment of this application, the probability value update module is specifically used to read the historical access information corresponding to the I / O request data using the hit information;

[0129] When historical access information is used to determine the eviction algorithm used when I / O request data is evicted by the upper cache layer;

[0130] If the eviction algorithm is the LRU algorithm, then use the formula Reduce the probability value;

[0131] If the expulsion algorithm is the LFU algorithm, then utilize Increase the probability value;

[0132] Where P is the probability value, P' is the new probability value, λ and d correspond to the learning rate and discount rate of the upper cache layer relative to the probability value, respectively, T is the logical time when the I / O request data is hit in the lower cache layer, and evict_time is the logical time when the I / O request data is evicted by the upper cache.

[0133] In one specific embodiment of this application, the probability value update module is specifically used to dynamically update the probability value corresponding to the top-level cache layer using the hit information if the upper-level cache layer is the top-level cache layer.

[0134] If the upper cache layer is an intermediate cache layer, the probability value corresponding to the top cache layer is dynamically updated using the hit information.

[0135] In one specific embodiment of this application, the eviction module is specifically used to evict the target I / O request data to the area in the lower cache layer corresponding to the upper cache layer; wherein, different areas are set in the lower cache layer for different upper cache layers.

[0136] In one specific embodiment of this application, a new data buffer module is used to cache new I / O request data, specifically including: storing the new I / O request data into an intermediate cache layer in a multi-level cache;

[0137] Get the access frequency of new I / O request data within a specified time period;

[0138] By leveraging access frequency, new I / O request data is migrated to the corresponding cache layer.

[0139] In one specific embodiment of this application, the new data buffer module is specifically used to determine whether the access frequency is greater than the dynamic update frequency threshold;

[0140] If so, the new I / O request data will be migrated to the top-level cache layer.

[0141] In one specific embodiment of this application, the new data buffer module is specifically used to establish a first-in-first-out queue for each upper-layer cache layer; wherein, the number of records that the first-in-first-out queue can hold corresponds to the maximum I / O request data that the corresponding cache layer can cache;

[0142] In each first-in-first-out queue, record the access frequency corresponding to the evicted I / O request data;

[0143] Each time an I / O request is evicted, the average access frequency of all accesses in the corresponding first-in-first-out queue is recalculated and compared with the frequency threshold.

[0144] Based on the comparison results, the frequency threshold was adjusted.

[0145] Corresponding to the above method embodiments, this application also provides an electronic device. The electronic device described below and the multi-level cache management method described above can be referred to in correspondence.

[0146] See Figure 5 As shown, the electronic device includes:

[0147] Memory 332 is used to store computer programs;

[0148] The processor 322 is used to implement the steps of the multi-level cache management method in the above method embodiments when executing a computer program.

[0149] For details, please refer to Figure 6 , Figure 6 This is a schematic diagram of a specific structure of an electronic device provided in this embodiment. The electronic device can vary significantly due to differences in configuration or performance. It may include one or more central processing units (CPUs) 322 (e.g., one or more processors) and a memory 332. The memory 332 stores one or more computer application programs 342 or data 344. The memory 332 can be temporary or persistent storage. The program stored in the memory 332 may include one or more modules (not shown in the diagram), each module may include a series of instruction operations on the data processing device. Furthermore, the central processing unit 322 may be configured to communicate with the memory 332 and execute the series of instruction operations stored in the memory 332 on the electronic device 301.

[0150] Electronic device 301 may also include one or more power supplies 326, one or more wired or wireless network interfaces 350, one or more input / output interfaces 358, and / or one or more operating systems 341.

[0151] The steps in the multi-level cache management method described above can be implemented by the structure of an electronic device.

[0152] Corresponding to the above method embodiments, this application also provides a readable storage medium. The readable storage medium described below can be referred to in conjunction with the multi-level cache management method described above.

[0153] A readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the multi-level cache management method described in the above method embodiments.

[0154] Specifically, the readable storage medium can be a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, or any other readable storage medium capable of storing program code.

[0155] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0156] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0157] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0158] Finally, it should be noted that in this document, the terms include, encompass, or any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0159] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A multi-level cache management method, characterized in that, include: Each time I / O request data is hit in the lower layer of the multi-level cache, the probability value of the corresponding upper layer cache is dynamically updated using the hit information; When it is necessary to evict a target I / O request from the upper cache layer, a random number is generated; If the random number is less than the probability value, the target I / O request data is selected using the LRU algorithm; If the random number is greater than or equal to the probability value, the target I / O request data is selected using the LFU algorithm; Eject the target I / O request data; The step of dynamically updating the probability value of the corresponding upper-level cache layer using hit information includes: Using the hit information, read the historical access information corresponding to the I / O request data; When the historical access information is used to determine the eviction algorithm used when the I / O request data is evicted by the upper cache layer; If the eviction algorithm is the LRU algorithm, then the formula is used. Reduce the probability value; If the expulsion algorithm is the LFU algorithm, then utilize Increase the probability value; Wherein, P is the probability value, P' is the new probability value, 𝜆 and d correspond to the learning rate and discount rate of the upper cache layer relative to the probability value, respectively, T is the logical time when the I / O request data is hit in the lower cache layer, and evict_time is the logical time when the I / O request data is evicted by the upper cache.

2. The multi-level cache management method according to claim 1, characterized in that, The method of dynamically updating the probability value of the corresponding upper-level cache layer using hit information includes: If the upper cache layer is the top cache layer, then the probability value corresponding to the top cache layer is dynamically updated using the hit information; If the upper cache layer is an intermediate cache layer, then the hit information dynamically updates the probability value corresponding to the top cache layer.

3. The multi-level cache management method according to claim 1, characterized in that, Evicting the target I / O request data includes: The target I / O request data is evicted to the region in the lower cache layer that corresponds to the upper cache layer; wherein, different regions are set in the lower cache layer for different upper cache layers.

4. The multi-level cache management method according to claim 1, characterized in that, Cache new I / O request data, including: The new I / O request data is stored in the intermediate cache layer of the multi-level cache; Get the access frequency of the new I / O request data within a specified time period; Using the access frequency, the new I / O request data is migrated to the top-level cache layer.

5. The multi-level cache management method according to claim 4, characterized in that, Using the access frequency, the new I / O request data is migrated to the top-level cache layer, including: Determine whether the access frequency is greater than the dynamically updated frequency threshold; If so, the new I / O request data is migrated to the top-level cache layer.

6. The multi-level cache management method according to claim 5, characterized in that, Dynamically updating the frequency threshold includes: A first-in-first-out (FIFO) queue is established for each of the upper-level cache layers; wherein the number of records that the FIFO queue can hold corresponds to the maximum I / O request data that the corresponding cache layer can cache. In each of the aforementioned first-in-first-out queues, the access frequency corresponding to the evicted I / O request data is recorded; Each time an I / O request data is evicted, the average value of all access frequencies in the corresponding first-in-first-out queue is recalculated and compared with the value of the frequency threshold. Based on the comparison results, the frequency threshold is adjusted.

7. A multi-level cache management device, characterized in that, include: The probability value update module is used to dynamically update the probability value of the corresponding upper cache layer after each hit of I / O request data in the lower cache layer of the multi-level cache. A random number generation module is used to generate random numbers when it is necessary to evict a target I / O request data in the upper cache layer; The eviction confirmation module is used to select the target I / O request data using the LRU algorithm if the random number is less than the probability value, and to select the target I / O request data using the LFU algorithm if the random number is greater than or equal to the probability value. The eviction module is used to evict the target I / O request data; Specifically, the probability value update module is used to read the historical access information corresponding to the I / O request data using the hit information; to determine the eviction algorithm used when the I / O request data is evicted by the upper-layer cache layer using the historical access information; and if the eviction algorithm is the LRU algorithm, then the formula is used. Reduce the probability value; if the expulsion algorithm is the LFU algorithm, then utilize The probability value is increased; where P is the probability value, P' is the new probability value, 𝜆 and d correspond to the learning rate and discount rate of the upper cache layer relative to the probability value, respectively, T is the logical time when the I / O request data is hit in the lower cache layer, and evict_time is the logical time when the I / O request data is evicted by the upper cache.

8. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the multi-level cache management method as described in any one of claims 1 to 6 when executing the computer program.

9. A readable storage medium, characterized in that, The readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the multi-level cache management method as described in any one of claims 1 to 6.

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