An FPGA bus board applicable to multiple chassis slots

Abstract

The present invention discloses an FPGA bus board applicable to a variety of chassis slots, which includes a PCB board. The PCB board is provided with an FPGA chip, a level conversion chip, a CPCI bus, a PXI bus, a PXIe bus, and a signal connection area. The FPGA chip includes a processing module, a synchronous clock control module, a trigger control logic module, a PCIe core, and a PCI core that are all connected to the processing module. The signal connection area includes a synchronous clock signal connection area, a trigger signal connection area, a PCIe bus signal connection area, and a PCI bus signal connection area. This bus board integrates the CPCI bus, the PXI bus, and the PXIe bus at the same time, and designs a connection area suitable for a variety of different connectors, and can crimp the corresponding connectors according to different chassis slots to realize the insertion of the same bus board suitable for different slots, thus solving the technical problems of repeated design and resource waste existing in the existing bus boards.

Description

Technical Field

[0001] The present invention relates to the field of measurement and control technology, and particularly to an FPGA bus board applicable to multiple chassis slots. Background Art

[0002] At present, in the field of measurement and control instruments, there are mainly four types of bus boards based on FPGA chips, namely CPCI bus boards, PXI bus boards, CPCIe (CPCI Express) bus boards, and PXIe bus boards (PXI Express). The buses of these four types of bus boards have independent and complete specification definitions and constraints. Since the PXI bus can be compatible with the CPCI bus and the PXIe bus can be compatible with the CPCIe bus, these four types of bus boards can be classified into two incompatible types: PXI and PXIe. In practical applications, the two types of bus boards each have their own markets and their usage frequencies are roughly the same. However, due to differences in bus throughput, trigger bus, synchronous clock, power configuration, etc., the more advanced PXIe bus boards cannot completely replace the PXI bus boards.

[0003] At present, there are mainly three types of chassis on the market. One is a CPCI chassis that supports CPCI bus boards, one is a PXI chassis that supports PXI bus boards, and one is a PXIe chassis that supports PXI bus boards and PXIe bus boards. Although the PXIe specification designs a hybrid slot chassis, that is, one slot can support multiple bus boards, there is no technology that can enable a bus board to support multiple slots. Often, for bus boards with the same function, different designs are required to be realized for chassis with different slots, thus there are problems of repeated design and resource waste.

[0004] Therefore, it is necessary to develop new technologies to solve the above technical problems. Summary of the Invention

[0005] The present invention provides an FPGA bus board applicable to multiple chassis slots for the above technical problems. The bus board integrates the CPCI bus, PXI bus, and PXIe bus at the same time, and designs a connection area suitable for multiple different connectors, so that corresponding connectors can be crimped according to different chassis slots to realize the insertion of the same bus board suitable for different slots, and solves the technical problems of repeated design and resource waste existing in the existing bus boards.

[0006] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0007] An FPGA bus board applicable to multiple chassis slots, characterized in that: it includes a PCB board, on which an FPGA chip, a level conversion chip, a CPCI bus, a PXI bus, a PXIe bus and a signal connection area for crimping different connectors are provided;

[0008] The FPGA chip includes a processing module, a synchronous clock control module, a trigger control logic module, a PCIe core and a PCI core, and the synchronous clock control module, the trigger control logic module, the PCIe core and the PCI core are all connected to the processing module;

[0009] The signal connection area includes a synchronous clock signal connection area, a trigger signal connection area, a PCIe bus signal connection area and a PCI bus signal connection area; among them,

[0010] The PCI core is connected to the PCI bus signal connection area through the PCIe bus and the level conversion chip;

[0011] One end of the PXI bus is respectively connected to the trigger signal connection area and the PCI bus signal connection area, and the other end is respectively connected to the trigger control logic module and the PCI core;

[0012] One end of the PXIe bus is respectively connected to the synchronous clock signal connection area, the trigger signal connection area and the PCIe bus signal connection area, and the other end is respectively connected to the synchronous clock control module, the trigger control logic module and the PCIe core;

[0013] When the connector is crimped on the PCI bus signal connection area, the bus board is applicable to the CPCI chassis slot;

[0014] When the connector is crimped on the synchronous clock signal connection area and the trigger signal connection area, and crimped on the PCI bus signal connection area, the bus board is applicable to the PXI chassis slot;

[0015] When the connector is crimped on the synchronous clock signal connection area and the trigger signal connection area, and crimped on the PCIe bus signal connection area, the bus board is applicable to the PXIe chassis slot.

[0016] The signal connection areas are all arranged on the same side of the end of the PCB board, and the synchronous clock signal connection area, the trigger signal connection area, the PCIe bus signal connection area and the PCI bus signal connection area are arranged in sequence from top to bottom.

[0017] The signal connection area is a jack adapted to the connector pins.

[0018] The level conversion chip is used to convert 3.3V or 5V PCI signals into 3.3V PCI signals.

[0019] By adopting the above technical solution, the beneficial technical effects of the present invention are as follows:

[0020] The bus board card of the present invention integrates the CPCI bus, PXI bus and PXIe bus at the same time. Through the signal connection areas arranged on the PCB board and connected to the FPGA chip by using the CPCI bus, PXI bus and PXIe bus respectively, the present invention can connect different connectors, and can crimp the corresponding connectors according to different chassis slots during actual application to achieve that the same bus board card is suitable for plugging into different slots. That is to say, the present invention can support the plugging of different chassis slots by crimping different connectors according to actual needs, and solves the technical problems of repeated design and resource waste existing in the existing bus board cards. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is the principle block diagram of the present invention;

[0022] Figure 2 is the structural schematic diagram of the present invention with the J1 connector crimped;

[0023] Figure 3 is the structural schematic diagram of the present invention with the J1 connector and XJ4 connector crimped;

[0024] Figure 4 is the structural schematic diagram of the present invention with the XJ3 connector and XJ4 connector crimped. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] Since the PCI bus specification and PXI bus specification are relatively old, most design guides adopt traditional design schemes, technologies and devices, which can meet the performance indicators required by the specifications. However, with the development of technology, the current design schemes and device selections can greatly improve the performance of the design, such as higher logic operation speed, higher performance bus transmission DMA controller, higher integration and flexibility, and reduce the design time cost, device cost and product power consumption. Especially, the cost of some old devices has risen sharply in recent years. Therefore, the present invention provides a bus board card based on an FPGA chip. While the bus board card is suitable for plugging into multiple chassis slots, it can reduce the design cost for CPCI or PXI bus board cards, that is, it can realize the technology that one bus board card supports multiple slots, and can reduce costs and improve performance.

[0026] Such as Figure 1As shown in the figure, the bus board card includes a PCB board, on which there are an FPGA chip, a level conversion chip, a CPCI bus, a PXI bus, a PXIe bus, and a signal connection area for crimping different connectors. Since the specification supports two optional PCI signal level hardware, the level conversion chip is used to convert the 3.3V or 5V PCI signal into a 3.3V PCI signal. Among them,

[0027] The FPGA chip includes a processing module, a synchronous clock control module, a trigger control logic module, a PCIe core, and a PCI core. The synchronous clock control module, the trigger control logic module, the PCIe core, and the PCI core are all connected to the processing module.

[0028] The signal connection area includes a synchronous clock signal connection area, a trigger signal connection area, a PCIe bus signal connection area, and a PCI bus signal connection area. The synchronous clock signal connection area, the trigger signal connection area, the PCIe bus signal connection area, and the PCI bus signal connection area are all arranged on the same side of the end of the PCB board, and the synchronous clock signal connection area, the trigger signal connection area, the PCIe bus signal connection area, and the PCI bus signal connection area are arranged in sequence from top to bottom.

[0029] Furthermore, the synchronous clock signal connection area, the trigger signal connection area, the PCIe bus signal connection area, and the PCI bus signal connection area are all jacks arranged on the PCB board and adapted to the connector pins. These signal connection areas are used to crimp different connectors. For example, they can be used to crimp J1 connectors, XJ3 connectors, and XJ4 connectors. By crimping different connectors, the bus board card can be adapted to the plugging of different chassis slots.

[0030] In the FPGA chip, the PCI core is connected to the signal connection area through the PCI bus and the level conversion chip. One end of the PXI bus is respectively connected to the trigger signal connection area and the PCI bus signal connection area, and the other end is respectively connected to the trigger control logic module and the PCI core. One end of the PXIe bus is respectively connected to the synchronous clock signal connection area, the trigger signal connection area, and the PCIe bus signal connection area, and the other end is respectively connected to the synchronous clock control module, the trigger control logic module, and the PCIe core.

[0031] As Figure 2 shown, when the connector is crimped on the PCI bus signal connection area, the bus board card is applicable to the CPCI chassis slot.

[0032] As Figure 3 shown, when the connector is crimped on the synchronous clock signal connection area and the trigger signal connection area, and also crimped on the PCI bus signal connection area, the bus board card is applicable to the PXI chassis slot.

[0033] AsFigure 4 As shown, when the connector is crimped onto the synchronous clock signal connection area and the trigger signal connection area, and onto the PCIe bus signal connection area, this bus board is applicable to the PXIe chassis slot.

[0034] It should be noted that the FPGA chips and level conversion chips involved in the present invention are all existing conventional products. For example, the level conversion chip can adopt the SN74CBTD3861 chip of TI Corporation, and the FPGA can adopt the SMQ7K325T type FPGA of Shenzhen Guowei.

[0035] The following uses the above two designs for verification. When selecting ICs from other manufacturers, the design method is similar.

[0036] 1. PCI Core

[0037] For the PCI core part, the IP core instantiation of PCI needs to be carried out according to the conventional method, and the configuration space and the user BAR space address are allocated. In particular, the signals PCI_RST_N and PCI_FRAME_N need to be pulled up in the constraint file. An example of the BAR space setting is as follows:

[0038] BAR0: The space size is 4 kB, the starting address is 0x1000, and the rest of the BAR space is unused.

[0039] 2. PCIe Core

[0040] For the design of the PCIe core part, similarly, the IP core instantiation of PCIe is carried out according to the conventional method, and the configuration space and the user BAR space address are allocated. In particular, the signal PCIe_RST_N needs to be pulled up in the constraint file. The BAR space setting needs to be consistent with the lower bits of the BAR space of PCI, and the higher bits have one more bit of 1. An example of the BAR space setting is as follows:

[0041] BAR0: The space size is 4 kB, the starting address is 0x3000, and the rest of the BAR space is unused.

[0042] 3. Trigger Control Logic Module

[0043] The trigger control unit is no different from the conventional design. It mainly needs to implement the PXI trigger bus, star trigger, PXI adjacent trigger, and PXIe differential synchronous trigger functions according to the specifications.

[0044] 4. Synchronous Clock Control Module

[0045] The synchronous clock control logic requires a clock enable to gate the PCI clock and the PCIe clock. The gating signal is sourced from the latched PCIe reset signal. When the PCIe reset signal is low, it indicates that the PCIe bus has completed initialization. At this time, the PCIe core initialization is completed, and at the same time, the PCI initialization is prohibited to avoid bus conflicts.

[0046] 5. Board-specific logic

[0047] The board-specific logic can be added when designing the specific functions of the board. Specifically, the address of the board-specific logic is set to coincide with the address of the BAR0 space of the PCI, which facilitates access by both PCI and PCIe. An example of the dedicated logic space setting is: the space size is 4 kB, the starting address is 0x1000, and the internal logic judges the address by the lower 13 bits, and the higher bits are not used.

[0048] Through the above specific design, the present invention can achieve a technology in which a bus board supports multiple slots.

[0049] The above is only the specific implementation manner of the present invention. Any feature disclosed in this specification, unless specifically described, can be replaced by other equivalent or similar-purpose alternative features; all the features disclosed, or all the steps in any method or process, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. An FPGA bus board applicable to multiple chassis slots, characterized in that: It includes a PCB board, on which there are an FPGA chip, a level conversion chip, a CPCI bus, a PXI bus, a PXIe bus, and a signal connection area for crimping different connectors; The FPGA chip includes a processing module, a synchronous clock control module, a trigger control logic module, a PCIe core, and a PCI core. The synchronous clock control module, the trigger control logic module, the PCIe core, and the PCI core are all connected to the processing module; The signal connection area includes a synchronous clock signal connection area, a trigger signal connection area, a PCIe bus signal connection area, and a PCI bus signal connection area; among them, The PCI core is connected to the PCI bus signal connection area through the PCIe bus and the level conversion chip; One end of the PXI bus is respectively connected to the trigger signal connection area and the PCI bus signal connection area, and the other end is respectively connected to the trigger control logic module and the PCI core; One end of the PXIe bus is respectively connected to the synchronous clock signal connection area, the trigger signal connection area, and the PCIe bus signal connection area, and the other end is respectively connected to the synchronous clock control module, the trigger control logic module, and the PCIe core; When the connector is crimped on the PCI bus signal connection area, the bus board is applicable to the CPCI chassis slot; When the connector is crimped on the synchronous clock signal connection area and the trigger signal connection area, and also on the PCI bus signal connection area, the bus board is applicable to the PXI chassis slot; When the connector is crimped on the synchronous clock signal connection area and the trigger signal connection area, and also on the PCIe bus signal connection area, the bus board is applicable to the PXIe chassis slot.

2. The FPGA bus board applicable to multiple chassis slots according to claim 1, wherein: The signal connection areas are all arranged on the same side of the end of the PCB board, and the synchronous clock signal connection area, the trigger signal connection area, the PCIe bus signal connection area, and the PCI bus signal connection area are arranged in sequence from top to bottom.

3. The FPGA bus board applicable to multiple chassis slots according to claim 1, wherein: The signal connection area is a jack adapted to the connector pins.

4. The FPGA bus board applicable to multiple chassis slots according to claim 1, wherein: The level conversion chip is used to convert the 3.3V or 5V PCI signal into a 3.3V PCI signal.

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