Chip Search Methods and Devices

Abstract

This invention discloses a wafer search method and apparatus. The method includes: obtaining a target wafer and a reference wafer; determining a first specific region in the target wafer and obtaining a first significant distribution feature of the first specific region; determining a second specific region in the reference wafer and obtaining a second significant distribution feature of the second specific region; in response to determining that the first significant distribution feature corresponds to the second significant distribution feature, estimating the fault pattern similarity between the first specific region and the second specific region; and in response to determining that the fault pattern similarity is higher than a threshold value, providing a reference wafer as the search result corresponding to the target wafer.

Description

Technical Field

[0001] This invention relates to a search method and apparatus, and more particularly to a chip search method and apparatus. Background Technology

[0002] In the existing technology, when a user wants to search for other chips with similar die (chip) failure patterns to a target chip in a database, the user usually makes a visual judgment or draws a specific area on the target chip so that the search system can compare it with other chips in the database.

[0003] Please refer to Figure 1A This is a schematic diagram of an existing chip alignment mechanism. Figure 1A In this scenario, assuming the user selects chip 101 as the target chip, the user can draw a specific region 101a on chip 101. The search system can then use this drawing to find other specific regions corresponding to region 101a in other chips in the database, such as region 102a in chip 102 and region 103a in chip 103. The search system can then estimate the die failure ratio in region 101a (e.g., 62% as shown), and estimate the die failure ratios in specific regions of other chips, such as 60% for region 102a and 59% for region 103a. After obtaining the die failure ratios in specific regions of other chips, the search system can use chips with die failure ratios close to those of region 101a (e.g., chips 102 and 103) as search results corresponding to chip 101.

[0004] However, the above approach has at least the following drawbacks: (1) When the die fault pattern in the target chip is special, the user has to painstakingly set the appropriate specific area, which is both time-consuming and inaccurate; (2) After the target chip is selected, the search system begins to acquire the die level data of other chips, which takes a lot of time; (3) Only the specific area is considered and other areas are not considered, so it is easy to select chips with a wide range of fault patterns as the search result of the target chip; (4) Since the die level data is considered, when the size, shape and total number of each chip are different, it is impossible to make cross-product comparisons.

[0005] Please refer to Figure 1B This is a schematic diagram of the die-level data for two wafers. Figure 1BIn the example, chip 104 has 38 and 44 dies on its horizontal and vertical axes, respectively, while chip 105 has 287 and 8 dies on its horizontal and vertical axes, respectively. Under these circumstances, chips 104 and 105 cannot be compared across products due to their different sizes, shapes, and total numbers. Summary of the Invention

[0006] In view of this, the present invention provides a chip searching method and apparatus, which can be used to solve the above-mentioned technical problems.

[0007] This invention provides a wafer search method, suitable for a wafer search device. The method includes: acquiring a target wafer and a reference wafer, wherein the target wafer and the reference wafer are individually distributed with a plurality of faulty dies and a plurality of normal dies, and the target wafer is divided into a plurality of first regions, and the reference wafer is divided into a plurality of second regions corresponding to the plurality of first regions; determining a first specific region among the plurality of first regions, and acquiring a first significant distribution feature of the fault patterns of the plurality of faulty dies in the first specific region; determining at least one second specific region among the plurality of second regions, and acquiring a second significant distribution feature of the fault patterns of the plurality of faulty dies in each second specific region; in response to determining that the first significant distribution feature corresponds to any second significant distribution feature of the at least one second specific region, estimating a fault pattern similarity between the first specific region and each second specific region; and in response to determining that the fault pattern similarity is higher than a similarity threshold, providing a reference wafer as a search result corresponding to the target wafer.

[0008] This invention provides a wafer search device, including a storage circuit and a processor. The storage circuit stores program code. The processor is coupled to the storage circuit and accesses the program code to execute: acquiring a target wafer and a reference wafer, wherein the target wafer and the reference wafer each have a plurality of faulty dies and a plurality of normal dies individually distributed thereon, and the target wafer is divided into a plurality of first regions, and the reference wafer is divided into a plurality of second regions corresponding to the plurality of first regions; determining a first specific region among the plurality of first regions, and acquiring a first significant distribution feature of the fault patterns of the plurality of faulty dies in the first specific region; determining at least one second specific region among the plurality of second regions, and acquiring a second significant distribution feature of the fault patterns of the plurality of faulty dies in each second specific region; in response to determining that the first significant distribution feature corresponds to any second significant distribution feature of the at least one second specific region, estimating a fault pattern similarity between the first specific region and each second specific region; in response to determining that the fault pattern similarity is higher than a similarity threshold, providing a reference wafer as a search result corresponding to the target wafer. Attached Figure Description

[0009] Figure 1A This is a schematic diagram of an existing chip alignment mechanism;

[0010] Figure 1B This is a schematic diagram of the die-level data for two chips;

[0011] Figure 2 This is a schematic diagram of a chip searching device according to an embodiment of the present invention;

[0012] Figure 3 This is a schematic diagram of a wafer divided into multiple regions, illustrating an embodiment of the present invention;

[0013] Figure 4 This is a schematic diagram illustrating the coordinate normalization mechanism of an embodiment of the present invention;

[0014] Figure 5 This is a flowchart illustrating a chip search method according to an embodiment of the present invention;

[0015] Figure 6 This is a schematic diagram illustrating the estimation of the first feature value of each preset distribution feature in a first specific region, according to an embodiment of the present invention.

[0016] Figure 7 This is a schematic diagram illustrating wafer alignment according to an embodiment of the present invention.

[0017] Symbol Explanation

[0018] 101~105, 300, 400: Chips

[0019] 101a~103a: Specific areas

[0020] 200: Chip Search Device

[0021] 202: Storage Circuit

[0022] 204: Processor

[0023] 710: Target chip

[0024] 711~714: First District

[0025] 720, 730, 740: Reference chips

[0026] 721~724, 731~734, 741~744: Second Region

[0027] A1~A9: Area

[0028] G1~G4: Feature Enhancement Matrix

[0029] MM: First die distribution matrix

[0030] M1~M4: Reference die distribution matrix

[0031] Ma~Me: Element

[0032] S510~S550: Steps Detailed Implementation

[0033] Please refer to Figure 2 This is a schematic diagram of a chip search device according to an embodiment of the present invention. In different embodiments, the chip search device 200 may be implemented as various computer devices and / or intelligent devices, but is not limited thereto.

[0034] like Figure 2 As shown, the chip search device 200 may include a storage circuit 202 and a processor 204. The storage circuit 202 may be, for example, any type of fixed or removable random access memory (RAM), read-only memory (ROM), flash memory, hard disk or other similar device or combination of these devices, and may be used to record multiple program codes or modules.

[0035] Processor 204 is coupled to memory circuit 202 and may be a general purpose processor, special purpose processor, conventional processor, digital signal processor, multiple microprocessors, one or more microprocessors incorporating a digital signal processor core, controller, microcontroller, application specific integrated circuit (ASIC), field programmable gate array (FPGA), any other type of integrated circuit, state machine, processor based on advanced RISC machine (ARM), and the like.

[0036] In an embodiment of the present invention, the processor 204 can access the modules and program code recorded in the storage circuit 202 to implement the chip search method proposed in the present invention, the details of which are described below.

[0037] In embodiments of the present invention, the chip search device 200 may maintain a chip database containing multiple chips, from which a user can select a chip to be used as a comparison benchmark, allowing the chip search device 200 to find other similar chips in the chip database. In some embodiments, each chip in the chip database may include multiple faulty dies and multiple normal dies.

[0038] In embodiments of the present invention, to facilitate the execution of the proposed wafer search method, each wafer under consideration can be divided into multiple regions, such as... Figure 3 As shown in the example. Please refer to... Figure 3 This is a schematic diagram of a wafer divided into multiple regions, according to an embodiment of the present invention.

[0039] like Figure 3 As shown, the wafer 300 can be divided into nine regions A1 to A9. In embodiments of the present invention, each wafer in the wafer database is divided into multiple regions corresponding to regions A1 to A9. For ease of explanation, it is assumed below that each wafer under consideration is divided into regions A1 to A9, but this is not a limitation.

[0040] In one embodiment, the processor 204 may also pre-estimate the proportion of faulty dies in individual regions A1 to A9. In some embodiments, for the i-th region (hereinafter referred to as region Ai) among regions A1 to A9, the processor 204 may calculate the number of faulty dies and the total number of dies in region Ai, and divide the number of faulty dies by the total number of dies as the proportion of faulty dies in region Ai, but may not be limited to this.

[0041] In other embodiments, each wafer in the wafer database may also be divided in other ways according to the designer's needs, and is not limited to... Figure 3 The state is shown. Furthermore, the processor 204 can also estimate the proportion of faulty dies in each region of each chip in advance for subsequent use.

[0042] In some embodiments, the processor 204 may pre-represent each faulty die and normal die of each chip using normalized coordinates.

[0043] Please refer to Figure 4 This is a schematic diagram illustrating a coordinate normalization mechanism according to an embodiment of the present invention. Figure 4 In this context, it is assumed that the horizontal axis of the chip 400 includes x1 to xn, and the vertical axis includes y1 to ym (n and m are positive integers). In this case, for the die 401 with coordinates (a, b) on the chip 400, the processor 204 can accordingly rewrite the coordinates of the die 401 using the corresponding normalized coordinates. Figure 4 In this context, the normalized coordinates of die 401 can be represented, for example, as (a', b') = ((a-x1) / n, (b-y1) / m), but are not limited to this. Based on the principle of similarity, the coordinates of each die on each wafer in the wafer database are represented by the processor 204 in corresponding normalized coordinates.

[0044] Please refer to Figure 5 This is a flowchart illustrating a chip search method according to an embodiment of the present invention. The method of this embodiment can be derived from... Figure 2 The chip search device 200 is executed, and the following is paired with Figure 2 Component description shown Figure 5Details of each step.

[0045] First, in step S510, the processor 204 can obtain the target chip and the reference chip.

[0046] In some embodiments, a user may select one or more chips (hereinafter referred to as selected chips) in a chip database, and the processor 204 may find one or more chips in the chip database as search results for the user's reference.

[0047] In some embodiments, the processor 204 may determine a target wafer based on one or more selected wafers and compare this target wafer individually with each wafer in the wafer database. For ease of explanation, the wafer used for comparison with the target wafer will be referred to as a reference wafer, but is not limited thereto.

[0048] In different embodiments, the processor 204 may, depending on the user's settings, decide to use a single selected chip as the target chip, or to integrate one or more selected chips to generate the corresponding target chip.

[0049] In one embodiment, the processor 204 may, for example, allow a user to select a region of interest (e.g., region A1) on a selected chip, wherein this region of interest is the region in the target chip used for comparison with a reference chip in the future (hereinafter referred to as the first specific region).

[0050] Subsequently, the processor 204 allows the user to decide whether to compare all regions on the reference chip individually with the first specific region (hereinafter referred to as the undefined region scenario), or to compare only the regions on the reference chip whose locations correspond to the first specific region with the first specific region (hereinafter referred to as the defined region scenario).

[0051] In one embodiment, it is assumed that the user selects region A1 as the region of interest. In this case, in the first embodiment (i.e., the limited region scenario), when the user decides to compare only the region on the reference chip that corresponds to the first specific region (e.g., region A1 on the reference chip) with the first specific region in the future, the processor 204 can generate the corresponding target chip by integrating one or more of the selected chips.

[0052] Specifically, in the first embodiment (i.e., the defined region scenario), the processor 204 can determine the faulty die on the target wafer based on the faulty dies on each selected wafer. Specifically, in one embodiment, in response to determining that each selected wafer has a faulty die located at a specific location, the processor 204 can determine that the target wafer has a faulty die located at a specific location. On the other hand, in response to determining that any of the selected wafers does not have a faulty die located at a specific location, the processor 204 can determine that the target wafer does not have a faulty die located at a specific location.

[0053] From another perspective, processor 204 can be understood as determining the faulty die on the target chip by taking the intersection of the faulty dies on each selected chip. For example, processor 204 can first create a blank chip (i.e., the fault / normal status of all dies is undetermined) as the target chip. Then, when all selected chips have faulty dies at a certain location, processor 204 sets the die at the corresponding location on the target chip as the faulty die, and when not all selected chips have faulty dies at a certain location, processor 204 sets the die at the corresponding location on the target chip as the normal die, but this is not limited to this.

[0054] On the other hand, in the second embodiment (i.e., the undefined region scenario), when the user decides to compare all regions on the reference chip individually with the first specific region, the processor 204 can select a single chip as the target chip for comparison with the reference chip. In the second embodiment, after the comparison is completed, the processor 204 can select another of the aforementioned selected chips as the target chip and compare it again with the same reference chip, but is not limited to this.

[0055] After obtaining the target chip, the processor 204 may divide the target chip into multiple regions (hereinafter referred to as the first region) as previously stated, and the reference chip may also be divided into multiple regions (hereinafter referred to as the second region) corresponding to the multiple first regions.

[0056] Next, in step S520, the processor 204 may determine a first specific region in the plurality of first regions and obtain a first significant distribution feature of the fault pattern of the plurality of faulty dies in the first specific region.

[0057] As previously stated, the processor 204 can determine the first specific region on the target chip based on the region of interest determined by the user. For example, assuming the region of interest determined by the user is region A1 on each selected chip, the processor 204 will select region A1 on the target chip as the first specific region; if the region of interest determined by the user is region A2 on each selected chip, the processor 204 will select region A2 on the target chip as the first specific region, but it is not limited to this.

[0058] In one embodiment, the first significant distribution feature is one of a plurality of preset distribution features. During the process of the processor 204 acquiring the first significant distribution feature of the fault patterns of the plurality of faulty dies in the first specific region, the processor 204 may first estimate a plurality of first feature values ​​of the aforementioned preset distribution features in the first specific region. The following is supplemented with… Figure 6 Further explanation is needed.

[0059] Please refer to Figure 6This is a schematic diagram illustrating, according to an embodiment of the present invention, the estimation of first feature values ​​of preset distribution characteristics of a first specific region. In this embodiment, it is assumed that the first specific region is the i-th first region among the plurality of first regions. In this case, the processor 204 can obtain the first fault die ratio of the first specific region according to previous teachings (i.e., by dividing the total number of faulty dies in the first specific region by the total number of dies in the first specific region, in F...). i express).

[0060] The processor 204 can then characterize the target wafer as a first die distribution matrix MM, wherein the elements (shown as diagonal grids) with a first value (e.g., 1) in the first die distribution matrix MM correspond to one of the faulty dies of the target wafer, and the elements (shown as blank grids) with a second value (e.g., 0) in the first die distribution matrix MM correspond to one of the normal dies of the target wafer.

[0061] exist Figure 6 In this context, the considered preset distribution features include, for example, horizontal features, vertical features, right-side diagonal features, and left-side diagonal features (which may be referred to as the 1st to 4th preset distribution features, respectively), and the aforementioned preset distribution features are not limited to these. In this case, the processor 204 can perform a convolution operation between the first die distribution matrix MM and the j-th feature enhancement matrix of the plurality of feature enhancement matrices G1 to G4 to generate the j-th reference die distribution matrix among the plurality of reference die distribution matrices, wherein the j-th feature enhancement matrix corresponds to the j-th preset distribution feature among the aforementioned preset distribution features.

[0062] For example, processor 204 can perform a convolution operation between the first die distribution matrix MM and the feature enhancement matrix G1 to generate a reference die distribution matrix M1 corresponding to the horizontal features. From another perspective, processor 204 can be understood as enhancing the horizontal features of the fault pattern in the first die distribution matrix MM. For example, processor 204 can limit the convolution operation between the first die distribution matrix MM and the feature enhancement matrix G1 in each step, ensuring that the current sum is greater than or equal to a set threshold (e.g., 3), before retaining the elements currently used for convolution in the first die distribution matrix MM in the reference die distribution matrix M1. In this case, elements that are not horizontally discontinuous in the first die distribution matrix MM, such as elements Ma, Mb, and Mc, will not be retained in the reference die distribution matrix M1.

[0063] Similarly, processor 204 can perform a convolution operation between the first die distribution matrix MM and the feature enhancement matrix G2 to generate a reference die distribution matrix M2 corresponding to the vertical features. In this case, elements that are not vertically discontinuous in the first die distribution matrix MM will not be retained in the reference die distribution matrix M2, such as elements Mb, Mc, Md, Me, and Mf.

[0064] Furthermore, the processor 204 can perform a convolution operation between the first die distribution matrix MM and the feature enhancement matrix G3 to generate a reference die distribution matrix M3 corresponding to the right-diagonal features. In this case, elements that are discontinuous in the right-diagonal direction in the first die distribution matrix MM will not be retained in the reference die distribution matrix M3, such as elements Mb, Mc, Me, and Mf.

[0065] Similarly, processor 204 can perform a convolution operation between the first die distribution matrix MM and the feature enhancement matrix G4 to generate a reference die distribution matrix M4 corresponding to the features in the left diagonal direction. In this case, elements that are discontinuous in the left diagonal direction in the first die distribution matrix MM will not be retained in the reference die distribution matrix M4.

[0066] After obtaining the reference die distribution matrices M1 to M4, the processor 204 can estimate the j-th faulty die number among multiple faulty die numbers based on the elements with a first value in the j-th reference die distribution matrix, wherein the j-th faulty die number corresponds to the j-th preset distribution feature. Figure 6 In the reference die distribution matrix M1, since the number of elements with the first value is 8 (i.e., the number of diagonal cells in the reference die distribution matrix M1), the processor 204 can estimate the number of faulty dies corresponding to the horizontal direction feature (i.e., the first preset distribution feature) as 8. Furthermore, since the number of elements with the first value in the reference die distribution matrix M2 is 6 (i.e., the number of diagonal cells in the reference die distribution matrix M2), the processor 204 can estimate the number of faulty dies corresponding to the vertical direction feature (i.e., the second preset distribution feature) as 6. Based on the similarity principle, the processor 204 can estimate the number of faulty dies for the right diagonal direction feature and the left diagonal direction feature as 7 and 2 respectively; the details are not elaborated here.

[0067] After obtaining the number of faulty dies corresponding to each preset distribution feature, the processor 204 can estimate the j-th first feature value among the aforementioned first feature values ​​of the first specific region based on the j-th faulty die number and the first faulty die ratio of the first specific region, wherein the j-th first feature value corresponds to the j-th preset distribution feature. In one embodiment, the processor 204 can divide the j-th faulty die number by the first faulty die ratio of the first specific region (i.e., F...).i To obtain the j-th first feature value (in P) corresponding to the j-th preset distribution feature. ij express).

[0068] exist Figure 6 In this context, processor 204 can divide the number of the first faulty die (i.e., 8) by F. i To obtain the first feature value corresponding to the horizontal direction feature (i.e., P) i1 Similarly, processor 204 can divide the number of the second faulty die (i.e., 6) by F. i To obtain the second first feature value corresponding to the vertical direction feature (i.e., P) i2 Based on the principle of similarity, processor 204 can correspondingly obtain P. i3 and P i4 The details will not be elaborated here.

[0069] In obtaining the aforementioned preset distribution characteristics of the first specific region, the plurality of first feature values ​​(e.g., P) i1 ~P i4 Afterwards, the processor 204 can find the first highest eigenvalue among the aforementioned first eigenvalues, and find the one corresponding to the first highest eigenvalue among the aforementioned preset distribution features in the first specific region as the first significant distribution feature. For example, suppose the processor 204 determines P i1 In P i1 ~P i4 If the highest eigenvalue is found in the middle, then processor 204 can determine that it corresponds to P. i1 The horizontal direction feature is the first significant distribution feature of the first specific region. For another example, suppose processor 204 determines P... i2 In P i1 ~P i4 If the highest eigenvalue is found in the middle, then processor 204 can determine that it corresponds to P. i2 The vertical direction feature is the first significant distribution feature of the first specific region.

[0070] Next, in step S530, the processor 204 may determine at least one second specific region among the plurality of second regions and obtain the second significant distribution features of the fault patterns of the plurality of faulty dies in each second specific region.

[0071] In embodiments of the present invention, the at least one second specific region can be understood as a region in the reference wafer used for comparison with a first specific region of the target wafer.

[0072] Therefore, in the first embodiment (i.e., the defined region scenario), the processor 204 can identify one of the plurality of second regions that corresponds to the same position as the first specific region as the second specific region. For example, if the first specific region is region A1 in the target wafer, the processor 204 can select region A1 in the reference wafer as the second specific region. In other words, if the position of the first specific region is defined as needing to correspond to the position of the second specific region, the processor 204 can identify one of the plurality of second regions that corresponds to the same position as the first specific region as the second specific region. That is, in the first embodiment, there will only be one second specific region in the reference wafer, but it is not limited to this.

[0073] On the other hand, in the second embodiment (i.e., the undefined region scenario), the processor 204 may use all of the plurality of second regions as second specific regions. In other words, if the location of the first specific region is not limited to correspond to the location of the second specific region, the processor 204 may use all of the plurality of second regions as second specific regions. That is, in the second embodiment, the number of second specific regions may be the same as the number of second regions, but it is not limited to this.

[0074] After determining one or more second specific regions according to the above teachings, the processor 204 can obtain a second significant distribution feature of the fault pattern of the plurality of faulty dies in each second specific region. In one embodiment, the processor 204 can estimate a plurality of second feature values ​​(denoted as P′) of the preset distribution feature of each second specific region. ij (represented); Among the plurality of second characteristic values, find the second highest characteristic value, and among the aforementioned preset distribution characteristics of each second specific region, find the one corresponding to the second highest characteristic value as the second significant distribution characteristic. The processor 204 obtains the second significant distribution characteristics of each second specific region in a manner similar to that of obtaining the first significant distribution characteristics of the first specific region; therefore, relevant details can be found in [reference needed]. Figure 6 The explanation will not be repeated here.

[0075] In other embodiments, the processor 204 may pre-calculate multiple feature values ​​and corresponding significant distribution features of the preset distribution features of each chip in the chip database, so as to directly retrieve them after the user selects a chip, thereby accelerating the efficiency of subsequent processing, but it is not limited to this.

[0076] For example, in one embodiment, when obtaining the first significant distribution feature of the fault pattern of a faulty die in a first specific region, the processor 204 can directly obtain the first feature value of the preset distribution feature of the first specific region from the aforementioned wafer database, find the first highest feature value among the first feature values, and find the one corresponding to the first highest feature value among the preset distribution features of the first specific region as the first significant distribution feature, but this is not limited to this. Similarly, when obtaining the second significant distribution feature of the fault pattern of a faulty die in a second specific region, the processor 204 can also directly obtain the second feature value of the preset distribution feature of the second specific region from the aforementioned wafer database, find the second highest feature value among the second feature values, and find the one corresponding to the second highest feature value among the preset distribution features of the second specific region as the second significant distribution feature, but this is not limited to this.

[0077] In one embodiment, the processor 204 may determine whether the first significant distribution feature corresponds to any second significant distribution feature of the second specific region.

[0078] In the first embodiment (i.e., the defined region scenario), since there is only one second specific region in the reference wafer, the processor 204 can determine whether the first significant distribution feature of the first specific region and the second significant distribution feature of the second specific region both correspond to the same preset distribution feature. If so, the processor 204 can determine that the first significant distribution feature corresponds to the second significant distribution feature of the second specific region; otherwise, it can determine that the first significant distribution feature does not correspond to the second significant distribution feature of the second specific region.

[0079] For example, assuming both the first and second salient features are horizontal features, the processor 204 can determine that the first salient distribution feature corresponds to the second salient distribution feature of the second specific region. As another example, assuming both the first and second salient features are vertical features, the processor 204 can also determine that the first salient distribution feature corresponds to the second salient distribution feature of the second specific region.

[0080] On the other hand, assuming the first salient feature is a horizontal feature, but the second salient feature is a vertical feature, a left diagonal feature, or a right diagonal feature, the processor 204 can determine that the first salient distribution feature does not correspond to the second salient distribution feature of the second specific region, but it is not limited to this.

[0081] In the second embodiment (i.e., the undefined region scenario), the processor 204 can determine whether the first salient distribution feature and the second salient distribution feature of any of the second specific regions both correspond to the same preset distribution feature. If so, the processor 204 can determine that the first salient distribution feature corresponds to the second salient distribution feature of any of the second specific regions. On the other hand, if the first salient feature is different from the second salient features of each of the second specific regions, the processor 204 can determine that the first salient distribution feature does not correspond to the second salient distribution feature of any of the second specific regions.

[0082] For example, assuming the first salient feature is a left-slanting feature, then when any second salient distribution feature in the second specific region is a left-slanting feature, the processor 204 can determine that the first salient distribution feature corresponds to any second salient distribution feature in the second specific region. As another example, assuming the first salient feature is a right-slanting feature, then when any second salient distribution feature in the second specific region is a right-slanting feature, the processor 204 can determine that the first salient distribution feature corresponds to any second salient distribution feature in the second specific region.

[0083] On the other hand, assuming that the first significant distribution feature is a horizontal feature, but the second significant features of each second specific region are not horizontal features, the processor 204 can determine that the first significant distribution feature does not correspond to any of the second significant distribution features of the second specific region, but it is not limited to this.

[0084] Therefore, in step S540, in response to determining that the first significant distribution feature corresponds to any second significant distribution feature of the second specific region, the processor 204 can estimate the fault pattern similarity between the first specific region and each of the second specific regions.

[0085] In an embodiment of the present invention, for the i-th second specific region within the aforementioned second specific region, the processor 204 may estimate a plurality of second feature values ​​of the aforementioned pre-distributed features of the i-th second specific region. Then, the processor 204 may, based on the aforementioned first feature value (P) of the first specific region... ij The second feature value (P') of the i-th second specific region. ij The number of the aforementioned preset distribution features (represented by m) and the correction parameter (represented by z) are used to estimate the fault pattern similarity between the first specific region and the i-th second specific region.

[0086] In the first embodiment (i.e., the defined region scenario), since there is only one second specific region in the reference wafer (which may be the i-th second region), the fault pattern similarity between the first specific region and the second specific region (denoted as S) is... i (Indicated) can be estimated as "S" i =∑j I j ×(z-|P ij -P' ij |) / (z×m)”. In some embodiments, z is, for example, a value between 0 and 1 (e.g., 0.2), but is not limited to this. Additionally, if |P ij -P' ij |<z, then I j If |P ij -P' ij |≥z, then I j It can be 0, but it is not limited to this.

[0087] In the second embodiment (i.e., the undefined region scenario), the fault pattern similarity (denoted by S) between the first specific region and the i-th second specific region (which may be the i-th second region) is... i (Indicated) can be estimated as "S" i =∑ j I j ×(z-|P ij -P' ij |) / (z×m)”. In some embodiments, z is, for example, a value between 0 and 1 (e.g., 0.2), but is not limited to this. Additionally, if |P ij -P' ij |<z, then I j If |P ij -P' ij |≥z, then I j It can be 0, but it is not limited to this.

[0088] The similarity of fault patterns between the first specific region and each second specific region is obtained (i.e., S). i After that, the processor 204 can determine whether the similarity of the fault pattern is higher than the similarity threshold (denoted by T). In different embodiments, T can be set to any value according to the designer's needs, such as 80, but is not limited to this.

[0089] Subsequently, in step S550, in response to the determination that the similarity of the fault pattern is higher than the similarity threshold, the processor 204 can provide a reference chip as the search result corresponding to the target chip.

[0090] In the first embodiment (i.e., the defined region scenario), since there is only one second specific region in the reference wafer, the processor 204 can determine the S corresponding to this second specific region. i Is it higher than a similarity threshold? If so, the processor 204 can accordingly use the reference wafer as the search result corresponding to the target wafer. On the other hand, if the S corresponding to this second specific region... iIf the similarity threshold is not exceeded, the processor 204 may not provide a reference chip as a search result corresponding to the target chip, but this is not a limitation.

[0091] In the second embodiment (i.e., the undefined region scenario), the processor 204 can determine any S corresponding to the second specific region. i Is it higher than a similarity threshold? If so, the processor 204 can accordingly use the reference wafer as the search result corresponding to the target wafer. On the other hand, if the S corresponding to each second specific region... i If the similarity threshold is not exceeded, the processor 204 can use the other of the selected chips as a new target chip, and determine whether to use the reference chip as the search result corresponding to the new target chip according to the above teaching. In short, in the second embodiment, after completing the comparison between one of the selected chips and the reference chip, the processor 204 can compare the other of the selected chips with the same reference chip to determine whether to use this reference chip as the search result of the other of the selected chips, but it is not limited to this.

[0092] After completing the comparison between the target chip and the reference chip, the processor 204 may use other chips in the chip database as new reference chips, and decide whether to use this new reference chip as the search result of the target chip according to the above instructions, but it is not limited to this.

[0093] Therefore, the method of the present invention can provide one or more chips with similar fault patterns to the target chip in the chip database as the search results of the target chip, and the user can perform subsequent common machine analysis based on the search results corresponding to the target chip, or perform machine variance analysis (ANOVA) or correlation analysis with the above-mentioned feature values.

[0094] To make the concept of this invention easier to understand, the following additional information is provided. Figure 7 For further explanation, please refer to [link / reference]. Figure 7 This is a schematic diagram of wafer alignment according to an embodiment of the present invention. Figure 7 In this context, it is assumed that each chip under consideration is divided into four corresponding regions. For example, the target chip 710 may be divided into first regions 711 to 714, the reference chip 720 may be divided into second regions 721 to 724 corresponding to the first regions 711 to 714, the reference chip 730 may be divided into second regions 731 to 734 corresponding to the first regions 711 to 714, and the reference chip 740 may be divided into second regions 741 to 744 corresponding to the first regions 711 to 714, but this is not a limitation.

[0095] exist Figure 7In this context, assuming the user selects the first region 712 as the first specific region of the target chip 710, the user can then decide whether to compare the target chip 710 with each of the reference chips 720, 730, and 740 based on the first embodiment (i.e., the limited region scenario) or the second embodiment (i.e., the unlimited region scenario).

[0096] Assuming the user chooses to adopt the first embodiment (i.e., the limited region scenario), the processor 204 will only select the second region corresponding to the first specific region (i.e., the first region 712) in each reference chip as the second specific region under consideration. In this case, the processor 204 will select the second region 722 in reference chip 720 corresponding to the first region 712 as the second specific region in reference chip 720, select the second region 732 in reference chip 730 corresponding to the first region 712 as the second specific region in reference chip 730, and select the second region 742 in reference chip 740 corresponding to the first region 712 as the second specific region in reference chip 740.

[0097] exist Figure 7 In this embodiment, assuming that a first salient feature of a first specific region (i.e., first region 712) is determined to be a right-angled feature, and a second salient feature of a second specific region of the reference chip 730 (i.e., second region 732) is also determined to be a right-angled feature, the processor 204 can further estimate the fault pattern similarity between the first specific region (i.e., first region 712) and the second specific region of the reference chip 730 (i.e., second region 732), and then decide whether to provide the reference chip 730 as a search result for the target chip 710. If the fault pattern similarity between the first specific region (i.e., first region 712) and the second specific region of the reference chip 730 (i.e., second region 732) is higher than a similarity threshold, the processor 204 can provide the reference chip 730 as a search result for the target chip 710 in the first embodiment.

[0098] On the other hand, since neither the second salient feature of the second specific region (i.e., the second region 722) of the reference chip 720 nor the second salient feature of the second specific region (i.e., the second region 742) of the reference chip 740 is a right-angled feature, the processor 204 may not provide the reference chips 720 and 740 as search results of the target chip 710 in the first embodiment.

[0099] Furthermore, assuming the user chooses to adopt the second embodiment (i.e., the undefined region scenario), the processor 204 can select each second region in each reference chip as the second specific region under consideration. In this case, the processor 204 will select second regions 721-724 in reference chip 720 as the second specific region in reference chip 720, select second regions 731-734 in reference chip 730 as the second specific region in reference chip 730, and select second regions 741-744 in reference chip 740 as the second specific region in reference chip 740.

[0100] exist Figure 7 Since the second significant features of each of the second regions 721 to 724 in the reference chip 720 are not right-slanted features, the processor 204 may provide the reference chip 720 as a search result of the target chip 710 in the second embodiment.

[0101] Furthermore, since the second salient feature of one of the second specific regions (i.e., the second region 732) in the reference chip 730 is also a right-slanted feature, the processor 204 can further estimate the fault pattern similarity between the first specific region (i.e., the first region 712) and the second specific region (i.e., the second region 732) of the reference chip 730, and then decide whether to provide the reference chip 730 as a search result for the target chip 710. Assuming that the fault pattern similarity between the first specific region (i.e., the first region 712) and the second specific region (i.e., the second region 732) of the reference chip 730 is higher than a similarity threshold, the processor 204 can provide the reference chip 730 as a search result for the target chip 710 in the second embodiment.

[0102] Furthermore, since the second salient feature of one of the second specific regions (i.e., the second region 743) in the reference chip 740 is also a right-slanted feature, the processor 204 can further estimate the fault pattern similarity between the first specific region (i.e., the first region 712) and the second specific region (i.e., the second region 743) of the reference chip 740, and then decide whether to provide the reference chip 740 as a search result for the target chip 710. Assuming that the fault pattern similarity between the first specific region (i.e., the first region 712) and the second specific region (i.e., the second region 743) of the reference chip 740 is higher than a similarity threshold, the processor 204 can provide the reference chip 740 as a search result for the target chip 710 in the second embodiment.

[0103] In summary, by representing each wafer die using normalized coordinates, the method of this invention can achieve cross-product comparison. Furthermore, compared to existing methods that only compare based on the failure rate in a specific region, this invention can more accurately identify reference wafers with similar failure patterns to the target wafer.

[0104] Furthermore, since the amount of data required for searching is far less than that of existing methods, the method of the present invention achieves significantly better search efficiency. For example, assuming there are 750 chips in the chip database, and each chip has 3000 dies, the existing method requires approximately 2,250,000 data points (i.e., 750 × 3000) for searching. However, the method of the present invention requires only 750 × m data points. Assuming the number of predefined distribution features considered is 4, the method of the present invention requires only about 3000 data points (i.e., 750 × 4), which is clearly far less than the amount of data required by existing methods.

[0105] Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A wafer search method, suitable for a wafer search device, the wafer search method comprising: Obtain a target wafer and a reference wafer, wherein the target wafer and the reference wafer are individually distributed with a plurality of faulty dies and a plurality of normal dies, and the target wafer is divided into a plurality of first regions, and the reference wafer is divided into a plurality of second regions corresponding to the first regions; In these first regions, a first specific region is determined, and the first significant distribution characteristics of the fault patterns of the faulty dies in the first specific region are obtained; In these second regions, at least one second specific region is determined, and the second significant distribution characteristics of the fault patterns of the faulty dies in each of the second specific regions are obtained; In response to determining that the first significant distribution feature corresponds to any of the second significant distribution features of the at least one second specific region, the similarity of the fault patterns between the first specific region and each of the second specific regions is estimated; In response to the determination that the similarity of the fault pattern is higher than a similarity threshold, a reference chip is provided as the search result corresponding to the target chip. The first significant distribution feature is one of a plurality of preset distribution features, including horizontal, vertical, right-angle, and left-angle features. The step of obtaining the first significant distribution feature of the fault pattern of the faulty dies in the first specific region includes: Based on convolution operations and multiple feature enhancement matrices, multiple first feature values ​​of the preset distribution features of the first specific region are estimated, each of the multiple first feature values ​​being associated with the number of faulty dies corresponding to one of the multiple preset distribution features and the proportion of first faulty dies in the first specific region.

2. The wafer searching method as described in claim 1, wherein the step of obtaining the target wafer includes: Obtain at least one selected chip, wherein each selected chip has a plurality of faulty dies and a plurality of normal dies distributed on it; In response to the determination that the location of the first specific region is limited to correspond to the location of the at least one second specific region, the faulty dies on the target wafer are determined based on the faulty dies on each of the selected wafers.

3. The wafer search method as described in claim 2, wherein the step of determining the faulty dies on the target wafer based on the faulty dies on each selected wafer includes: The reaction is to determine that each of the selected chips has a faulty die located at a specific location, and to determine that the target chip has a faulty die located at that specific location; In response to determining that any of the at least one selected wafer does not have a faulty die located at the specific location, the target wafer is determined not to have a faulty die located at the specific location.

4. The wafer searching method as described in claim 1, wherein the step of obtaining the target wafer includes: Obtain at least one selected chip, wherein each selected chip has a plurality of faulty dies and a plurality of normal dies distributed on it; In response to the determination that the location of the first specific region is not limited to the location corresponding to the location of the at least one second specific region, one of the at least one selected wafers is taken as the target wafer.

5. The wafer search method as described in claim 4, further comprising: In response to the determination that the similarity of the fault pattern is not higher than the similarity threshold, one of the at least one selected chips is taken as the target chip, and it is determined whether to take the reference chip as the search result corresponding to the target chip.

6. The wafer search method of claim 1, wherein the step of obtaining the first significant distribution feature of the fault pattern of the faulty dies in the first specific region further comprises: Among these first characteristic values, the first highest characteristic value is found, and among these preset distribution characteristics in the first specific region, one corresponding to the first highest characteristic value is selected as the first significant distribution characteristic.

7. The wafer search method of claim 6, wherein the first specific region is the i-th first region among the first regions, and the step of estimating the first feature values ​​of the preset distribution characteristics of the first specific region further includes: The proportion of first faulty dies in the first specific region is estimated based on the faulty dies and normal dies in the first specific region. The target wafer is characterized as a first die distribution matrix, wherein the element with a first value in the first die distribution matrix corresponds to one of the faulty dies of the target wafer, and the element with a second value in the first die distribution matrix corresponds to one of the normal dies of the target wafer; The first die distribution matrix is ​​convolved with the j-th feature enhancement matrix of the plurality of feature enhancement matrices to generate the j-th reference die distribution matrix among the plurality of reference die distribution matrices, wherein the j-th feature enhancement matrix corresponds to the j-th preset distribution feature among the preset distribution features; The j-th faulty die number is estimated from the elements with the first value in the j-th reference die distribution matrix, wherein the j-th faulty die number corresponds to the j-th preset distribution feature; Based on the number of the j-th faulty die and the proportion of the first faulty die in the first specific region, the j-th first feature value among the first feature values ​​of the first specific region is estimated, wherein the j-th first feature value corresponds to the j-th preset distribution feature.

8. The wafer search method of claim 6, wherein the target wafer is obtained from a wafer database, and the step of obtaining the first significant distribution feature of the fault patterns of the faulty dies in the first specific region further includes: Obtain multiple first feature values ​​of the preset distribution characteristics of the first specific region from the chip database; Among these first characteristic values, the first highest characteristic value is found, and among these preset distribution characteristics in the first specific region, one corresponding to the first highest characteristic value is selected as the first significant distribution characteristic.

9. The wafer search method of claim 1, wherein the step of determining the at least one second specific region in the second regions comprises: In response to the determination that the location of the first specific region is not limited to corresponding to the location of the at least one second specific region, the second regions are regarded as the at least one second specific region; In response to the determination that the location of the first specific region is limited to the location corresponding to the location of the at least one second specific region, the at least one second specific region is identified among the second regions that corresponds to the same location as the first specific region.

10. The wafer search method of claim 1, wherein the second significant distribution feature is one of a plurality of preset distribution features, and the step of obtaining the second significant distribution feature of the fault pattern of the faulty dies in the at least one second specific region includes: Estimate multiple second feature values ​​of the preset distribution characteristics of each of the second specific regions; Among these second characteristic values, the second highest characteristic value is found, and among the preset distribution characteristics of each second specific region, the one corresponding to the second highest characteristic value is selected as the second significant distribution characteristic.

11. The wafer search method of claim 1, wherein the reference wafer is taken from a wafer database, the second significant distribution feature is one of a plurality of preset distribution features, and the step of obtaining the second significant distribution feature of the fault patterns of the faulty dies in the at least one second specific region includes: Obtain multiple second feature values ​​of the preset distribution characteristics of each of the second specific regions from the chip database; Among these second characteristic values, the second highest characteristic value is found, and among the preset distribution characteristics of each second specific region, the one corresponding to the second highest characteristic value is selected as the second significant distribution characteristic.

12. The wafer search method of claim 1, wherein in response to determining that the first significant distribution feature and the second significant distribution feature of any of the at least one second specific region correspond to the same one of a plurality of preset distribution features, the first significant distribution feature corresponds to the second significant distribution feature of any of the at least one second specific region.

13. The wafer search method as claimed in claim 1, wherein the faulty dies and normal dies of the target wafer and the reference wafer each have normalized coordinates.

14. The wafer search method of claim 1, wherein the step of estimating the similarity of the fault pattern between the first specific region and each of the second specific regions includes: Estimate multiple first feature values ​​of multiple preset distribution characteristics of the first specific region; For the i-th second specific region in the at least one second specific region, estimate a plurality of second feature values ​​of the preset distribution characteristics of the i-th second specific region; as well as Based on the first feature values ​​of the first specific region, the second feature values ​​of the i-th second specific region, the number of preset distribution features, and correction parameters, the similarity of the fault pattern between the first specific region and the i-th second specific region is estimated.

15. The wafer search method as described in claim 1, further comprising: If the similarity of the fault pattern is determined to be less than the similarity threshold, the reference chip will not be provided as the search result corresponding to the target chip.

16. A chip searching device, comprising: Storage circuitry stores program code; as well as The processor, coupled to the storage circuit, accesses the program code for execution: Obtain a target wafer and a reference wafer, wherein the target wafer and the reference wafer are individually distributed with a plurality of faulty dies and a plurality of normal dies, and the target wafer is divided into a plurality of first regions, and the reference wafer is divided into a plurality of second regions corresponding to the first regions; In these first regions, a first specific region is determined, and the first significant distribution characteristics of the fault patterns of the faulty dies in the first specific region are obtained; In these second regions, at least one second specific region is determined, and the second significant distribution characteristics of the fault patterns of the faulty dies in each of the second specific regions are obtained; In response to determining that the first significant distribution feature corresponds to any of the second significant distribution features of the at least one second specific region, the similarity of the fault patterns between the first specific region and each of the second specific regions is estimated; In response to the determination that the similarity of the fault pattern is higher than a similarity threshold, a reference chip is provided as the search result corresponding to the target chip. The first significant distribution feature is one of a plurality of preset distribution features, including horizontal, vertical, right-angle, and left-angle features. The step of obtaining the first significant distribution feature of the fault pattern of the faulty dies in the first specific region includes: Based on convolution operations and multiple feature enhancement matrices, multiple first feature values ​​of the preset distribution features of the first specific region are estimated, each of the multiple first feature values ​​being associated with the number of faulty dies corresponding to one of the multiple preset distribution features and the proportion of first faulty dies in the first specific region.

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