Self-aligned dual-trench MOSFET structure and manufacturing method thereof

Abstract

The present invention discloses a self-aligned dual-trench MOSFET structure and its manufacturing method. After forming a first semiconductor layer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type on a substrate, different etching selectivities between first to fourth hard masks are utilized, combined with a sidewall process, to form an array of self-aligned gate trenches and source trenches in an alternating manner in the first semiconductor layer. The gate trenches include a gate oxide layer and a gate electrode, and the source trenches include a second semiconductor layer of the second conductivity type. Sidewall structures are formed on the first semiconductor layer between the gate and source trenches, and an adhesive layer is formed between the sidewalls. The present invention can save on photomasks, reduce device area, further reduce resistance, increase current flow and switching speed, and improve device performance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a self-aligned dual-groove MOSFET structure and a manufacturing method thereof. Background Art

[0002] Compared to planar MOSFETs, trench MOSFETs can provide a shorter current path between the source and the drain, thereby reducing the on-resistance and allowing more current to flow through the switch, thereby significantly reducing power loss. Reducing the spacing between structures in a MOSFET device allows the MOSFET device to have a smaller die area, which can further reduce the resistance per square area and increase the current density. However, as the device area continues to shrink, the number of processing steps and the number of masks in the manufacturing process also increase, which undoubtedly increases manufacturing costs. In addition, due to the existence of overlay errors, an increase in short-circuit resistance is also caused. Summary of the Invention

[0003] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and to provide a self-aligned dual-trench MOSFET structure and a manufacturing method thereof.

[0004] To achieve the above object, the technical solution of the present invention is as follows:

[0005] The present invention provides a self-aligned double-trench MOSFET structure, comprising:

[0006] a first semiconductor layer of a first conductivity type covering the upper surface of the substrate;

[0007] a source region layer of a first conductivity type formed in the first semiconductor layer and located within the upper surface of the first semiconductor layer, and a body region layer of a second conductivity type located below the source region layer;

[0008] an array of a plurality of gate trenches and source trenches formed in parallel and alternatingly into the first semiconductor layer from the upper surface of the first semiconductor layer, wherein a gate electrode and a gate oxide layer located between the gate electrode and an inner wall of the gate trench are formed in the gate trench, and a second semiconductor layer of a second conductivity type is formed in the source trench;

[0009] a plurality of spacer structures protruding from the upper surface of the first semiconductor layer and located between every two adjacent gate trenches and source trenches, and an adhesive layer formed between the spacers;

[0010] The source trench is formed between every two adjacent gate trenches in a self-aligned manner through the opening between every two adjacent sidewalls.

[0011] Furthermore, the bottom end of the gate trench is located in the first semiconductor layer below the body layer, and the bottom end of the source trench is flush with or not flush with the bottom end of the gate trench.

[0012] Furthermore, a top end of the gate protrudes above the upper surface of the first semiconductor layer and is located between the sidewalls.

[0013] Furthermore, the side wall includes a first side wall and a second side wall connected to each other; wherein, the first side wall is arranged adjacent to both sides of the gate trench, the second side wall is formed on the outside of the first side wall and is arranged adjacent to both sides of the source trench, and the horizontal width of the source region layer located between the source trench and the gate trench is determined by the horizontal width of the second side wall.

[0014] Furthermore, it also includes: a top metal layer covering the sidewalls and the upper surface of the adhesive layer.

[0015] The present invention also provides a method for manufacturing a self-aligned dual-trench MOSFET structure, comprising:

[0016] Providing a substrate, and forming a first semiconductor layer of a first conductivity type covering an upper surface of the substrate;

[0017] forming a source region layer of a first conductivity type located within an upper surface of the first semiconductor layer in the first semiconductor layer, and forming a body region layer of a second conductivity type located below the source region layer;

[0018] forming a plurality of first hard mask layer patterns on an upper surface of the first semiconductor layer;

[0019] Conformally forming a second hard mask layer on the first hard mask layer pattern, and performing back etching to form second hard mask layer patterns on both sides of the first hard mask layer pattern, and exposing the top of the first hard mask layer pattern and the upper surface of the first semiconductor layer between two adjacent second hard mask layer patterns;

[0020] forming a third hard mask layer on the exposed upper surface of the first semiconductor layer, and performing back etching to form a third hard mask layer pattern between two second hard mask layer patterns located on adjacent sides;

[0021] removing the second hard mask layer pattern, and then forming first spacer structures on both sides of the first hard mask layer pattern and on both sides of the third hard mask layer pattern;

[0022] Using the first sidewall spacer as a mask, forming a gate trench downward on the exposed upper surface of the first semiconductor layer, forming a gate oxide layer on the inner wall of the gate trench, and forming a gate in the gate trench within the gate oxide layer;

[0023] forming a fourth hard mask layer covering the gate trench, and performing back etching to form a fourth hard mask layer pattern between two first sidewall spacers located on adjacent sides;

[0024] removing the first hard mask layer pattern and the third hard mask layer pattern, then forming a source trench self-aligned between the gate trenches downward on the exposed upper surface of the first semiconductor layer, and forming a second semiconductor layer of a second conductivity type in the source trench;

[0025] The fourth hard mask layer pattern is removed, and an adhesive layer is formed between the first sidewalls to cover the exposed gate trench and the source trench.

[0026] Furthermore, the step of forming a gate trench downward on the exposed upper surface of the first semiconductor layer using the first sidewall as a mask, forming a gate oxide layer on an inner wall of the gate trench, and forming a gate in the gate trench within the gate oxide layer specifically includes:

[0027] Using the first spacers, the first hard mask layer pattern, and the third hard mask layer pattern as a common mask, etching downward to form a gate trench on the upper surface of the first semiconductor layer exposed between the first spacers, with the bottom end of the gate trench located in the first semiconductor layer below the body layer;

[0028] A gate oxide layer material is deposited on the inner wall of the gate trench, and a gate material is filled in the gate trench within the gate oxide layer. The gate material is etched back to form a gate oxide layer on the inner wall of the gate trench, and a gate is formed in the gate trench within the gate oxide layer, and the top of the gate protrudes above the upper surface of the first semiconductor layer and is located between the first sidewalls.

[0029] Furthermore, the removing of the first hard mask layer pattern and the third hard mask layer pattern, then forming a source trench self-aligned between the gate trenches downward on the exposed upper surface of the first semiconductor layer, and forming a second semiconductor layer of a second conductivity type in the source trench, specifically includes:

[0030] The first hard mask layer pattern and the third hard mask layer pattern are removed by etching back, and then, using the first spacer and the fourth hard mask layer pattern as a common mask, a source trench self-aligned between the gate trenches is formed downward on the upper surface of the first semiconductor layer exposed between the first spacers, with the bottom end of the source trench being flush with or not flush with the bottom end of the gate trench;

[0031] Then, the source trench is filled with a second semiconductor layer material and etched back to form a second semiconductor layer of a second conductivity type in the source trench, and the top of the second semiconductor layer is flush with the upper surface of the first semiconductor layer.

[0032] Furthermore, the removing of the first hard mask layer pattern and the third hard mask layer pattern, then forming a source trench self-aligned between the gate trenches downward on the exposed upper surface of the first semiconductor layer, and forming a second semiconductor layer of a second conductivity type in the source trench, specifically includes:

[0033] By back etching, the first hard mask layer pattern and the third hard mask layer pattern are removed, and a second spacer structure is formed on the outer side of the first spacer located on both sides of the fourth hard mask layer pattern;

[0034] Then, using the second spacer, the first spacer, and the fourth hard mask layer pattern as a common mask, a source trench self-aligned between the gate trenches is formed downward on the upper surface of the first semiconductor layer exposed between the second spacers, and the bottom end of the source trench is flush with or not flush with the bottom end of the gate trench;

[0035] Then, filling the source trench with a second semiconductor layer material and performing back etching to form a second semiconductor layer of a second conductivity type in the source trench, and making the top of the second semiconductor layer flush with the upper surface of the first semiconductor layer;

[0036] When forming the second sidewall spacer, the horizontal width of the second sidewall spacer is adjusted to adjust the horizontal width of the source region layer between the source trench and the gate trench.

[0037] Furthermore, the method further includes: forming a top metal layer covering the first sidewall spacer and the upper surface of the adhesive layer.

[0038] As can be seen from the above technical solution, the present invention forms a second hard mask layer conformally on the first hard mask layer pattern and forms the second hard mask layer pattern on both sides of the first hard mask layer pattern by back-etching, so that a third hard mask layer pattern can be self-aligned between the second hard mask layer patterns. While saving one mask, the pitch is reduced, so that the MOSFET device has a smaller tube core area, thereby further reducing the resistance per square area, increasing the current density, and significantly reducing the cost; at the same time, since there is no overlay error, the short-circuit resistance can be effectively reduced; in this way, by step-by-step removing the second hard mask layer pattern and the first hard mask layer pattern and the third hard mask layer pattern, the source trench can be accurately self-aligned between the gate trenches to effectively reduce the resistance and increase the switching speed; in addition, when forming the source trench, the second sidewall with adjustable width can be added outside the first sidewall to adjust the formation width of the source trench, so as to adjust the horizontal width of the source region layer located between the source trench and the gate trench, thereby further improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of a self-aligned dual-trench MOSFET structure according to a preferred embodiment of the present invention;

[0040] Figure 2 A flowchart of a method for manufacturing a self-aligned dual-trench MOSFET structure according to a preferred embodiment of the present invention;

[0041] Figure 3-Figure 7 A preferred embodiment of the present invention is based on Figure 2 Schematic diagram of the process steps for manufacturing a self-aligned dual-trench MOSFET structure using a method. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meanings understood by people with ordinary skills in the field to which the invention belongs. The words "including" and similar words used in this article mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0043] Unless otherwise specified below, the various parts of the MOSFET device can be made of materials known to those skilled in the art. Semiconductor materials can include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si, Ge, etc. The gate conductor can be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x , Ni3Si, Pt, Ru, W, and combinations of the aforementioned conductive materials. The gate dielectric can be made of SiO2 or a material having a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, titanates, and the like. Furthermore, the gate dielectric can be formed not only of materials known to those skilled in the art, but also of materials developed in the future for use as gate dielectrics.

[0044] The first conductivity type may be one of N-type and P-type, and the second conductivity type may be the other of N-type and P-type. N-type can be formed by implanting an N-type dopant (e.g., P, As, etc.) into a semiconductor material. P-type can be formed by implanting a P-type dopant (e.g., B, etc.) into a semiconductor material. The above description can be understood with reference to known techniques.

[0045] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0046] See also Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a self-aligned dual-trench MOSFET structure according to a preferred embodiment of the present invention. Figure 1 As shown, a self-aligned double-trench MOSFET structure of the present invention includes:

[0047] A first semiconductor layer 11 of a first conductivity type covering the upper surface of the substrate 10; a source region layer 14 of the first conductivity type formed in the first semiconductor layer 11 and located within the upper surface 111 of the first semiconductor layer 11, and a body region layer 13 of the second conductivity type located below the source region layer 14; an array of multiple gate trenches 12 and source trenches 20 formed in parallel from the upper surface 111 of the first semiconductor layer 11 and in an alternating manner, wherein a gate electrode 122 and a gate oxide layer 121 located between the gate electrode 122 and the inner wall of the gate trench 12 are formed in the gate trench 12, and a second semiconductor layer 201 of the second conductivity type is formed in the source trench 20; a plurality of sidewall structures 15 protruding from the upper surface 111 of the first semiconductor layer 11 and located between every two adjacent gate trenches 12 and source trenches 20, and an adhesive layer 19 formed between the sidewalls 15.

[0048] The source trench 20 is formed between every two adjacent gate trenches 12 in a self-aligned manner through the opening between every two adjacent sidewall spacers 15 .

[0049] See also Figure 1 In a preferred embodiment, the substrate 10 may be a silicon substrate 10 (N+ substrate) that is heavily doped with an N+ type of the first conductivity type, and a first semiconductor layer 11 of the first conductivity type that is lightly doped with an N- type is used on the silicon substrate 10. The first semiconductor layer 11 may be, for example, an epitaxial (EPI) single crystal silicon layer grown on the silicon substrate 10 and lightly doped with an N- type first semiconductor layer 11 (N-EPI).

[0050] The body layer 13 may be a P-type lightly doped second conductivity type body layer 13 (P-body) in the first semiconductor layer 11. The source layer 14 may be a N+ type heavily doped first conductivity type source layer 14 in the first semiconductor layer 11.

[0051] In a preferred embodiment, the gate 122 may be a heavily N+-doped polysilicon gate 122 of the first conductivity type (poly 1).

[0052] The second semiconductor layer 201 serves as a source contact conductor, and a second semiconductor layer 201 of the second conductivity type that is P-type doped may be used.

[0053] In a preferred embodiment, the second semiconductor layer 201 may be an epitaxial single crystal silicon layer grown in the source trench 20 and P-type doped, that is, the second semiconductor layer 201 may be a P-type doped epitaxial single crystal silicon layer (PEPI).

[0054] In a preferred embodiment, the adhesion layer 19 can be made of at least one material selected from the group consisting of Ti, TiN, and TaN.

[0055] The sidewall spacer 15 can be made of conventional materials used in the sidewall spacer process.

[0056] In a preferred embodiment, a top metal layer 18 is further covered on the upper surfaces of the sidewalls 15 and the adhesive layer 19. The top metal layer 18 can be made of, for example, W or Al.

[0057] In other preferred embodiments, structures such as an interlayer dielectric layer and a metal interconnection layer may be further disposed on the top metal layer 18 .

[0058] See also Figure 1 In a preferred embodiment, the bottom ends of the gate trench 12 and the source trench 20 are disposed in the first semiconductor layer 11 below the body layer 13. The bottom ends of the source trench 20 and the gate trench 12 may be flush with each other in the horizontal direction. Alternatively, the bottom ends of the source trench 20 and the gate trench 12 may not be flush with each other in the horizontal direction.

[0059] Furthermore, the bottom of the source trench 20 can be configured to extend into the substrate 10 of the first conductivity type. The gate 122 is isolated by a gate oxide layer 121, and the second semiconductor layer 201 of the second conductivity type, which serves as a source contact conductor, is connected to the substrate 10 to further reduce resistance. The above-described structure of the present invention can reduce device area, provide a shorter source-drain current path, further reduce resistance per square area, and increase current density, thereby reducing on-resistance, allowing more current to flow through the switch, and significantly reducing power loss.

[0060] In a preferred embodiment, a top end of the gate 122 may protrude above the upper surface 111 of the first semiconductor layer 11 and be located between the sidewalls 15 .

[0061] In a preferred embodiment, the spacer 15 may include a first spacer 16 and a second spacer 17 connected in a horizontal direction. The first spacer 16 is disposed adjacent to both sides of the gate trench 12; the second spacer 17 is located outside the first spacer 16 and adjacent to both sides of the source trench 20. Thus, the horizontal width of the source layer 14 between the source trench 20 and the gate trench 12 is determined by the horizontal width of the second spacer 17. Whether to include the second spacer 17 and its width can be determined based on design requirements.

[0062] The following describes in detail a method for manufacturing a self-aligned dual-trench MOSFET structure according to the present invention in conjunction with the accompanying drawings.

[0063] The present invention provides a method for manufacturing a self-aligned dual-groove MOSFET structure, which can be used to manufacture the above-mentioned Figure 1 A self-aligned double-trench MOSFET structure, the method may include the following steps:

[0064] Step S1: providing a substrate, and forming a first semiconductor layer of a first conductivity type covering an upper surface of the substrate.

[0065] See also Figure 3 In a preferred embodiment, a silicon substrate 10 of the first conductivity type that is heavily doped with N+ type may be used, and a first semiconductor layer 11 of the first conductivity type that is lightly doped with N- type may be used on the silicon substrate 10. The first semiconductor layer 11 may be, for example, an epitaxial single crystal silicon layer grown on the silicon substrate 10, and may be lightly doped with N- type by an ion implantation process.

[0066] Step S2: forming a source region layer of the first conductivity type located within the upper surface of the first semiconductor layer in the first semiconductor layer, and forming a body region layer of the second conductivity type located below the source region layer.

[0067] See also Figure 3 In a preferred embodiment, an ion implantation process may be used to perform light P-type doping into the first semiconductor layer 11 from the upper surface 111 of the first semiconductor layer 11 to form a body region layer 13 of the second conductivity type.

[0068] Next, an ion implantation process may be used to perform N+ type heavy doping into the first semiconductor layer 11 from the upper surface 111 of the first semiconductor layer 11 , thereby forming a first conductive type source layer 14 on the upper surface 111 of the first semiconductor layer 11 above the body layer 13 .

[0069] Step S3: forming a plurality of first hard mask layer patterns on the upper surface of the first semiconductor layer.

[0070] See also Figure 3 In a preferred embodiment, a first hard mask layer material is deposited entirely on the upper surface 111 of the first semiconductor layer 11. A photoresist layer is then formed on the first hard mask layer. Subsequently, a plurality of first hard mask layer patterns 21 (HM1) are formed on the upper surface 111 of the first semiconductor layer 11 through photolithography and etching. Thereafter, any remaining photoresist on the first hard mask layer patterns 21 is removed.

[0071] The first hard mask layer may be made of conventional hard mask layer materials, for example, one or more of silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.

[0072] Step S4: Conformally forming a second hard mask layer on the first hard mask layer pattern, and performing back etching to form a second hard mask layer pattern on both sides of the first hard mask layer pattern, and exposing the top of the first hard mask layer pattern and the upper surface of the first semiconductor layer between the two second hard mask layer patterns on adjacent sides.

[0073] See also Figure 4 In a preferred embodiment, a conformal CVD process can be used to conformally deposit a second hard mask layer material on the first hard mask layer patterns 21 and on the exposed upper surface 111 of the first semiconductor layer 11. The second hard mask layer is then etched back to form second hard mask layer patterns 22 (HM2) on both sides of each first hard mask layer pattern 21, exposing the top of the first hard mask layer pattern 21 and two second hard mask layer patterns 22 located on adjacent sides, i.e., the upper surface 111 of the first semiconductor layer 11 located between the two second hard mask layer patterns 22 located inside the two adjacent first hard mask layer patterns 21.

[0074] When depositing the second hard mask layer, the thickness during deposition can be controlled to reserve a width for subsequent deposition of the third hard mask layer.

[0075] The second hard mask layer may be made of conventional hard mask layer materials, for example, one or more of silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.

[0076] Step S5: forming a third hard mask layer on the exposed upper surface of the first semiconductor layer, and performing back etching to form a third hard mask layer pattern between two second hard mask layer patterns located on adjacent sides.

[0077] See also Figure 4 In a preferred embodiment, conventional processes can be used to deposit a third hard mask layer material on the entire surface 111 of the exposed first semiconductor layer 11 between two adjacent second hard mask layer patterns 22, completely filling the gap between the two adjacent second hard mask layer patterns 22 to form a third hard mask layer covering the first hard mask layer patterns 21, the second hard mask layer patterns 22, and the upper surface 111 of the first semiconductor layer 11. The third hard mask layer material can then be back-etched to form a third hard mask layer pattern 23 (HM3) between the two adjacent second hard mask layer patterns 22. By conformally forming the second hard mask layer on the first hard mask layer patterns 21 and back-etching to form the second hard mask layer patterns 22 on both sides of the first hard mask layer patterns 21, the third hard mask layer patterns 23 can be self-aligned between the second hard mask layer patterns 22, thereby achieving a reduced pitch while saving one photomask.

[0078] The third hard mask layer may be made of a conventional hard mask layer material, for example, one or more of silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.

[0079] Step S6: removing the second hard mask layer pattern, and then forming first spacer structures on both sides of the first hard mask layer pattern and on both sides of the third hard mask layer pattern respectively.

[0080] See also Figure 5 In a preferred embodiment, different etching selectivities between the second hard mask layer material and the first and third hard mask layer materials can be utilized to remove the second hard mask layer pattern 22 located between the first hard mask layer pattern 21 and the third hard mask layer pattern 23, thereby exposing the upper surface 111 of the first semiconductor layer 11 located between the first hard mask layer pattern 21 and the third hard mask layer pattern 23.

[0081] Then, a sidewall process can be used to fully deposit sidewall material on the first hard mask layer pattern 21, the third hard mask layer pattern 23 and the upper surface 111 of the exposed first semiconductor layer 11, and then back-etching is performed to form first sidewall 16 structures on both sides of each first hard mask layer pattern 21 and each third hard mask layer pattern 23.

[0082] When forming the first sidewall spacer 16, the horizontal width of the first sidewall spacer 16 formed by back etching can be adjusted by controlling the deposition thickness of the first sidewall spacer material, so as to adjust the spacing between the two first sidewall spacers 16 located inside two adjacent first hard mask layer patterns 21 and third hard mask layer patterns 23, thereby achieving adjustment of the horizontal width of the gate trench 12 formed by subsequent etching.

[0083] The material of the spacer 15 can be a conventional spacer material having different etching selectivities with the material of the first hard mask layer and the material of the third hard mask layer.

[0084] Step S7: using the first sidewall spacer as a mask, forming a gate trench downwardly on the exposed upper surface of the first semiconductor layer, forming a gate oxide layer on the inner wall of the gate trench, and forming a gate in the gate trench within the gate oxide layer.

[0085] See also Figure 5 In a preferred embodiment, after forming the first spacer 16, the first spacer 16 can be used as a mask. That is, the combined pattern of the first spacer 16 and the first hard mask layer pattern 21, and the combined pattern of the first spacer 16 and the third hard mask layer pattern 23 can be used as a common mask to etch downward on the upper surface 111 of the first semiconductor layer 11 exposed between every two adjacent first spacers 16. This forms a plurality of parallel deep trenches serving as gate trenches 12 in the first semiconductor layer 11, with the bottom ends of the gate trenches 12 located in the first semiconductor layer 11 below the body layer 13.

[0086] Then, a gate oxide layer material is fully deposited on the inner wall surface of the gate trench 12 and on the surface of the first sidewall 16 and the first hard mask layer pattern 21 and the third hard mask layer pattern 23, and the gate material is further filled in the gate trench 12 within the gate oxide layer material until the gap between the first sidewalls 16 is filled, so that the gate material covers the gate oxide layer material.

[0087] Next, the gate material may be etched back to form a gate oxide layer 121 on the inner wall of the gate trench 12 , and a gate 122 (poly 1) may be formed in the gate trench 12 within the gate oxide layer 121 .

[0088] When etching back the gate material, the etching back time can be controlled so that the top of the gate 122 and the gate oxide layer 121 protrude above the upper surface 111 of the first semiconductor layer 11 and are located between the first spacers 16, that is, the top of the gate 122 and the gate oxide layer 121 are located below the upper end of the first spacer 16. For example, the top of the gate 122 and the gate oxide layer 121 can be located at the middle of the height of the first spacer 16, but the present invention is not limited thereto.

[0089] The gate 122 may be made of, for example, N+ heavily doped polysilicon.

[0090] Step S8: forming a fourth hard mask layer covering the gate trench, and performing back etching to form a fourth hard mask layer pattern between two first spacers located on adjacent sides.

[0091] See also Figure 6 In a preferred embodiment, a fourth hard mask layer material is deposited on the surface of the device structure formed in the previous step to fill the gap between two adjacent first spacers 16 above the gate trench 12, thereby completely covering the gate electrode 122 and the top of the gate oxide layer 121 exposed in the gate trench 12.

[0092] Then, the fourth hard mask layer material is etched back to form a fourth hard mask layer pattern 24 (HM4) between two adjacent first spacers 16, that is, between two first spacers 16 located inside two adjacent first hard mask layer patterns 21 and third hard mask layer patterns 23.

[0093] The fourth hard mask layer may be made of TEOS oxide (tetraethoxysilane oxide).

[0094] Step S9: removing the first hard mask layer pattern and the third hard mask layer pattern, and then forming a source trench self-aligned between the gate trenches on the upper surface of the exposed first semiconductor layer, and forming a second semiconductor layer of the second conductivity type in the source trench.

[0095] See also Figure 7In a preferred embodiment, the first hard mask layer pattern 21 and the third hard mask layer pattern 23 can be removed by etching back using different etching selectivities between the first hard mask layer material and the third hard mask layer material and the first spacer 16 and the fourth hard mask layer material.

[0096] Then, a spacer process can be used to further form a second spacer 17 structure on the outer sides of the two first spacers 16 located on both sides of each fourth hard mask layer pattern 24, that is, on both sides of each gate trench 12. The first spacer 16 and the second spacer 17 together form the spacer 15 structure.

[0097] Next, using the second sidewall 17, the first sidewall 16 and the fourth hard mask layer pattern 24 as a common mask, a plurality of deep trenches self-aligned between the gate trenches 12 are formed downward on the upper surface 111 of the first semiconductor layer 11 exposed between every two adjacent second sidewalls 17 to form source trenches 20, and the bottom ends of the source trenches 20 are made flush or not flush with the bottom ends of the gate trenches 12.

[0098] Furthermore, the bottom end of the source trench 20 may also extend into the substrate 10 having the first conductivity type.

[0099] Afterwards, the source trench 20 is filled with a second semiconductor layer material. Next, the second semiconductor layer material is etched back to form a second semiconductor layer 201 in the source trench 20, and the top of the second semiconductor layer 201 is flush or substantially flush with the upper surface 111 of the first semiconductor layer 11.

[0100] In a preferred embodiment, the second semiconductor layer 201 can be filled by growing an epitaxial single crystal silicon layer in the source trench 20 and performing P-type doping to have the second conductivity type.

[0101] After forming a first semiconductor layer 11 of the first conductivity type, a body layer 13 of the second conductivity type, and a source layer 14 of the first conductivity type, the present invention utilizes different etching selectivities between the first hard mask to the fourth hard mask, combined with a spacer process, to achieve the alternating formation of a self-aligned array of multiple gate trenches 12 and source trenches 20 in the first semiconductor layer 11. This invention not only saves on masks and reduces processing steps in the manufacturing process, significantly lowering manufacturing costs, but also reduces device area and eliminates overlay errors, thereby reducing on-resistance, allowing more current to flow through the switch, and significantly reducing power loss.

[0102] When forming the second sidewall spacer 17, the deposition thickness of the second sidewall spacer material is controlled to adjust the horizontal width of the second sidewall spacer 17 formed by back-etching, thereby adjusting the spacing between the two second sidewall spacers 17 located inside two adjacent first sidewall spacers 16, thereby adjusting the horizontal width of the source layer 14 located between the source trench 20 and the gate trench 12. At the same time, fine-tuning of the device area can also be achieved.

[0103] As another specific embodiment, depending on design requirements, the step of forming the second spacer 17 can be omitted, and only the width of the first spacer 16 can be adjusted as a means of adjusting the device structure. In this case, after removing the first hard mask layer pattern 21 and the third hard mask layer pattern 23, the first spacer 16 and the fourth hard mask layer pattern 24 are used as a common mask to form a source trench 20 self-aligned between the gate trenches 12 on the upper surface 111 of the first semiconductor layer 11 exposed between the first spacers 16.

[0104] Step S10: removing the fourth hard mask layer pattern, forming an adhesive layer between the first spacers on the exposed gate trenches and source trenches, and forming a top metal layer covering the first spacers and the upper surface of the adhesive layer.

[0105] See also Figure 7 In a preferred embodiment, the fourth hard mask layer pattern 24 can be removed by etching back to expose the top of the gate 122 by utilizing different etching selectivities between the fourth hard mask layer material and the first spacer material and the second spacer material.

[0106] See also Figure 1 Then, an adhesive layer material is deposited on the surface of the device structure formed above to fill the gaps between the second sidewalls 17 , and then etched back to form an adhesive layer 19 between the first sidewalls 16 on the exposed gate electrode 122 of the gate trench 12 and the conductive second semiconductor layer 201 of the source trench 20 .

[0107] The adhesive layer 19 located above the gate trench 12 is in direct contact with the first spacer 16 , and the adhesive layer 19 located above the source trench 20 is in direct contact with the second spacer 17 .

[0108] The adhesive layer 19 may be made of at least one material selected from the group consisting of Ti, TiN, and TaN.

[0109] Next, a metal material may be deposited on the surface of the device structure to form a top metal layer 18 covering the first sidewall spacer 16 (sidewall spacer 15 ) and the upper surface of the adhesive layer 19 , and then patterned.

[0110] The top metal layer 18 can be made of metal such as W or Al.

[0111] Afterwards, a process of forming structures such as an interlayer dielectric layer and a metal interconnection layer may be continued on the top metal layer 18 .

[0112] In summary, the present invention forms a second hard mask layer conformally on the first hard mask layer pattern 21, and forms a second hard mask layer pattern 22 on both sides of the first hard mask layer pattern 21 by back etching, and can form a third hard mask layer pattern 23 by self-alignment between the second hard mask layer patterns 22. While saving a mask, the pitch is reduced, so that the MOSFET device has a smaller die area, thereby further reducing the resistance per square area, increasing the current density, and bringing about a significant reduction in cost; at the same time, since there is no overlay error, it can effectively Reduce short-circuit resistance; in this way, by step-by-step removing the second hard mask layer pattern 22 and the first hard mask layer pattern 21 and the third hard mask layer pattern 23, the source trench 20 can be accurately self-aligned and formed between the gate trenches 12, which can effectively reduce resistance and increase switching speed; in addition, when forming the source trench 20, the second sidewall 17 with adjustable width can be added outside the first sidewall 16 to adjust the formation width of the source trench 20, so as to adjust the horizontal width of the source region layer 14 located between the source trench 20 and the gate trench 12, thereby further improving device performance.

[0113] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations of these embodiments are possible. However, it should be understood that such modifications and variations are within the scope and spirit of the invention as defined in the appended claims. Furthermore, the invention described herein is susceptible to other embodiments and may be practiced or implemented in a variety of ways.

Claims

1. A method for manufacturing a self-aligned dual-trench MOSFET structure, characterized in that: include: Providing a substrate, and forming a first semiconductor layer of a first conductivity type covering an upper surface of the substrate; forming a source region layer of a first conductivity type located within an upper surface of the first semiconductor layer in the first semiconductor layer, and forming a body region layer of a second conductivity type located below the source region layer; forming a plurality of first hard mask layer patterns on an upper surface of the first semiconductor layer; Conformally forming a second hard mask layer on the first hard mask layer pattern, and performing back etching to form second hard mask layer patterns on both sides of the first hard mask layer pattern, and exposing the top of the first hard mask layer pattern and the upper surface of the first semiconductor layer between two adjacent second hard mask layer patterns; forming a third hard mask layer on the exposed upper surface of the first semiconductor layer, and performing back etching to form a third hard mask layer pattern between two second hard mask layer patterns located on adjacent sides; removing the second hard mask layer pattern, and then forming first spacer structures on both sides of the first hard mask layer pattern and on both sides of the third hard mask layer pattern; Using the first sidewall spacer as a mask, forming a gate trench downward on the exposed upper surface of the first semiconductor layer, forming a gate oxide layer on the inner wall of the gate trench, and forming a gate in the gate trench within the gate oxide layer; forming a fourth hard mask layer covering the gate trench, and performing back etching to form a fourth hard mask layer pattern between two first sidewall spacers located on adjacent sides; removing the first hard mask layer pattern and the third hard mask layer pattern, then forming a source trench self-aligned between the gate trenches downward on the exposed upper surface of the first semiconductor layer, and forming a second semiconductor layer of a second conductivity type in the source trench; The fourth hard mask layer pattern is removed, and an adhesive layer is formed between the first sidewalls to cover the exposed gate trench and the source trench.

2. The method for manufacturing a self-aligned double trench MOSFET structure according to claim 1, wherein: The method of forming a gate trench downward on the exposed upper surface of the first semiconductor layer using the first sidewall as a mask, forming a gate oxide layer on the inner wall of the gate trench, and forming a gate in the gate trench within the gate oxide layer specifically includes: Using the first spacers, the first hard mask layer pattern, and the third hard mask layer pattern as a common mask, etching downward to form a gate trench on the upper surface of the first semiconductor layer exposed between the first spacers, with the bottom end of the gate trench located in the first semiconductor layer below the body layer; A gate oxide layer material is deposited on the inner wall of the gate trench, and a gate material is filled in the gate trench within the gate oxide layer. The gate material is etched back to form a gate oxide layer on the inner wall of the gate trench, and a gate is formed in the gate trench within the gate oxide layer, and the top of the gate protrudes above the upper surface of the first semiconductor layer and is located between the first sidewalls.

3. The method for manufacturing a self-aligned double trench MOSFET structure according to claim 1, wherein: The removing of the first hard mask layer pattern and the third hard mask layer pattern, then forming a source trench self-aligned between the gate trenches downward on the exposed upper surface of the first semiconductor layer, and forming a second semiconductor layer of a second conductivity type in the source trench, specifically includes: The first hard mask layer pattern and the third hard mask layer pattern are removed by etching back, and then, using the first spacer and the fourth hard mask layer pattern as a common mask, a source trench self-aligned between the gate trenches is formed downward on the upper surface of the first semiconductor layer exposed between the first spacers, with the bottom end of the source trench being flush with or not flush with the bottom end of the gate trench; Then, the source trench is filled with a second semiconductor layer material and etched back to form a second semiconductor layer of a second conductivity type in the source trench, and the top of the second semiconductor layer is flush with the upper surface of the first semiconductor layer.

4. The method for manufacturing a self-aligned double trench MOSFET structure according to claim 1, wherein: The removing of the first hard mask layer pattern and the third hard mask layer pattern, then forming a source trench self-aligned between the gate trenches downward on the exposed upper surface of the first semiconductor layer, and forming a second semiconductor layer of a second conductivity type in the source trench, specifically includes: By back etching, the first hard mask layer pattern and the third hard mask layer pattern are removed, and a second spacer structure is formed on the outer side of the first spacer located on both sides of the fourth hard mask layer pattern; Then, using the second spacer, the first spacer, and the fourth hard mask layer pattern as a common mask, a source trench self-aligned between the gate trenches is formed downward on the upper surface of the first semiconductor layer exposed between the second spacers, and the bottom end of the source trench is flush with or not flush with the bottom end of the gate trench; Then, filling the source trench with a second semiconductor layer material and performing back etching to form a second semiconductor layer of a second conductivity type in the source trench, and making the top of the second semiconductor layer flush with the upper surface of the first semiconductor layer; When forming the second sidewall spacer, the horizontal width of the second sidewall spacer is adjusted to adjust the horizontal width of the source region layer between the source trench and the gate trench.

5. The method for manufacturing a self-aligned double trench MOSFET structure according to claim 1, wherein: Also includes: A top metal layer is formed covering the first sidewall spacer and the upper surface of the adhesive layer.

6. A self-aligned double-trench MOSFET structure, characterized in that: The MOSFET structure is manufactured according to the manufacturing method of any one of claims 1 to 5, and comprises: a first semiconductor layer of a first conductivity type covering the upper surface of the substrate; a source region layer of a first conductivity type formed in the first semiconductor layer and located within the upper surface of the first semiconductor layer, and a body region layer of a second conductivity type located below the source region layer; an array of a plurality of gate trenches and source trenches formed in parallel and alternatingly into the first semiconductor layer from the upper surface of the first semiconductor layer, wherein a gate electrode and a gate oxide layer located between the gate electrode and an inner wall of the gate trench are formed in the gate trench, and a second semiconductor layer of a second conductivity type is formed in the source trench; a plurality of spacer structures protruding from the upper surface of the first semiconductor layer and located between every two adjacent gate trenches and source trenches, and an adhesive layer formed between the spacers; The source trench is formed between every two adjacent gate trenches in a self-aligned manner through the opening between every two adjacent sidewalls.

7. The self-aligned double trench MOSFET structure according to claim 6, wherein: The bottom end of the gate trench is located in the first semiconductor layer below the body layer, and the bottom end of the source trench is flush with or not flush with the bottom end of the gate trench.

8. The self-aligned double trench MOSFET structure according to claim 6, wherein: The top of the gate protrudes from the upper surface of the first semiconductor layer and is located between the sidewalls.

9. The self-aligned double trench MOSFET structure according to claim 6, wherein: The sidewalls include a first sidewall and a second sidewall connected to each other; wherein, the first sidewalls are arranged adjacent to both sides of the gate trench, the second sidewalls are formed on the outside of the first sidewalls and are arranged adjacent to both sides of the source trench, and the horizontal width of the source region layer located between the source trench and the gate trench is determined by the horizontal width of the second sidewalls.

10. The self-aligned double trench MOSFET structure according to claim 6, wherein: Also includes: A top metal layer covers the sidewalls and the upper surface of the adhesive layer.

Images