A calibration circuit and method thereof

Abstract

The present invention provides a correction circuit and a method thereof, which are used for a Boost dual-output circuit. The correction circuit includes a detection circuit and a control circuit. The detection circuit is configured to compare the main output signal with a first threshold signal and a second threshold signal, and compare the secondary output signal with a third threshold signal and a fourth threshold signal, where the first threshold signal is less than the second threshold signal, and the third threshold signal is less than the fourth threshold signal. The control circuit controls the conduction time of the Boost dual-output circuit according to the comparison result of the detection circuit, and outputs control signals for extending, maintaining, and shortening the conduction time of the Boost dual-output circuit respectively according to different comparison results, so as to stabilize the proportional relationship between the main output signal and the secondary output signal. The correction circuit and the method thereof provided by the present invention stabilize the proportional relationship between the main output signal and the secondary output signal under different loads, thereby realizing the adaptive and stable operation of the Boost dual-output circuit.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular but not limited to a correction circuit and a method thereof. Background Art

[0002] Figure 1 A Boost dual-output circuit is shown. When the switching transistor Q is turned on, the primary voltage of the transformer Tr is V, and the secondary voltage of Tr is Vin / N. At this time, the secondary current passes through the diode Df, and the leakage inductance Lm quickly charges the capacitor Cc to Vin / N. When the switching transistor Q is turned off, the primary voltage of the transformer Tr is Vo - Vin, and the secondary voltage of the transformer Tr is (Vo - Vin) / N. At this time, the diode Df is cut off, and the diode Dc is turned on. The capacitor Cvdd is charged by the secondary side of the transformer and the capacitor Cc, and the voltage on the capacitor Cvdd is (Vo - Vin) / N + Vin / N = Vo / N. This circuit can achieve the stability of the voltage Vdd of the capacitor Cvdd under different input conditions.

[0003] When the loads of the main output Vo and the auxiliary output Vdd are matched, the proportionality of the two output voltages can be ensured. If the loads of the two outputs are not matched, the voltage out of control will occur. As Figure 2 shown, when the load of the Vdd path decreases, the energy on the capacitor Cc cannot be released in time, resulting in the voltage on the capacitor Cc not being proportional to Vin, and the average voltage Vc increases. Finally, the result of the superposition with the secondary side of the transformer Tr is that Vdd is greater than Vo / N. Moreover, when the load of the Vdd path is heavy, when the switching transistor is turned off, the primary side of the transformer Tr is clamped by the secondary side, resulting in a low drain voltage of the switching transistor Q, and the diode Do does not turn on, which will also cause the disproportion of Vdd and Vo and the out-of-control voltage.

[0004] In view of this, a new structure or control method is needed to solve at least some of the above problems. Summary of the Invention

[0005] At least aiming at one or more problems in the background art, the present invention provides a correction circuit and a method thereof, which can shorten the conduction time of the Boost dual-output circuit and release the energy on the capacitor Cc in time when the load of the Vdd path of the Boost dual-output circuit decreases; when the load of the Vdd path is heavy, extend the conduction time of the Boost dual-output circuit and increase the drain voltage of the switching transistor Q.

[0006] According to a first aspect of the present invention, a correction circuit is applied to a Boost dual-output circuit. The Boost dual-output circuit has two operating modes: a non-standby mode and a standby mode. The correction circuit is characterized in that it includes:

[0007] A detection circuit, whose input terminals are respectively coupled to the main output signal and the secondary output signal of the Boost dual-output circuit, is configured to compare the sampled main output signal with a first threshold signal and a second threshold signal, and compare the sampled secondary output signal with a third threshold signal and a fourth threshold signal, wherein the first threshold signal is less than the second threshold signal, and the third threshold signal is less than the fourth threshold signal;

[0008] A control circuit, whose input terminal is coupled to the output terminal of the detection circuit, is configured to output a control signal for extending the conduction time of the Boost dual-output circuit when the main output signal is less than the first threshold signal or the secondary output signal is less than the third threshold signal; in a non-standby mode, when the main output signal is greater than the first threshold signal and less than the second threshold signal, and in a standby mode, when the secondary output signal is greater than the third threshold signal and less than the fourth threshold signal, output a control signal for maintaining the conduction time of the Boost dual-output circuit; in a non-standby mode, when the main output signal is greater than the second threshold signal, and in a standby mode, when the secondary output signal is greater than the fourth threshold signal, output a control signal for shortening the conduction time of the Boost dual-output circuit.

[0009] Optionally, the detection circuit includes: a main output signal detection circuit, including a first comparator, a second comparator, and a first decoder, where the first comparator is configured to compare the main output signal and the first threshold signal, the second comparator is configured to compare the main output signal and the second threshold signal, and the first decoder is configured to translate the comparison results of the first comparator and the second comparator into a first detection signal, so that the control circuit outputs a control signal for controlling the conduction time of the Boost dual-output circuit according to the first detection signal; a secondary output signal detection circuit, including a third comparator, a fourth comparator, and a second decoder, where the first comparator is configured to compare the secondary output signal and the third threshold signal, the fourth comparator is configured to compare the secondary output signal and the fourth threshold signal, and the second decoder is configured to translate the comparison results of the third comparator and the fourth comparator into a second detection signal, so that the control circuit outputs a control signal for controlling the conduction time of the Boost dual-output circuit according to the second detection signal.

[0010] Optionally, the first detection signal includes a first low signal, a first medium signal, and a first high signal; the second detection signal includes a second low signal, a second medium signal, and a second high signal.

[0011] Optionally, the control circuit includes: a first AND gate, whose input terminals are respectively coupled to the receiver signal and the second medium signal; a second AND gate, whose input terminals are respectively coupled to the receiver signal and the second high signal; a first OR gate, whose input terminals are respectively coupled to the output terminal of the first AND gate and the first medium signal; a second OR gate, whose input terminals are respectively coupled to the output terminal of the second AND gate and the first high signal; a third OR gate, whose input terminals are respectively coupled to the first low signal and the second low signal, and whose output terminal outputs a control signal for extending the conduction time of the Boost dual-output circuit; a first NOT gate, whose input terminal is coupled to the second low signal; a third AND gate, whose input terminals are respectively coupled to the output terminal of the first OR gate and the output terminal of the first NOT gate, and whose output terminal outputs a control signal for maintaining the conduction time of the Boost dual-output circuit; a fourth AND gate, whose input terminals are respectively coupled to the output terminal of the second OR gate and the output terminal of the first NOT gate, and whose output terminal outputs a control signal for shortening the conduction time of the Boost dual-output circuit.

[0012] Optionally, the control circuit includes: a second NOT gate, whose input terminal is coupled to the receiver signal; a first AND gate, whose input terminals are respectively coupled to the output terminal of the second NOT gate and the first medium signal; a second AND gate, whose input terminals are respectively coupled to the receiver signal and the second medium signal; a second NOT gate, whose input terminal is coupled to the receiver signal; a third AND gate, whose input terminals are respectively coupled to the output terminal of the second NOT gate and the first high signal; a fourth AND gate, whose input terminals are respectively coupled to the receiver signal and the second high signal; a first OR gate, whose input terminals are respectively coupled to the output terminal of the first AND gate and the output terminal of the second AND gate; a second OR gate, whose input terminals are respectively coupled to the output terminal of the third AND gate and the output terminal of the fourth AND gate; a third OR gate, whose input terminals are respectively coupled to the first low signal and the second low signal, and whose output terminal outputs a control signal for extending the conduction time of the Boost dual-output circuit; a third NOT gate, whose input terminal is coupled to the second low signal; a fifth AND gate, whose input terminals are respectively coupled to the output terminal of the first OR gate and the output terminal of the third NOT gate, and whose output terminal outputs a control signal for maintaining the conduction time of the Boost dual-output circuit; a sixth AND gate, whose input terminals are respectively coupled to the output terminal of the second OR gate and the output terminal of the third NOT gate, and whose output terminal outputs a control signal for shortening the conduction time of the Boost dual-output circuit.

[0013] According to a second aspect of the present invention, a correction circuit is applied to a Boost dual-output circuit, and the correction circuit includes:

[0014] A detection circuit, whose input ends are respectively coupled to the main output signal and the secondary output signal of the Boost dual-output circuit, is used to compare the sampled main output signal with a first threshold signal and a second threshold signal, and to compare the sampled secondary output signal with a third threshold signal and a fourth threshold signal, where the first threshold signal is less than the second threshold signal, and the third threshold signal is less than the fourth threshold signal;

[0015] A control circuit, whose input end is coupled to the output end of the detection circuit, is used to output a control signal for extending the conduction time of the Boost dual-output circuit when the main output signal is less than the first threshold signal or the secondary output signal is less than the third threshold signal; to output a control signal for maintaining the conduction time of the Boost dual-output circuit when the secondary output signal is greater than the third threshold signal, the main output signal is greater than the first threshold signal and the main output signal is less than the second threshold signal, and when the main output signal is greater than the first threshold signal, the secondary output signal is greater than the third threshold signal and the secondary output signal is less than the fourth threshold signal; and to output a control signal for shortening the conduction time of the Boost dual-output circuit when the main output signal is greater than the second threshold signal and the secondary output signal is greater than the fourth threshold signal.

[0016] Optionally, the detection circuit is further used to output a first detection signal and a second detection signal, where the first detection signal includes a first low signal, a first medium signal, and a first high signal, and the second detection signal includes a second low signal, a second medium signal, and a second high signal.

[0017] Optionally, the control circuit includes: a third one-or gate, whose input ends are respectively coupled to the first low signal and the second low signal, and whose output end outputs a control signal for extending the conduction time of the Boost dual-output circuit; a third two-or gate, whose input ends are respectively coupled to the first medium signal and the second medium signal; a third three-or gate, whose input ends are respectively coupled to the first high signal and the second high signal; a third one-inverter gate, whose input end is coupled to the output end of the third one-or gate; a third one-and gate, whose input ends are respectively coupled to the output end of the third one-inverter gate and the output end of the third two-or gate, and whose output end outputs a control signal for maintaining the conduction time of the Boost dual-output circuit; a third two-inverter gate, whose input end is coupled to the output end of the third two-or gate; a third two-and gate, having three input ends, whose input ends are respectively coupled to the output end of the third one-inverter gate, the output end of the third two-inverter gate, and the output end of the third two-or gate, and whose output end outputs a control signal for shortening the conduction time of the Boost dual-output circuit.

[0018] According to a third aspect of the present invention, a calibration circuit is applied to a multi-output circuit, and the calibration circuit includes:

[0019] A detection circuit, whose input terminals are respectively coupled to multiple output signals of the multi-output circuit, is configured to compare each sampled output signal with corresponding first threshold signal and second threshold signal, wherein the first threshold signal is less than the second threshold signal;

[0020] A control circuit, whose input terminal is coupled to the output terminal of the detection circuit, is configured to output a control signal for extending the conduction time of the multi-output circuit when any of the output signals is less than the corresponding first threshold signal; output a control signal for maintaining the conduction time of the multi-output circuit when all the output signals are greater than the corresponding first threshold signal and any of the output signals is less than the corresponding second threshold signal; and output a control signal for shortening the conduction time of the multi-output circuit when all the output signals are greater than the corresponding second threshold signal.

[0021] According to the fourth aspect of the present invention, a calibration method is applied to a Boost dual-output circuit, which has two operating modes: a non-standby mode and a standby mode, and includes the following steps:

[0022] Sample the main output signal and the secondary output signal of the Boost dual-output circuit, and compare the sampled main output signal with a first threshold signal and a second threshold signal, and compare the sampled secondary output signal with a third threshold signal and a fourth threshold signal, wherein the first threshold signal is less than the second threshold signal, and the third threshold signal is less than the fourth threshold signal;

[0023] Output a control signal for extending the conduction time of the Boost dual-output circuit when the main output signal is less than the first threshold signal or the secondary output signal is less than the third threshold signal; output a control signal for maintaining the conduction time of the Boost dual-output circuit when, in the non-standby mode, the main output signal is greater than the first threshold signal and less than the second threshold signal, and when, in the standby mode, the secondary output signal is greater than the third threshold signal and less than the fourth threshold signal; output a control signal for shortening the conduction time of the Boost dual-output circuit when, in the non-standby mode, the main output signal is greater than the second threshold signal, and when, in the standby mode, the secondary output signal is greater than the fourth threshold signal.

[0024] The present invention provides a calibration circuit and a method therefor. The calibration circuit includes a detection circuit and a control circuit. The detection circuit is coupled to the main output signal and the secondary output signal of the Boost dual-output circuit, and is configured to compare the main output signal with a first threshold signal and a second threshold signal, and compare the secondary output signal with a third threshold signal and a fourth threshold signal, where the first threshold signal is less than the second threshold signal, and the third threshold signal is less than the fourth threshold signal. The control signal is coupled to the detection circuit and controls the conduction time of the Boost dual-output circuit according to the comparison result of the detection circuit. If the main output signal is less than the first threshold or the secondary output signal is less than the third threshold, it indicates that the load of the Boost dual-output circuit is relatively heavy at this time. The control circuit outputs a control signal to extend the conduction time of the Boost dual-output circuit, so that the conduction time increases, the drain voltage of the switching transistor Q increases, ensuring the conduction of the diode Do and maintaining the proportional relationship between Vo and Vdd. If the main output signal is between the first threshold signal and the second threshold signal or the secondary output signal is between the third threshold signal and the fourth threshold signal, it indicates that the load of the Boost dual-output circuit is normal at this time. The control circuit does not change the conduction time and maintains the proportional relationship between Vo and Vdd. If the main output signal is greater than the second threshold signal or the secondary output signal is greater than the fourth threshold signal, it indicates that the load of the Boost dual-output circuit is relatively light at this time. The control circuit outputs a control signal to shorten the conduction time of the Boost dual-output circuit, so that the conduction time decreases, and the energy on the capacitor Cc is released in time, maintaining the proportional relationship between Vo and Vdd. The calibration circuit and the method therefor proposed by the present invention achieve the stability of the proportional relationship between Vo and Vdd under different loads, thereby realizing the adaptive and stable operation of the Boost dual-output circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide a further understanding of the present invention, and together with the description, are used to explain the embodiments of the present invention and do not constitute a limitation to the present invention. In the drawings:

[0026] Figure 1 shows a Boost dual-output circuit;

[0027] Figure 2 shows a schematic diagram of the change of the voltage Vdd in the Boost dual-output circuit under light load and heavy load;

[0028] Figure 3 shows a schematic structural diagram of a calibration circuit according to an embodiment of the present invention;

[0029] Figure 4 shows a schematic structural diagram of a main output signal detection circuit according to an embodiment of the present invention;

[0030] Figure 5Shows a schematic structural diagram of a secondary output signal detection circuit according to an embodiment of the present invention;

[0031] Figure 6 Shows a schematic structural diagram of a control circuit according to an embodiment of the first aspect of the present invention;

[0032] Figure 7 Shows a schematic structural diagram of a control circuit according to another embodiment of the first aspect of the present invention;

[0033] Figure 8 Shows a schematic structural diagram of a control circuit according to an embodiment of the second aspect of the present invention. Detailed implementation manners

[0034] To further understand the present invention, the preferred implementation manners of the present invention will be described below in conjunction with embodiments. However, it should be understood that these descriptions are only for further explaining the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0035] The description of this part only focuses on several typical embodiments, and the present invention is not limited to the scope described in the embodiments. Combinations of different embodiments, mutual replacement of some technical features in different embodiments, and mutual replacement of the same or similar prior art means and some technical features in the embodiments are also within the scope of description and protection of the present invention.

[0036] "Coupled" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium such as a conductor, where the electrical conduction medium may contain parasitic inductance or parasitic capacitance, or may also be a connection through an intermediate circuit or component described in the embodiments of the specification; indirect connection may also include a connection through other active or passive devices on the basis of achieving the same or similar functions, such as a connection through circuits or components such as switches, signal amplification circuits, and follower circuits. "Plurality" or "multiple" means two or more.

[0037] An embodiment of the present invention discloses a calibration circuit, which is applied to a Boost dual-output circuit (refer to Figure 1 ), and the Boost dual-output circuit has two operating modes: a non-standby mode and a standby mode. Among them, in the non-standby mode, the Vo load is heavy, and in the standby mode, the Vo load is very light or no-load.

[0038] Specifically, as Figure 3As shown, the calibration circuit includes a detection circuit and a control circuit. The input ends of the detection circuit are respectively coupled to the main output signal S1 and the secondary output signal S2 of the above Boost dual-output circuit, and are used to compare the sampled main output signal with a first threshold signal and a second threshold signal, and compare the sampled secondary output signal with a third threshold signal and a fourth threshold signal, wherein the first threshold signal is less than the second threshold signal, and the third threshold signal is less than the fourth threshold signal. In one embodiment, the main output signal S1 (or the secondary output signal S2) can be all the output signals of the Boost dual-output circuit in one output branch, or can be part of the output signals of the Boost dual-output circuit in one output branch; the main output signal S1 (or the secondary output signal S2) can be a voltage signal, or can be other circuit signals such as current. Preferably, the main output signal is all the voltage signals of the Boost dual-output circuit in one output branch (for example Figure 1 the Vo shown), and the secondary output signal is all the voltage signals of the Boost dual-output circuit in the other output branch (for example Figure 1 the Vdd shown).

[0039] In one embodiment, as Figure 4 and Figure 5As shown, the detection circuit includes a main output signal detection circuit and a secondary output signal detection circuit. Among them, the first threshold signal and the second threshold signal are characterized by the voltages across resistors R1 and R1 + R2, and the third threshold signal and the fourth threshold signal are characterized by the voltages across resistors R3 and R3 + R4. By adjusting the resistance values, the preset values of the threshold signals can be changed to adapt to different main output signals and secondary output signals. Taking the main output signal detection circuit as an example, the main output signal detection circuit includes a first comparator, a second comparator, and a first decoder. Among them, the positive input terminal of the first comparator is coupled to the main output signal Vo, the negative input terminal is coupled to the first threshold signal, and the input terminal is coupled to the first decoder; the positive input terminal of the second comparator is coupled to the main output signal Vo, the negative input terminal is coupled to the second threshold signal, and the input terminal is coupled to the first decoder. Thus, when the main output signal Vo is less than the voltage across resistor R1, both the first comparator and the second comparator output low-level signals, and the first decoder receives the signal "00"; when the main output signal Vo is greater than the voltage across resistor R1 and less than the voltage across resistor R1 + R2, the first comparator and the second comparator output high-level signals and low-level signals respectively, and the first decoder receives the signal "10"; when the main output signal Vo is greater than the voltage across resistor R1 + R2, both the first comparator and the second comparator output high-level signals, and the first decoder receives the signal "11". The first decoder translates the signals "00", "10", and "11" into the first low signal Vo_L, the first medium signal Vo_K, and the first high signal Vo_H. Similarly, the secondary output signal detection circuit includes a third comparator, a fourth comparator, and a second decoder. Among them, the positive input terminal of the third comparator is coupled to the secondary output signal Vdd, the negative input terminal is coupled to the third threshold signal, and the input terminal is coupled to the second decoder; the positive input terminal of the fourth comparator is coupled to the secondary output signal Vdd, the negative input terminal is coupled to the fourth threshold signal, and the input terminal is coupled to the second decoder. Thus, the second decoder translates the secondary output signal Vdd into the second low signal Vdd_L, the second medium signal Vdd_K, and the second high signal Vdd_H.

[0040] Specifically, the input end of the control circuit is coupled to the output end of the detection circuit. When the main output signal is less than the first threshold signal (i.e., the signal Vo_L is received) or the secondary output signal is less than the third threshold signal (i.e., the signal Vdd_L is received), it indicates that the load of the Boost dual-output circuit is relatively heavy at this time, and the main output signal (or the secondary output signal) is weak. The conduction time of the Boost dual-output circuit needs to be increased. Therefore, the control circuit outputs a control signal up to extend the conduction time of the Boost dual-output circuit; in the non-standby mode, when the main output signal is greater than the first threshold signal and less than the second threshold signal (i.e., the signal Vo_K is received), and in the standby mode, when the secondary output signal is greater than the third threshold signal and less than the fourth threshold signal (i.e., the signal Vdd_K is received), it indicates that the load of the Boost dual-output circuit is moderate at this time, and the main output signal (or the secondary output signal) is normal. The conduction time of the Boost dual-output circuit needs to be maintained. Therefore, the control circuit outputs a control signal keep to maintain the conduction time of the Boost dual-output circuit; in the non-standby mode, when the main output signal is greater than the second threshold signal (i.e., the signal Vo_H is received), and in the standby mode, when the secondary output signal is greater than the fourth threshold signal (i.e., the signal Vdd_H is received), it indicates that the load of the Boost dual-output circuit is relatively light at this time, and the main output signal (or the secondary output signal) is strong. The conduction time of the Boost dual-output circuit needs to be shortened. Therefore, the control circuit outputs a control signal down to shorten the conduction time of the Boost dual-output circuit.

[0041] In one embodiment, as Figure 6As shown, the control circuit includes a first AND gate 111, whose input terminals are respectively coupled to the receiver signal Stb and the second intermediate signal Vdd_K; a second AND gate 121, whose input terminals are respectively coupled to the receiver signal Stb and the second high signal Vdd_H; a first OR gate 112, whose input terminals are respectively coupled to the output terminal of the first AND gate 111 and the first intermediate signal Vo_K; a second OR gate 122, whose input terminals are respectively coupled to the output terminal of the second AND gate 121 and the first high signal Vo_H; a third OR gate 132, whose input terminals are respectively coupled to the first low signal Vo_L and the second low signal Vdd_L, and whose output terminal outputs a control signal up for extending the conduction time of the Boost dual-output circuit; a first NOT gate 113, whose input terminal is coupled to the second low signal Vdd_L; a third AND gate 131, whose input terminals are respectively coupled to the output terminal of the first OR gate 112 and the output terminal of the first NOT gate 113, and whose output terminal outputs a control signal keep for maintaining the conduction time of the Boost dual-output circuit; a fourth AND gate 141, whose input terminals are respectively coupled to the output terminal of the second OR gate 122 and the output terminal of the first NOT gate 113, and whose output terminal outputs a control signal down for shortening the conduction time of the Boost dual-output circuit. Among them, since the first AND gate 111 and the second AND gate 121 are coupled to the receiver signal Stb, in the non-standby mode, the output of the signals Vdd_K and Vdd_H will be inhibited; the first NOT gate 113 is coupled to the third AND gate 131 and the fourth AND gate 141, such that when the signal Vdd_L is received, the output of the signals Vo_K and Vo_H will be inhibited. The effect of this embodiment is that in the non-standby mode, the Vo load is relatively heavy, and at this time the conduction time is mainly controlled by the state of Vo, while monitoring the Vdd state to prevent Vdd from being too low or even out of control; in the standby mode, the Vo load is very light or no-load, and the Vdd load is relatively heavy, and at this time the Vdd voltage is mainly controlled, and Vo can be maintained within a reasonable range.

[0042] In one embodiment, as Figure 7As shown, the control circuit includes a second inverter 213, whose input terminal is coupled to the standby signal Stb; a second AND gate 211, whose input terminals are respectively coupled to the output terminal of the second inverter 213 and the first intermediate signal Vo_K; a second AND gate 221, whose input terminals are respectively coupled to the standby signal Stb and the second intermediate signal Vdd_K; a second inverter 223, whose input terminal is coupled to the standby signal Stb; a second AND gate 231, whose input terminals are respectively coupled to the output terminal of the second inverter 223 and the first high signal Vo_H; a second AND gate 241, whose input terminals are respectively coupled to the standby signal Stb and the second high signal Vdd_H; a second OR gate 212, whose input terminals are respectively coupled to the output terminal of the second AND gate 211 and the output terminal of the second AND gate 221; a second OR gate 222, whose input terminals are respectively coupled to the output terminal of the second AND gate 231 and the output terminal of the second AND gate 241; a second OR gate 232, whose input terminals are respectively coupled to the first low signal Vo_L and the second low signal Vdd_L, and whose output terminal outputs a control signal up for extending the conduction time of the Boost dual-output circuit; a second inverter 233, whose input terminal is coupled to the second low signal Vdd_L; a second AND gate 251, whose input terminals are respectively coupled to the output terminal of the second OR gate 212 and the output terminal of the second inverter 233, and whose output terminal outputs a control signal keep for maintaining the conduction time of the Boost dual-output circuit; a second AND gate 261, whose input terminals are respectively coupled to the output terminal of the second OR gate 222 and the output terminal of the second inverter 233, and whose output terminal outputs a control signal down for shortening the conduction time of the Boost dual-output circuit. Among them, compared with the previous embodiment, since the second inverter 213 and the second inverter 223 coupled to the standby signal Stb are added, in the standby mode, the output of the signals Vo_K and Vo_H will be suppressed, avoiding the situation where Vo_K and Vdd_H (or Vo_H and Vdd_K) are output simultaneously.

[0043] Based on a similar inventive concept, an embodiment of the present invention discloses a calibration circuit, which is applied to a Boost dual-output circuit (refer to Figure 1) including a detection circuit and a control circuit. Among them, the detection circuit has been elaborated in detail in the above embodiments and will not be elaborated here. The control circuit, whose input terminal is coupled to the output terminal of the detection circuit, is configured to output a control signal up for extending the conduction time of the Boost dual-output circuit when the main output signal S1 is less than the first threshold signal or the secondary output signal S2 is less than the third threshold signal; when the secondary output signal S2 is greater than the third threshold signal, the main output signal S1 is greater than the first threshold signal and the main output signal S1 is less than the second threshold signal, and when the main output signal S1 is greater than the first threshold signal, the secondary output signal S2 is greater than the third threshold signal and the secondary output signal S2 is less than the fourth threshold signal, output a control signal keep for maintaining the conduction time of the Boost dual-output circuit; when the main output signal S1 is greater than the second threshold signal and the secondary output signal S2 is greater than the fourth threshold signal, output a control signal down for shortening the conduction time of the Boost dual-output circuit.

[0044] In one embodiment, as Figure 8 shown, the control circuit includes a third OR gate 312, whose input terminals are respectively coupled to the first low signal Vo_L and the second low signal Vdd_L, and whose output terminal outputs a control signal up for extending the conduction time of the Boost dual-output circuit; a third OR gate 322, whose input terminals are respectively coupled to the first middle signal Vo_K and the second middle signal Vdd_K; a third OR gate 332, whose input terminals are respectively coupled to the first high signal Vo_H and the second high signal Vdd_H; a third NOT gate 313, whose input terminal is coupled to the output terminal of the third OR gate 312; a third AND gate 311, whose input terminals are respectively coupled to the output terminal of the third NOT gate 313 and the output terminal of the third OR gate 322, and whose output terminal outputs a control signal keep for maintaining the conduction time of the Boost dual-output circuit; a third NOT gate 323, whose input terminal is coupled to the output terminal of the third OR gate 322; a third AND gate 321, having three input terminals, whose input terminals are respectively coupled to the output terminal of the third NOT gate 313, the output terminal of the third NOT gate 323, and the output terminal of the third OR gate 322, and whose output terminal outputs a control signal down for shortening the conduction time of the Boost dual-output circuit. Among them, the third NOT gate 313 will inhibit the output of the control signals keep and down, and the third NOT gate 323 will inhibit the output of the control signal down. Therefore, the effect of this embodiment is: no longer detecting the working mode of the Boost dual-output circuit, controlling the conduction time of the Boost dual-output circuit according to the signal strengths of the main output signal and the secondary output signal, and the first low signal Vo_L (or the second low signal Vdd_L) has the highest priority, and the first high signal Vo_H (or the second high signal Vdd_H) has the lowest priority.

[0045] Based on a similar inventive concept, an embodiment of the present invention discloses a correction circuit applied to a multi-output circuit. The correction circuit includes a detection circuit and a control circuit. Compared with the above embodiment, the correction circuit in this embodiment is no longer limited to being applied to a Boost dual-output circuit, and includes but is not limited to being applied to a circuit with two or more outputs in a Buck switching circuit, a Boost switching circuit, a Buck-Boost switching circuit, and a flyback switching circuit. Among them, the input end of the detection circuit is respectively coupled to multiple output signals of the multi-output circuit, and is used to compare each sampled output signal with a corresponding first threshold signal and a second threshold signal, where the first threshold signal is less than the second threshold signal. The input end of the control circuit is coupled to the output end of the detection circuit, and is used to output a control signal up for extending the conduction time of the multi-output circuit when any output signal is less than the corresponding first threshold signal; to output a control signal keep for maintaining the conduction time of the multi-output circuit when all output signals are greater than the corresponding first threshold signal and any output signal is less than the corresponding second threshold signal; and to output a control signal down for shortening the conduction time of the multi-output circuit when all output signals are greater than the corresponding second threshold signal. It should be noted that in this embodiment, the output signal of each branch of the multi-output circuit corresponds to an adapted first threshold signal and a second threshold signal. The first threshold signal and the second threshold signal are a general term for a type of signal and are not limited to a single signal.

[0046] Based on a similar inventive concept, an embodiment of the present invention discloses a correction method applied to a Boost dual-output circuit. The Boost dual-output circuit has two operating modes: a non-standby mode and a standby mode. The method is characterized by including the following steps:

[0047] S410: Sample the main output signal and the secondary output signal of the Boost dual-output circuit, and compare the sampled main output signal with a first threshold signal and a second threshold signal, and compare the sampled secondary output signal with a third threshold signal and a fourth threshold signal, where the first threshold signal is less than the second threshold signal, and the third threshold signal is less than the fourth threshold signal;

[0048] S420: Output a control signal for extending the conduction time of the Boost dual-output circuit when the main output signal is less than the first threshold signal or the secondary output signal is less than the third threshold signal; output a control signal for maintaining the conduction time of the Boost dual-output circuit when, in the non-standby mode, the main output signal is greater than the first threshold signal and less than the second threshold signal, and when, in the standby mode, the secondary output signal is greater than the third threshold signal and less than the fourth threshold signal; output a control signal for shortening the conduction time of the Boost dual-output circuit when, in the non-standby mode, the main output signal is greater than the second threshold signal, and when, in the standby mode, the secondary output signal is greater than the fourth threshold signal.

[0049] Those skilled in the art should know that in the logic control involved in the specification or drawings, logical controls such as "high level" and "low level", "set" and "reset", "AND gate" and "OR gate", "inverting input terminal" and "non-inverting input terminal" can be interchanged or changed, and the same functions or purposes as those in the above embodiments can be achieved by adjusting the subsequent logical control.

[0050] The description and application of the present invention here are illustrative, and it is not intended to limit the scope of the present invention to the above embodiments. The relevant descriptions of effects or advantages involved in the specification may not be reflected in actual experimental examples due to uncertainties in specific condition parameters or other factors, and the relevant descriptions of effects or advantages are not used to limit the scope of the invention. It is possible to make deformations and changes to the disclosed embodiments here, and various substitutions and equivalents of components are known to those of ordinary skill in the art. Those skilled in the art should clearly understand that the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the present invention. Other deformations and changes can be made to the disclosed embodiments here without departing from the scope and spirit of the present invention.

Claims

1. A correction circuit is applied to a Boost dual-output circuit. The Boost dual-output circuit has two operating modes: a non-standby mode and a standby mode. It is characterized in that The correction circuit includes: A detection circuit, whose input terminals are respectively coupled to the main output signal and the secondary output signal of the Boost dual-output circuit, and is used to compare the sampled main output signal with a first threshold signal and a second threshold signal, and compare the sampled secondary output signal with a third threshold signal and a fourth threshold signal, wherein the first threshold signal is less than the second threshold signal, and the third threshold signal is less than the fourth threshold signal; A control circuit, whose input terminal is coupled to the output terminal of the detection circuit, and is used to output a control signal for extending the conduction time of the Boost dual-output circuit when the main output signal is less than the first threshold signal or the secondary output signal is less than the third threshold signal; in the non-standby mode, when the main output signal is greater than the first threshold signal and less than the second threshold signal, and in the standby mode, when the secondary output signal is greater than the third threshold signal and less than the fourth threshold signal, output a control signal for maintaining the conduction time of the Boost dual-output circuit; in the non-standby mode, when the main output signal is greater than the second threshold signal, and in the standby mode, when the secondary output signal is greater than the fourth threshold signal, output a control signal for shortening the conduction time of the Boost dual-output circuit.

2. The calibration circuit according to claim 1, wherein The detection circuit includes: A main output signal detection circuit, including a first comparator, a second comparator and a first decoder. The first comparator is used to compare the main output signal and the first threshold signal, the second comparator is used to compare the main output signal and the second threshold signal, and the first decoder is used to translate the comparison results of the first comparator and the second comparator into a first detection signal, so that the control circuit outputs a control signal for controlling the conduction time of the Boost dual-output circuit according to the first detection signal; A secondary output signal detection circuit, including a third comparator, a fourth comparator and a second decoder. The first comparator is used to compare the secondary output signal and the third threshold signal, the fourth comparator is used to compare the secondary output signal and the fourth threshold signal, and the second decoder is used to translate the comparison results of the third comparator and the fourth comparator into a second detection signal, so that the control circuit outputs a control signal for controlling the conduction time of the Boost dual-output circuit according to the second detection signal.

3. The calibration circuit according to claim 2, wherein: The first detection signal includes a first low signal, a first medium signal and a first high signal; the second detection signal includes a second low signal, a second medium signal and a second high signal.

4. The calibration circuit according to claim 3, wherein The control circuit includes: An AND gate 11, whose input terminals are respectively coupled to the standby signal and the second medium signal; An AND gate 12, whose input terminals are respectively coupled to the standby signal and the second high signal; An OR gate 11, whose input terminals are respectively coupled to the output terminal of the AND gate 11 and the first medium signal; An OR gate 12, whose input terminals are respectively coupled to the output terminal of the AND gate 12 and the first high signal; A first three-input OR gate, whose input terminals are respectively coupled to the first low signal and the second low signal, and whose output terminal outputs a control signal for extending the conduction time of the Boost dual-output circuit; A first one-input NOT gate, whose input terminal is coupled to the second low signal; A first three-input AND gate, whose input terminals are respectively coupled to the output terminal of the first one-input OR gate and the output terminal of the first one-input NOT gate, and whose output terminal outputs a control signal for maintaining the conduction time of the Boost dual-output circuit; A first four-input AND gate, whose input terminals are respectively coupled to the output terminal of the first two-input OR gate and the output terminal of the first one-input NOT gate, and whose output terminal outputs a control signal for shortening the conduction time of the Boost dual-output circuit.

5. The calibration circuit according to claim 3, wherein The control circuit includes: A second one-input NOT gate, whose input terminal is coupled to the host signal; A second one-input AND gate, whose input terminals are respectively coupled to the output terminal of the second one-input NOT gate and the first middle signal; A second two-input AND gate, whose input terminals are respectively coupled to the host signal and the second middle signal; A second two-input NOT gate, whose input terminal is coupled to the host signal; A second three-input AND gate, whose input terminals are respectively coupled to the output terminal of the second two-input NOT gate and the first high signal; A second four-input AND gate, whose input terminals are respectively coupled to the host signal and the second high signal; A second one-input OR gate, whose input terminals are respectively coupled to the output terminal of the second one-input AND gate and the output terminal of the second two-input AND gate; A second two-input OR gate, whose input terminals are respectively coupled to the output terminal of the second three-input AND gate and the output terminal of the second four-input AND gate; A second three-input OR gate, whose input terminals are respectively coupled to the first low signal and the second low signal, and whose output terminal outputs a control signal for extending the conduction time of the Boost dual-output circuit; A second three-input NOT gate, whose input terminal is coupled to the second low signal; A second five-input AND gate, whose input terminals are respectively coupled to the output terminal of the second one-input OR gate and the output terminal of the second three-input NOT gate, and whose output terminal outputs a control signal for maintaining the conduction time of the Boost dual-output circuit; A second six-input AND gate, whose input terminals are respectively coupled to the output terminal of the second two-input OR gate and the output terminal of the second three-input NOT gate, and whose output terminal outputs a control signal for shortening the conduction time of the Boost dual-output circuit.

6. A calibration circuit is applied to a Boost dual-output circuit, and is characterized in that, The correction circuit includes: A detection circuit, whose input terminals are respectively coupled to the main output signal and the sub-output signal of the Boost dual-output circuit, and is used to compare the sampled main output signal with a first threshold signal and a second threshold signal, and compare the sampled sub-output signal with a third threshold signal and a fourth threshold signal, wherein the first threshold signal is less than the second threshold signal, and the third threshold signal is less than the fourth threshold signal; A control circuit, whose input terminal is coupled to the output terminal of a detection circuit, is configured to output a control signal for extending the conduction time of the Boost dual-output circuit when the main output signal is less than a first threshold signal or the secondary output signal is less than a third threshold signal; to output a control signal for maintaining the conduction time of the Boost dual-output circuit when the secondary output signal is greater than the third threshold signal, the main output signal is greater than the first threshold signal and the main output signal is less than a second threshold signal, and when the main output signal is greater than the first threshold signal, the secondary output signal is greater than the third threshold signal and the secondary output signal is less than a fourth threshold signal; and to output a control signal for shortening the conduction time of the Boost dual-output circuit when the main output signal is greater than the second threshold signal and the secondary output signal is greater than the fourth threshold signal.

7. The calibration circuit according to claim 6, wherein: The detection circuit is further configured to output a first detection signal and a second detection signal, where the first detection signal includes a first low signal, a first medium signal, and a first high signal, and the second detection signal includes a second low signal, a second medium signal, and a second high signal.

8. The calibration circuit according to claim 7, wherein The control circuit includes: A third one-or gate, whose input terminals are respectively coupled to the first low signal and the second low signal, and whose output terminal outputs a control signal for extending the conduction time of the Boost dual-output circuit; A third two-or gate, whose input terminals are respectively coupled to the first medium signal and the second medium signal; A third three-or gate, whose input terminals are respectively coupled to the first high signal and the second high signal; A third one-inverter, whose input terminal is coupled to the output terminal of the third one-or gate; A third one-and gate, whose input terminals are respectively coupled to the output terminal of the third one-inverter and the output terminal of the third two-or gate, and whose output terminal outputs a control signal for maintaining the conduction time of the Boost dual-output circuit; A third two-inverter, whose input terminal is coupled to the output terminal of the third two-or gate; A third two-and gate, having three input terminals, whose input terminals are respectively coupled to the output terminal of the third one-inverter, the output terminal of the third two-inverter, and the output terminal of the third two-or gate, and whose output terminal outputs a control signal for shortening the conduction time of the Boost dual-output circuit.

9. A calibration circuit is applied to a multi-output circuit, characterized in that, The correction circuit includes: A detection circuit, whose input terminals are respectively coupled to multiple output signals of the multi-output circuit, and is configured to compare each sampled output signal with a corresponding first threshold signal and a second threshold signal, where the first threshold signal is less than the second threshold signal; A control circuit, whose input terminal is coupled to the output terminal of the detection circuit, is configured to output a control signal for extending the conduction time of the multi-output circuit when any one of the output signals is less than the corresponding first threshold signal; to output a control signal for maintaining the conduction time of the multi-output circuit when all the output signals are greater than the corresponding first threshold signal and any one of the output signals is less than the corresponding second threshold signal; and to output a control signal for shortening the conduction time of the multi-output circuit when all the output signals are greater than the corresponding second threshold signal.

10. A calibration method is applied to a Boost dual-output circuit. The Boost dual-output circuit has two operating modes, namely a non-standby mode and a standby mode. It is characterized in that, Including the following steps: Sample the main output signal and the secondary output signal of the Boost dual-output circuit, compare the sampled main output signal with a first threshold signal and a second threshold signal, and compare the sampled secondary output signal with a third threshold signal and a fourth threshold signal, wherein the first threshold signal is less than the second threshold signal, and the third threshold signal is less than the fourth threshold signal; When the main output signal is less than the first threshold signal or the secondary output signal is less than the third threshold signal, output a control signal to extend the conduction time of the Boost dual-output circuit; in a non-standby mode, when the main output signal is greater than the first threshold signal and the main output signal is less than the second threshold signal, and in a standby mode, when the secondary output signal is greater than the third threshold signal and the secondary output signal is less than the fourth threshold signal, output a control signal to maintain the conduction time of the Boost dual-output circuit; in a non-standby mode, when the main output signal is greater than the second threshold signal, and in a standby mode, when the secondary output signal is greater than the fourth threshold signal, output a control signal to shorten the conduction time of the Boost dual-output circuit.

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