Optoelectronic device and optoelectronic integrated structure

Abstract

The optoelectronic device and optoelectronic integrated structure provided by the embodiments of the present application can reduce the process complexity and manufacturing cost. The optoelectronic device includes: a first substrate, on a first surface of the first substrate, an application specific integrated circuit (ASIC), a second substrate, and a photonic integrated circuit (PIC) are respectively disposed, and circuit traces of the first substrate are formed on the first surface; an electronic integrated circuit (EIC) flip-chip stacked on the second substrate and the PIC, the EIC being electrically connected to the PIC; at least one conductive via penetrating through at least one of a second surface and a third surface of the second substrate, the EIC being electrically connected to the ASIC disposed on the first substrate through the at least one conductive via and the circuit traces of the first substrate, the second surface being a surface of the second substrate away from the first substrate along the thickness direction of the second substrate, and the third surface being a surface of the second substrate close to the first substrate along the thickness direction of the second substrate.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of optoelectronic communication, and more particularly, to optoelectronic devices and optoelectronic integrated structures in the field of optoelectronic communication. Background Art

[0002] With the rapid growth of data center traffic, the demand for high throughput and large bandwidth in data centers has become increasingly urgent. The optoelectronic interconnection technology has emerged under such demands. How to reduce the size and power consumption of optoelectronic devices has become the main challenge of optoelectronic interconnection technology. The optoelectronic co-packaging technology is an effective way to address the above challenges. The optoelectronic co-packaging technology refers to integrating a photonic integrated circuit (PIC) and an electronic integrated circuit (EIC) fabricated using different processes on a common substrate or within a device, which is a packaging-level integration technology.

[0003] Optoelectronic co-packaging is usually achieved by 3D stacking to package the PIC and EIC on a substrate. Specifically, the PIC and an application specific integrated circuit (ASIC) are respectively provided on the substrate, and the EIC is provided on the PIC. Among them, the EIC is electrically connected to the PIC, and the EIC is electrically connected to the ASIC provided on the substrate through at least one through silicon via (TSV) passing through the PIC and the circuit traces of the substrate.

[0004] However, due to the high process technology complexity and manufacturing cost of designing and manufacturing TSVs on the PIC, the process technology complexity and manufacturing cost are relatively high when implementing optoelectronic co-packaging using the existing 3D stacking method. Summary of the Invention

[0005] Embodiments of the present application provide an optoelectronic device and an optoelectronic integrated structure, which can reduce the process complexity and manufacturing cost.

[0006] In a first aspect, an embodiment of the present application provides an optoelectronic device, including: a first substrate, on a first surface of the first substrate, an application-specific integrated circuit (ASIC), a second substrate, and a photonic integrated circuit (PIC) are respectively disposed, and circuit traces of the first substrate are formed on the first surface; an electronic integrated circuit (EIC) flip-chip stacked on the second substrate and the PIC, the EIC being electrically connected to the PIC; at least one conductive via penetrating through at least one of a second surface and a third surface of the second substrate, the EIC being electrically connected to the ASIC disposed on the first substrate through the at least one conductive via and the circuit traces of the first substrate, where the second surface is a surface of the second substrate away from the first substrate along the thickness direction of the second substrate, and the third surface is a surface of the second substrate close to the first substrate along the thickness direction of the second substrate.

[0007] In the optoelectronic device provided by the embodiment of the present application, the EIC is electrically connected to the ASIC disposed on the first substrate through at least one conductive via penetrating through the second substrate and the circuit traces of the first substrate, without passing through the PIC, thereby avoiding designing and manufacturing conductive vias on the PIC.

[0008] In addition, the second substrate belongs to a packaging substrate, and the process technology for designing and manufacturing conductive vias on the packaging substrate is relatively complete, and the complexity of the process technology and the manufacturing cost are relatively low. Therefore, the process technology complexity and manufacturing cost of the optoelectronic device provided by the embodiment of the present application are relatively low.

[0009] In a possible implementation manner, the second substrate and the PIC are encapsulated by a molding medium.

[0010] In a possible implementation manner, the at least one conductive via further penetrates through a fourth surface and a fifth surface of the molding medium, where the fourth surface is a surface of the molding medium close to the EIC along the thickness direction of the second substrate, and the fifth surface is a surface of the molding medium close to the first substrate along the thickness direction of the second substrate.

[0011] In a possible implementation manner, the optoelectronic device further includes at least one first conductive metal wire penetrating through the fourth surface and a sixth surface of the molding medium, where the sixth surface is a surface of the molding medium located between the fourth surface and the PIC and in contact with the PIC along the thickness direction of the second substrate;

[0012] The PIC is electrically connected to a first end of the at least one first conductive metal wire, and a second end of the at least one first conductive metal wire is electrically connected to the EIC.

[0013] In a possible implementation, the optoelectronic device further includes a first conductive connection member disposed between the PIC and the EIC; the second end of the at least one first conductive metal wire is electrically connected to the first end of the first conductive connection member, and the second end of the first conductive connection member is electrically connected to the EIC.

[0014] In a possible implementation, the optoelectronic device further includes a second conductive connection member disposed between the EIC and the second substrate; the EIC is electrically connected to the first end of the second conductive connection member, and the second end of the second conductive connection member is electrically connected to the circuit trace of the first substrate through the at least one conductive via.

[0015] In a possible implementation, the second substrate is a silicon substrate, a glass substrate, or a ceramic substrate.

[0016] In a second aspect, an embodiment of the present application further provides another optoelectronic device, including: a first substrate, on a first surface of the first substrate, a dedicated integrated circuit ASIC, a second substrate, and a photonic integrated circuit PIC are respectively disposed, and a circuit trace of the first substrate is formed on the first surface; an electronic integrated circuit EIC embedded in the first substrate, the EIC is electrically connected to the ASIC disposed on the first substrate through the circuit trace of the first substrate; at least one conductive via penetrating through a second surface and a third surface of the second substrate, the PIC is electrically connected to the EIC through the at least one conductive via, wherein the second surface is a surface of the second substrate away from the first substrate along the thickness direction of the second substrate, and the third surface is a surface of the second substrate close to the first substrate along the thickness direction of the second substrate.

[0017] In the optoelectronic device provided by the embodiment of the present application, the PIC is electrically connected to the EIC through at least one conductive via penetrating through the second substrate, without passing through the PIC, thereby avoiding designing and manufacturing conductive vias on the PIC.

[0018] In addition, the second substrate belongs to a packaging substrate, and the process technology for designing and manufacturing conductive vias on the packaging substrate is relatively complete, and the process technology complexity and manufacturing cost are relatively low. Therefore, the optoelectronic device provided by the embodiment of the present application has relatively low process technology complexity and manufacturing cost.

[0019] In addition, the EIC is embedded in the first substrate, and the EIC is electrically connected to the ASIC through the circuit trace on the first substrate, and the signal transmission path is short, which can reduce the parasitic parameters during signal transmission and reduce the signal loss. Therefore, the signal transmission bandwidth can be increased, thereby improving the signal transmission performance.

[0020] In a possible implementation, the second substrate and the PIC are encapsulated by a molding medium.

[0021] In a possible implementation, the at least one conductive via also penetrates through the fourth surface and the fifth surface of the plastic encapsulation medium, where the fourth surface is the surface of the plastic encapsulation medium away from the EIC along the thickness direction of the second substrate, and the fifth surface is the surface of the plastic encapsulation medium close to the first substrate along the thickness direction of the second substrate.

[0022] In a possible implementation, the optoelectronic device further includes at least one first conductive metal wire that penetrates through the fourth surface and the sixth surface of the plastic encapsulation medium, where the sixth surface is the surface of the plastic encapsulation medium located between the fourth surface and the PIC and in contact with the PIC along the thickness direction of the second substrate; the PIC is electrically connected to the first end of the at least one first conductive metal wire, and the second end of the at least one first conductive metal wire is electrically connected to the EIC through the at least one conductive via.

[0023] In a possible implementation, the optoelectronic device further includes a first conductive connection member disposed on the seventh surface of the PIC, where the seventh surface is the surface of the PIC away from the first substrate along the thickness direction of the PIC; the second end of the at least one first conductive metal wire is electrically connected to the first end of the first conductive connection member, and the second end of the first conductive connection member is electrically connected to the EIC through the at least one conductive via.

[0024] In a possible implementation, the second substrate is a silicon substrate, a glass substrate, or a ceramic substrate.

[0025] In a third aspect, an optoelectronic integrated structure provided by an embodiment of the present application includes

[0026] a printed circuit board (PCB) on which the optoelectronic device of the first aspect or the optoelectronic device of the second aspect is integrated. Description of the Drawings

[0027] Figure 1 A schematic structural diagram of an existing optoelectronic device 100 is provided;

[0028] Figure 2 A schematic structural diagram of an optoelectronic device 200 according to an embodiment of the present application is provided;

[0029] Figure 3 A connection schematic diagram (top view) of an ASIC and a first substrate according to an embodiment of the present application is provided;

[0030] Figure 4 Another connection schematic diagram (cross-sectional view) of an ASIC and a first substrate according to an embodiment of the present application is provided;

[0031] Figure 5Schematic structural diagrams of the optoelectronic device 500 according to the embodiments of the present application are provided;

[0032] Figure 6 Schematic structural diagrams of the optoelectronic device 600 according to the embodiments of the present application are provided;

[0033] Figure 7 Schematic structural diagrams of the optoelectronic device 700 according to the embodiments of the present application are provided;

[0034] Figure 8 Schematic structural diagrams of the optoelectronic device 800 according to the embodiments of the present application are provided;

[0035] Figure 9 Schematic structural diagrams of another optoelectronic device 800 according to the embodiments of the present application are provided;

[0036] Figure 10 Schematic structural diagrams of the optoelectronic device 1000 according to the embodiments of the present application are provided;

[0037] Figure 11 Schematic structural diagrams of the optoelectronic device 1100 according to the embodiments of the present application are provided. Detailed embodiments

[0038] The technical solutions in the present application will be described below with reference to the accompanying drawings.

[0039] First, the following professional terms involved in the embodiments of the present application are introduced.

[0040] 1. Three-dimensional (3D) stacking

[0041] The 3D stacking technology is a three-dimensional stacking processing technology that stacks chips or structures with different functions through stacking technology or via interconnection and other micro-machining technologies, aiming to form a three-dimensional integrated, signal-connected, and wafer-level, chip-level, silicon cap packaging, etc. packaging and reliability technology in the Z-axis direction.

[0042] 2. Through-silicon via (TSV)

[0043] TSV is the key to 3D chip stacking technology. It allows multiple layers of 3D chips to be stacked, and TSV is used to provide communication in the vertical direction between multiple wafers. Among them, TSV is a method of using vertical through-silicon vias to complete inter-chip interconnection. Due to shorter connection distances and higher strength, it can achieve smaller, thinner, better-performing, higher-density, and significantly reduced size and weight packaging, and can also be used for interconnection between different types of chips. TSV realizes inter-chip interconnection by making vertical conduction between chips and between wafers, enabling the maximum density and minimum external dimensions of 3D chip stacking, and greatly improving chip speed and reducing power consumption.

[0044] 3. Flip Chip (FC)

[0045] Flip chip refers to depositing tin - lead balls on the input / output (I / O) pads of a chip, and then flipping the chip and heating it to combine the molten tin - lead balls with the substrate.

[0046] 4. Redistribution Layer (RDL)

[0047] RDL is a key part of fan - out packaging. RDL deposits metal layers and dielectric layers on the wafer surface and forms corresponding metal wiring patterns to re - layout the I / O ports of the chip and arrange them in new areas with more relaxed pitch occupancy.

[0048] Figure 1 Fig. shows a schematic structural diagram of an existing optoelectronic device 100, which adopts optoelectronic co - packaging technology based on 3D stacking. As Figure 1 shown, the optoelectronic device 100 may include a substrate 101, on which an ASIC 102 and a PIC 103 are respectively provided. The optoelectronic device 100 further includes an EIC 104 stacked on the PIC 103 and at least one TSV 105 passing through the PIC 103. Among them, the PIC 103 is electrically connected to the EIC 104, and the EIC 104 is electrically connected to the ASIC 102 provided on the substrate 101 through the at least one TSV 105 and the circuit traces of the substrate 101.

[0049] That is to say, the existing optoelectronic device 100 needs to design and manufacture at least one TSV on the PIC 103.

[0050] However, since the process technology for designing and manufacturing TSVs on PICs is relatively complex and the manufacturing cost is relatively high. In addition, the development of TSV manufacturing technology for PICs in the industry is not yet mature. Therefore, the process technology of the existing optoelectronic device 100 is relatively complex and the manufacturing cost is relatively high.

[0051] Regarding the problems existing in the above - mentioned existing optoelectronic device 100, Figure 2 Fig. shows a schematic structural diagram of an optoelectronic device 200 provided by an embodiment of the present application.

[0052] As Figure 2 shown, the optoelectronic device 200 may include a first substrate 201, on the first surface of which an ASIC 202, a second substrate 203 and a PIC 204 are respectively provided.

[0053] The optoelectronic device 200 further includes an EIC 205 flip-chip stacked on the second substrate 203 and the PIC 204, and at least one conductive via 206 penetrating through the second surface and the third surface of the second substrate 203. The EIC 205 is electrically connected to the PIC 204, and the EIC 205 is electrically connected to the ASIC 202 disposed on the first substrate 201 through the at least one conductive via 206 and the circuit traces of the first substrate 201.

[0054] It should be noted that the circuit traces of the first substrate 201 are formed on the first surface; the second surface may be the surface of the second substrate 203 away from the first substrate 201 along the thickness direction of the second substrate; the third surface is the surface of the second substrate 203 close to the first substrate 201 along the thickness direction of the second substrate.

[0055] For example: the first surface may be surface ① as shown in Figure 2 ; the second surface may be surface ② as shown in Figure 2 ; the third surface may be surface ③ as shown in Figure 2 .

[0056] It should be noted that Figure 2 only one conductive via 206 is schematically shown in

[0057] , but the embodiments of the present application are not limited thereto.

[0058] Optionally, the at least one conductive via 206 may be arranged in various ways, and the embodiments of the present application do not limit this.

[0059] Optionally, the at least one conductive via 206 may be arranged in other ways according to actual needs, and the embodiments of the present application do not limit this.

[0060] Optionally, the conductive via 206 may be made conductive in various ways, and the embodiments of the present application do not limit this.

[0061] In one possible implementation, as shown in Figure 2 , the conductive via 206 may be filled with a conductive metal to form a conductive metal column, and the conductive via 206 is made conductive through the conductive metal column.

[0062] In another possible implementation, a conductive metal layer is provided on the inner wall of the conductive via 206, and the conductive via 206 is made conductive through the conductive metal layer.

[0063] In another possible implementation, a conductive metal wire may be provided in the conductive via 206, and the conductive via 206 conducts electricity through the conductive metal wire.

[0064] Optionally, the second substrate 203 may be a substrate made of various packaging materials, and the embodiments of the present application do not limit this.

[0065] For example: the second substrate 203 may be a silicon substrate, a glass substrate, a ceramic substrate, or other organic substrate.

[0066] Optionally, the PIC 204 may be various types of chips, and the embodiments of the present application do not limit this.

[0067] For example: the PIC 204 may be an active chip, a passive chip, or an integrated chip.

[0068] Optionally, the PIC 204 may be a chip made of various chip materials, and the embodiments of the present application do not limit this.

[0069] For example: the PIC 204 may be a silicon-based chip or a III-V compound-based chip.

[0070] It should be noted that the chip types and chip materials of the above PIC 204 can be combined in various ways, and the embodiments of the present application do not limit this. For example: the PIC 204 may be a silicon-based active chip, or the PIC 204 may be a III-V compound (such as InP or GaAs)-based integrated chip.

[0071] In the optoelectronic device 200 provided by the embodiments of the present application, the EIC 205 is electrically connected to the ASIC 202 provided on the first substrate 201 through at least one conductive via 206 penetrating the second substrate 203 and the circuit traces of the first substrate 201, without passing through the PIC 204, thereby avoiding designing and manufacturing conductive vias on the PIC 204.

[0072] In addition, the second substrate 203 belongs to a packaging substrate, and the process technology for designing and manufacturing conductive vias on the packaging substrate is relatively complete, and the complexity of the process technology and the manufacturing cost are relatively low. Therefore, the optoelectronic device 200 has a lower process technology complexity and manufacturing cost compared to the existing optoelectronic device 100.

[0073] Optionally, the ASIC 202, the second substrate 203, and the PIC 204 are respectively provided on the first surface of the first substrate 201. It can be understood that: the ASIC 202, the second substrate 203, and the PIC 204 are respectively mounted on the surface ①.

[0074] Optionally, the ASIC 202, the second substrate 203, and the PIC 204 can be mounted on the surface ① in various ways, and the embodiments of the present application do not limit this.

[0075] It should be noted that circuit traces of the ASIC 202 are formed on the seventh surface of the ASIC 202, and the seventh surface is the surface close to the first substrate 201 along the thickness direction of the ASIC 202; circuit traces of the PIC 204 are formed on the eighth surface of the PIC 204, and the eighth surface is the surface close to the EIC 205 along the thickness direction of the PIC 204.

[0076] For example: the seventh surface can be the surface ⑦ as shown in Figure 2 ; the eighth surface can be the surface ⑧ as shown in Figure 2 .

[0077] That is to say, the ASIC 202 can be flip-mounted on the first surface, and the PIC 204 can be face-mounted on the first surface.

[0078] It should be noted that the "flip mounting" described in the embodiments of the present application can also be referred to as "flip welding" or "flip packaging", and the embodiments of the present application do not limit this.

[0079] In a possible implementation manner, as shown in Figure 2 , the ASIC 202 can be flip-mounted on the surface ① through at least one first solder ball 210.

[0080] For example: as shown in Figure 3 (top view) and Figure 4 (cross-sectional view) show a connection schematic diagram of the AIC 202 and the first substrate 201. As shown in Figure 3 and Figure 4 , at least one first pad 211 is provided on the surface ① of the first substrate 201, at least one second pad 212 is provided on the surface ⑦ of the ASIC 202, and the at least one first pad 211 and the at least one second pad 212 are welded together through at least one first solder ball 210.

[0081] It should be noted that Figure 3 and Figure 4 only take 4 first pads 211, 4 first solder balls 210, and 4 second solder balls 212 as examples for introduction, and the embodiments of the present application do not limit the number of pads and solder balls.

[0082] It should be noted that the mounting manners of the second substrate 203 and the PIC 204 on the first substrate 201 can refer to Figure 3 and Figure 4The installation manner of the ASIC 202 on the first substrate 201 is not described herein again to avoid repetition.

[0083] Optionally, the EIC 205 is flip-chip stacked on the second substrate 203 and the PIC 204, and may include: the EIC 205 is flip-chip mounted on the surface ② of the second substrate 203; or, the EIC 205 is flip-chip mounted on the surface ⑧ of the PIC 204; or, the EIC 205 is flip-chip mounted on the surface ② of the second substrate 203 and the surface ⑧ of the PIC 204.

[0084] It should be noted that circuit traces of the EIC 205 are formed on the ninth surface of the EIC 205, and the ninth surface is close to the surface of the PIC 204 along the thickness direction of the EIC 205.

[0085] For example: the ninth surface may be the surface ⑨ as shown in Figure 2 The surface shown.

[0086] Optionally, the EIC 205 may be flip-chip stacked on the second substrate 203 and the PIC 204 in various ways, and the embodiments of the present application do not limit this.

[0087] In a possible manner, the EIC 205 may be flip-chip mounted on the second substrate 203 and / or the PIC 204 through at least one second solder ball.

[0088] It should be noted that the installation manner of the EIC 205 on the first substrate 201 may refer to the installation manner of the ASIC 202 on the first substrate 201 described in Figure 3 And Figure 4 For avoiding repetition, it is not described herein again.

[0089] Optionally, the EIC 205 may be electrically connected to the PIC 204 in various ways, and the embodiments of the present application do not limit this.

[0090] In a possible implementation manner, as shown in Figure 2 The optoelectronic device 200 may further include a first conductive connection member 207 disposed between the PIC 204 and the EIC 205. The EIC 205 is electrically connected to the first end of the first conductive connection member 207, and the second end of the first conductive connection member 207 is electrically connected to the PIC 204.

[0091] Optionally, the first conductive connection member 207 may be in various forms, and the embodiments of the present application do not limit this.

[0092] In a possible implementation manner, the first conductive connection member 207 may be a first redistribution layer 207.

[0093] In another possible implementation, the first conductive connector 207 may be at least one second conductive metal wire 207.

[0094] Optionally, the EIC 205 may be electrically connected to the ASIC 202 through the at least one conductive via 206 and the circuit traces of the first substrate 201 in various ways, and the embodiments of the present application do not limit this.

[0095] In one possible implementation, the EIC 205 is electrically connected to the first end of the at least one conductive via 206, and the second end of the at least one conductive via 206 is electrically connected to the ASIC 202 through the circuit traces of the first substrate 201.

[0096] In another possible implementation, as Figure 2 shown, the optoelectronic device 200 may further include a second conductive connector 208 disposed between the EIC 205 and the second substrate 203. The EIC 205 is electrically connected to the first end of the second conductive connector 208, and the second end of the second conductive connector 208 is electrically connected to the circuit traces of the first substrate 201 on the surface ① through the at least one conductive via 206, where the circuit traces of the first substrate 201 are electrically connected to the ASIC 202.

[0097] Optionally, the second conductive connector 208 may be in various forms, and the embodiments of the present application do not limit this.

[0098] In one possible implementation, the second conductive connector 208 may be a second redistribution layer 208.

[0099] In another possible implementation, the second conductive connector 208 may be at least one third conductive metal wire 208. <tmp

[0100] Optionally, the optoelectronic device may further include a third conductive connector 209 disposed between the second substrate 203 and the first substrate 201. The second end of the second conductive connector 208 is electrically connected to the first end of the third conductive connector 209 through the at least one conductive via 206, and the second end of the third conductive connector 209 is electrically connected to the circuit traces of the first substrate 201 on the surface ①.

[0101] Optionally, the third conductive connector 209 may be in various forms, and the embodiments of the present application do not limit this.

[0102] In one possible implementation, the third conductive connector 209 may be a third redistribution layer 209.

[0103] In another possible implementation, the third conductive connecting member 209 may be at least one fourth conductive metal wire 209.

[0104] It should be noted that Figure 2 only schematically shows that the EIC 205 is flip-chip mounted on the surface ② and the surface ⑧, but the embodiments of the present application are not limited thereto.

[0105] For example: Figure 5 shows a schematic structural diagram of the optoelectronic device 500 provided by the embodiments of the present application. As Figure 5 shown, the EIC 505 is flip-chip mounted on the surface ② of the second substrate 503. A first conductive connecting member 507 is provided between the PIC 504 and the EIC 505. The EIC 505 is electrically connected to the first end of the first conductive connecting member 507, the PIC 504 is electrically connected to the second end of the first conductive connecting member 507, and the EIC 505 is electrically connected to the circuit trace on the first substrate 501 on the surface ① through the at least one conductive via 506. Among them, the circuit trace of the first substrate 501 is electrically connected to the ASIC 502.

[0106] In a possible implementation, the first conductive connecting member 507 may be at least one second conductive metal wire 507.

[0107] Again, for example: Figure 6 shows a schematic structural diagram of the optoelectronic device 600 provided by the embodiments of the present application. As Figure 6 shown, the EIC 605 is flip-chip mounted on the surface ⑧ of the PIC 604. A second conductive connecting member 608 is provided between the PIC 604 and the EIC 605. The EIC 605 is electrically connected to the PIC 604, and the EIC 605 is electrically connected to the first end of the second conductive connecting member 608. The second end of the second conductive connecting member 608 is electrically connected to the circuit trace on the first substrate 601 on the surface ① through the at least one conductive via 606. Among them, the circuit trace of the first substrate 601 is electrically connected to the ASIC 602.

[0108] In a possible implementation, the second conductive connecting member 608 may be at least one third conductive metal wire 608.

[0109] It should be noted that Figure 5 and Figure 6 For the structures of the parts not involved in Figures 2 to 4 reference can be made to the relevant parts in

[0110] It should be noted that Figures 2 to 6 only takes the example of the second substrate and the PIC being independently mounted on the first substrate for introduction.

[0111] Optionally, the second substrate and the PIC may be encapsulated and then mounted on the first substrate.

[0112] In a possible implementation, Figure 7 A schematic structural diagram of an optoelectronic device 700 provided by an embodiment of the present application is shown. As Figure 7 shown, the optoelectronic device 700 may include a first substrate 701. An ASIC 702, a second substrate 703, and a PIC 704 are respectively disposed on a surface ① of the first substrate 701. Among them, the second substrate 703 and the PIC 704 are encapsulated by an encapsulation medium 710.

[0113] The optoelectronic device 700 further includes an EIC 705 flip-chip stacked on a fourth surface of the encapsulation medium 710 and at least one conductive through-hole 706 penetrating the fourth surface and a fifth surface of the encapsulation medium 710. The EIC 705 is electrically connected to the PIC 704, and the EIC 705 is electrically connected to the ASIC 705 disposed on the first substrate 701 through the at least one conductive through-hole 706 and a circuit trace of the first substrate 701.

[0114] It should be noted that the fourth surface is the surface of the encapsulation medium 710 close to the EIC 704 along the thickness direction of the second substrate 703, and the fifth surface is the surface of the encapsulation medium 710 close to the first substrate 701 along the thickness direction of the second substrate 703.

[0115] For example: The fourth surface may be the surface ④ as shown in Figure 7 ; The fifth surface may be the surface ⑤ as shown in Figure 7 .

[0116] It should be noted that Figure 7 For the parts not involved in Figures 2 to 4 , the relevant parts in

[0117] In a possible implementation, the optoelectronic device 700 may further include at least one first conductive metal wire 711 penetrating the surface ④ and a sixth surface of the encapsulation medium 710. The PIC 704 is electrically connected to a first end of the at least one first conductive metal wire 711, and a second end of the at least one first conductive metal wire 711 is electrically connected to the EIC 705.

[0118] It should be noted that the sixth surface is the surface of the encapsulation medium located between the fourth surface and the PIC and in contact with the PIC along the thickness direction of the second substrate.

[0119] For example: The sixth surface may be the surface as shown in Figure 7The surface ⑥ shown in

[0120] Further, the optoelectronic device 700 may further include a first conductive connection member 707 disposed between the PIC 704 and the EIC 705. The second end of the at least one first conductive metal wire 711 is electrically connected to the first end of the first conductive connection member 707, and the second end of the first conductive connection member 707 is electrically connected to the EIC 705.

[0121] It should be noted that the structure of the first conductive connection member 707 may refer to the above-mentioned first conductive connection member 207. To avoid repetition, it will not be elaborated here.

[0122] Optionally, the EIC 705 may be electrically connected to the ASIC 702 through the at least one conductive via 706 and the circuit traces on the first substrate 701 on the surface ① in various ways, and the embodiments of the present application do not limit this.

[0123] In a possible implementation manner, the EIC 705 is electrically connected to the first end of the at least one conductive via 706, and the second end of the at least one conductive via 706 is electrically connected to the ASIC 702 through the circuit traces on the first substrate 701.

[0124] Optionally, the optoelectronic device 700 may further include a second conductive connection member 708 disposed between the EIC 705 and the second substrate 703. The EIC 705 is electrically connected to the first end of the second conductive connection member 708, the second end of the second conductive connection member 708 is electrically connected to the first end of the at least one conductive via 706, and the second end of the at least one conductive via 706 is electrically connected to the ASIC 702 through the circuit traces on the first substrate 701.

[0125] It should be noted that the structure of the second conductive connection member 708 may refer to the above-mentioned second conductive connection member 208. To avoid repetition, it will not be elaborated here.

[0126] Optionally, the optoelectronic device 700 may further include a third conductive connection member 709 disposed between the second substrate 703 and the first substrate 701. The second end of the at least one conductive via 706 is electrically connected to the first end of the third conductive connection member 709, and the second end of the third conductive connection member 709 is electrically connected to the ASIC 702 through the circuit traces on the first substrate 701.

[0127] It should be noted that the structure of the third conductive connection member 709 may refer to the above-mentioned third conductive connection member 209. To avoid repetition, it will not be elaborated here.

[0128] Optionally, Figures 2 to 7The PIC described in the embodiment may include an optical waveguide for guiding the transmission of optical signals.

[0129] In one possible implementation, Figure 8 Schematic diagram of the structure of the optoelectronic device 800 provided in the embodiment of the present application is shown. Figure 8 As shown, the PIC 804 may include an optical waveguide 812. The optical waveguide 812 may be arranged in parallel between the surface ⑧ and the surface ⑩ of the PIC 804 and close to the surface ⑧.

[0130] Optionally, the optical interface of the optical waveguide 812 can be set at multiple positions, which is not limited in the embodiment of the present application.

[0131] In one possible implementation, Figure 8 As shown, the optical interface 813 of the optical waveguide 812 can be set on the surface ⑧.

[0132] In another possible implementation, Figure 9 As shown, the optical interface 813 of the optical waveguide 812 can be set at the end face of the PIC 804 and close to the surface ⑧.

[0133] It should be noted that Figure 7 FIG. 7 schematically shows that the surface ① of the first substrate 701 is molded in the molding medium 710 , but the embodiment of the present application is not limited thereto.

[0134] Alternatively, as Figure 8 and Figure 9 As shown, the area on the surface ⑧ where the orthographic projection of the optical waveguide 812 is located can be exposed outside the molding medium 810.

[0135] Optionally, Figures 2 to 7 When the second substrate and the PIC are separately arranged on the first substrate, the position of the optical waveguide in the PIC can refer to Figure 8 and Figure 9 To avoid repetition, the introduction in is not repeated here.

[0136] Figure 10 Schematic diagram of the structure of the optoelectronic device 1000 provided in an embodiment of the present application is shown. Figure 10 As shown, the optoelectronic device 1000 includes a first substrate 1001 , on the first surface of which an ASIC 1002 , a second substrate 1003 and a PIC 1004 are respectively disposed.

[0137] The optoelectronic device 1000 further includes an EIC 1005 embedded in the first substrate 1001 and at least one conductive via 1006 penetrating through the second surface and the third surface of the second substrate 1003. The EIC 1005 is electrically connected to the ASIC 1002 disposed on the first substrate 1001 through the circuit traces of the first substrate 1001, and the PIC 1004 is electrically connected to the EIC 1005 through the at least one conductive via 1006.

[0138] In a possible implementation, circuit traces of the first substrate 1001 are formed on the first surface; the second surface may be the surface of the second substrate 1003 away from the first substrate 1001 along the thickness direction of the second substrate 1003; the third surface is the surface of the second substrate 1003 close to the first substrate 1001 along the thickness direction of the second substrate 1003.

[0139] For example: the first surface may be surface ① as shown in Figure 10 ; the second surface may be surface ② as shown in Figure 10 ; the third surface may be surface ③ as shown in Figure 10 .

[0140] Optionally, the second substrate 1003 may be a substrate made of various packaging materials, and the embodiments of the present application do not limit this.

[0141] For example: the second substrate 1003 may be a silicon substrate, a glass substrate, a ceramic substrate or other organic substrates.

[0142] Optionally, the PIC 1004 may be various types of chips, and the embodiments of the present application do not limit this.

[0143] For example: the PIC 1004 may be an active chip, a passive chip or an integrated chip.

[0144] Optionally, the PIC 1004 may be a chip made of various chip materials, and the embodiments of the present application do not limit this.

[0145] For example: the PIC 1004 may be a silicon-based chip or a III-V compound-based chip.

[0146] It should be noted that the chip types and chip materials of the above PIC 1004 can be combined in various ways, and the embodiments of the present application do not limit this. For example: the PIC 1004 may be a silicon-based active chip, or the PIC 1004 may be a III-V compound (such as InP or GaAs) - based integrated chip.

[0147] The optoelectronic device 1000 provided by the embodiment of the present application. The PIC 1004 is electrically connected to the EIC 1005 through at least one conductive through-hole 1006 penetrating through the second substrate 1003, without passing through the PIC 1004, thereby avoiding designing and manufacturing conductive through-holes on the PIC 1004.

[0148] In addition, the second substrate 1003 belongs to a packaging substrate. The process technology for designing and manufacturing conductive through-holes on the packaging substrate is relatively complete, and the complexity of the process technology and the manufacturing cost are relatively low. Therefore, the optoelectronic device 1000 has a lower process technology complexity and manufacturing cost compared to the existing optoelectronic device 100.

[0149] Furthermore, the EIC 1005 is embedded in the first substrate 1001, and the EIC 1005 is electrically connected to the ASIC 1002 through circuit traces on the first substrate 1001. The signal transmission path is short, which can reduce parasitic parameters during signal transmission and reduce signal loss. Therefore, it can improve the signal transmission bandwidth and thus improve signal transmission performance.

[0150] Optionally, the ASIC 1002, the second substrate 1003, and the PIC 1004 are respectively arranged on the first surface of the first substrate 1001. It can be understood that the ASIC 1002, the second substrate 1003, and the PIC 1004 are respectively mounted on the surface ①.

[0151] It should be noted that the mounting manners of the ASIC 1002, the second substrate 1003, and the PIC 1004 on the surface ① can be referred to Figure 2 for the corresponding introduction. To avoid repetition, it will not be elaborated here.

[0152] In a possible implementation manner, the ASIC 1002 can be flip-chip mounted on the first surface, and the PIC 1004 can be face-up mounted on the first surface. Specifically, it can be referred to Figure 2 for the corresponding introduction. It will not be elaborated here.

[0153] It should be noted that the "flip-chip mounting" described in the embodiment of the present application can also be referred to as "flip-chip welding" or "flip-chip packaging". The embodiment of the present application does not limit this.

[0154] In a possible implementation manner, circuit traces of the PIC 1004 are formed on the seventh surface of the PIC 1004. The seventh surface is the surface close to the EIC 1005 along the thickness direction of the PIC 1004; circuit traces of the ASIC 1002 are formed on the eighth surface of the ASIC 1002. The eighth surface is the surface close to the first substrate 1001 along the thickness direction of the ASIC 1002.

[0155] For example, the seventh surface may be surface ⑦ as shown in Figure 10 ; the eighth surface may be surface ⑧ as shown in Figure 10 .

[0156] In a possible implementation, the EIC 1005 is embedded in the first substrate 1001. Circuit traces of the EIC 1005 are formed on the ninth surface of the EIC 1005. The ninth surface is close to the surface of the PIC 1004 along the thickness direction of the EIC 1005, and the ninth surface of the EIC is exposed outside the first substrate 1001.

[0157] For example, the ninth surface may be surface ⑨ as shown in Figure 10 .

[0158] Optionally, the EIC 1005 may be electrically connected to the PIC 1004 in various ways, and the embodiments of the present application do not limit this.

[0159] In a possible implementation, as shown in Figure 10 , the optoelectronic device 1000 may further include a first conductive connector 1007 disposed on surface ⑦ of the PIC 1004. The PIC is electrically connected to the first end of the first conductive connector 1007. The second end of the first conductive connector 1007 is electrically connected to the first end of the at least one conductive via. The second end of the at least one conductive via is electrically connected to the EIC.

[0160] It should be noted that the structure of the first conductive connector 1007 may refer to the above-mentioned first conductive connector 207. To avoid repetition, it will not be elaborated here.

[0161] Optionally, the optoelectronic device 1000 may further include a second conductive connector 1008 disposed between the second substrate 1003 and the EIC 1005. The second end of the at least one conductive via 1006 is electrically connected to the EIC through the second conductive connector 1008.

[0162] It should be noted that the structure of the second conductive connector 1008 may refer to the above-mentioned second conductive connector 208. To avoid repetition, it will not be elaborated here.

[0163] Optionally, Figure 10 the parts not involved in Figures 2 to 6 may refer to the relevant parts in

[0164] It should be noted that Figure 10Only for illustrative purposes, the following takes the example that the second substrate 1003 and the PIC 1004 are independently mounted on the first substrate 1001, but the embodiments of the present application are not limited thereto.

[0165] Optionally, the second substrate 1003 and the PIC 1004 can be mounted on the first substrate after being encapsulated, and the embodiments of the present application do not limit this.

[0166] In one possible implementation, Figure 11 FIG. shows a schematic structural diagram of an optoelectronic device 1100 provided by an embodiment of the present application. As Figure 11 shown, the optoelectronic device 1100 may include a first substrate 1101, on the surface ① of the first substrate 1101, an ASIC 1102, a second substrate 1103, and a PIC 1104 are respectively provided. Among them, the second substrate 1103 and the PIC 1104 are encapsulated by an encapsulation medium 1109.

[0167] The optoelectronic device 1100 further includes an EIC 1105 embedded in the first substrate 1101 and at least one conductive through-hole 1106 penetrating through the fourth surface and the fifth surface of the encapsulation medium 1109. The EIC 1105 is electrically connected to the ASIC 1102 provided on the first substrate 1101 through the circuit traces of the first substrate 1101, and the PIC 1104 is electrically connected to the EIC 1105 through the at least one conductive through-hole 1106.

[0168] In one possible implementation, the fourth surface is the surface of the encapsulation medium 1109 close to the EIC 1104 along the thickness direction of the second substrate 1103, and the fifth surface is the surface of the encapsulation medium 1109 close to the first substrate 1101 along the thickness direction of the second substrate 1103.

[0169] For example: the fourth surface can be the surface ④ as shown in Figure 11 ; the fifth surface can be the surface ⑤ as shown in Figure 11 .

[0170] It should be noted that Figure 11 For the parts not involved in Figure 10 , reference can be made to the relevant parts in

[0171] Optionally, the PIC 1104 can be electrically connected to the EIC 1105 through the at least one conductive through-hole 1106 in various ways, and the embodiments of the present application do not limit this.

[0172] In a possible implementation, the optoelectronic device 1100 further includes at least one first conductive metal wire 1110 that penetrates through the fourth surface and the sixth surface of the encapsulation medium 1109. The PIC 1104 is electrically connected to the first end of the at least one first conductive metal wire 1110. The second end of the at least one first conductive metal wire 1110 is electrically connected to the first end of the at least one conductive via 1106. The second end of the at least one conductive via 1106 is electrically connected to the EIC 1105. Wherein, the second end of the at least one conductive via 1106 is close to the first substrate 1101.

[0173] In a possible implementation, the sixth surface is the surface of the encapsulation medium 1109 that is located between the fourth surface and the PIC 1104 along the thickness direction of the second substrate 1103 and contacts the PIC 1104.

[0174] For example: The sixth surface can be the surface ⑥ as shown in Figure 11 Figure.

[0175] Furthermore, the optoelectronic device 1100 further includes a first conductive connector 1107 disposed on the seventh surface of the PIC 1104. The second end of the at least one first conductive metal wire 1110 is electrically connected to one side of the first conductive connector 1107. The other side of the first conductive connector 1107 is electrically connected to the first end of the at least one conductive via 1106.

[0176] It should be noted that the structure of the first conductive connector 1107 can refer to the above-mentioned first conductive connector 207. To avoid repetition, it will not be elaborated here.

[0177] In a possible implementation, the seventh surface is the surface of the PIC 1104 that is away from the first substrate 1101 along the thickness direction of the PIC 1104.

[0178] For example: The seventh surface can be the surface ⑦ as shown in Figure 11 Figure.

[0179] Optionally, the optoelectronic device 1100 may further include a second conductive connector 1108 disposed between the second substrate 1103 and the EIC 1105. The second end of the at least one conductive via 1106 is electrically connected to one side of the second conductive connector 1108. The other side of the second conductive connector 1108 is electrically connected to the EIC 1105.

[0180] It should be noted that the structure of the second conductive connector 1108 can refer to the above-mentioned first conductive connector 208. To avoid repetition, it will not be elaborated here.

[0181] Optionally, the positions of the optical waveguides in the PIC1104 and the positions of the optical ports of the optical waveguides can be referred to Figure 8 and Figure 9 for the corresponding introductions therein. To avoid repetition, they will not be elaborated here.

[0182] The embodiment of the present application further provides an optoelectronic integrated structure, including a printed circuit board (PCB), on which any of the optoelectronic devices described in the above Figures 2 to 9 is integrated; or any of the optoelectronic devices described in the above Figure 10 or Figure 11 is integrated.

[0183] As described above, the above are only the specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A photoelectric device, characterized in that: include: A first substrate, wherein an application-specific integrated circuit (ASIC), a second substrate, and a photonic integrated circuit (PIC) are respectively disposed on a first surface of the first substrate, circuit traces of the first substrate are formed on the first surface, the PIC and the second substrate are soldered to the first surface, and the second substrate and the PIC are encapsulated by a plastic encapsulation medium; an electronic integrated circuit EIC embedded in the first substrate, the EIC being electrically connected to the ASIC disposed on the first substrate via the circuit traces of the first substrate; at least one conductive via extending through a fourth surface of the molding medium, the second surface of the second substrate, the third surface of the second substrate, and a fifth surface of the molding medium, wherein the second surface is a surface of the second substrate away from the first substrate along the thickness direction of the second substrate, the third surface is a surface of the second substrate close to the first substrate along the thickness direction of the second substrate, the fourth surface is a surface of the molding medium away from the EIC along the thickness direction of the second substrate, and the fifth surface is a surface of the molding medium close to the first substrate along the thickness direction of the second substrate; At least one first conductive metal line extends through the fourth surface and the sixth surface of the molding medium, the PIC is electrically connected to a first end of the at least one first conductive metal line, and a second end of the at least one first conductive metal line is electrically connected to the EIC through the at least one conductive via. The sixth surface is a surface of the molding medium located between the fourth surface and the PIC along the thickness direction of the second substrate and in contact with the PIC.

2. The photovoltaic device according to claim 1, wherein: The optoelectronic device further includes a first conductive connection member disposed on a seventh surface of the PIC, wherein the seventh surface is a surface of the PIC away from the first substrate along a thickness direction of the PIC; The second end of the at least one first conductive metal wire is electrically connected to the first end of the first conductive connector, and the second end of the first conductive connector is electrically connected to the EIC through the at least one conductive via.

3. The photovoltaic device according to claim 1 or 2, characterized in that The second substrate is a silicon substrate, a glass substrate or a ceramic substrate.

4. An optoelectronic integrated structure, characterized in that: include: A printed circuit board (PCB) having the optoelectronic device according to any one of claims 1 to 3 integrated thereon.

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