Method for fabricating low-noise photodetector devices in cdhgte substrates

Abstract

A method of manufacturing a photodetector device, comprising the steps of: fabricating a cadmium-rich structured coating (122) on a substrate (110) of Cd x Hg 1‑x Te, and using a first etch mask; performing an etch to enlarge the via of the first etch mask or to enlarge the via of an intermediate layer etched with the structured coating, thereby forming a second etch mask; implanting an acceptor dopant element into the substrate (110) through the second etch mask (150), and activating and diffusing the acceptor dopant element to form at least one P-doped region in the semiconductor substrate; performing a selective interdiffusion anneal of cadmium, thereby forming a cadmium-rich concentration well with a lateral gradient of cadmium concentration in each P-doped region; and fabricating at least one electrical contact pad (171) at each via (121) in the structured coating (122).

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of infrared photodiodes made of Cd x Hg 1-x Te (0 < x < 1) for detecting infrared radiation, in particular for infrared imaging applications. BACKGROUND

[0002] A photodiode comprises a substrate made of a semiconductor material in which a PN junction separates an N-doped region from a P-doped region. At thermodynamic equilibrium, a space-charge region of free carriers extends on both sides of the PN junction and induces a high electric field in the photodiode.

[0003] In operation, the N-doped region or the P-doped region forms an absorption region. When a photon having an adapted wavelength is absorbed in the absorption region, so-called minority carriers are generated in the absorption region. This minority carriers diffuse in the substrate until reaching the space-charge region where it is accelerated by the strong electric field towards the other doped region. It is collected in this other doped region to form an electric current. The photodiode is sensitive only in a determined range of wavelengths depending on the forbidden bandwidth or gap of the absorption region. A low gap value in the absorption region ensures the sensitivity of the photodiode to long wavelengths.

[0004] Different "parasitic" or "dark" currents related to thermal agitation and generation-recombination on defects limit the performance of the photodiode. Positioning the charge region of the junction in a material having a higher gap value allows to reduce the impact of these unwanted currents.

[0005] Moreover, it is known that in a semiconductor substrate of Cd x Hg 1-x Te (alloy of cadmium, mercury and tellurium, 0 < x < 1), the gap depends on the concentration of cadmium. The greater this concentration, the greater the gap.

[0006] Therefore, the person skilled in the art thought to manufacture a Cd x Hg 1-x Te photodiode having an absorption region with a low cadmium content to make the photodiode sensitive to long wavelengths and having a portion with a high cadmium content dedicated to reduce the dark current. In operation, at least a part of the space-charge region extends in the portion with a high cadmium content which allows to obtain a reduced dark current. An example of such a photodiode is described in patent application WO 2013 / 079446. In this document, the absorption region is N-doped. The well with a high cadmium content extends in the P-doped region and has a substantially constant cadmium concentration. By covering the Cd x Hg 1-xa CdTe substrate and by performing an interdiffusion anneal during which the cadmium atoms of the cadmium-rich layer will diffuse in the substrate, in particular in the P-doped region.

[0007] The drawback of this solution is that it requires a compromise on the composition of the well to avoid the latter from forming a barrier to the diffusion of the minority carriers in the space-charge region. It is therefore necessary to ensure that the concentration of cadmium in the well does not exceed a critical threshold beyond which the sensitivity of the photodiode is strongly affected. This means that the anneal conditions need to be precisely monitored to avoid an excessive diffusion of cadmium into the P-doped region.

[0008] The aim of the present invention is to provide a photodetection device based on Cd x Hg 1-x Te which is sensitive to long wavelengths and which is capable of reducing the dark current and which does not have the drawbacks of the prior art. SUMMARY

[0009] This aim is achieved by a method for manufacturing a photodetection device, comprising the following steps.

[0010] a) depositing a source coating on a semiconductor substrate of Cd x Hg 1-x Te, the source coating comprising at least one cadmium-rich layer having a higher average concentration of cadmium than the semiconductor substrate, the cadmium-rich layer being in direct physical contact with the upper surface of the semiconductor substrate.

[0011] b) generating a first etching mask superimposed on the source coating on the side opposite the semiconductor substrate.

[0012] c) a first etching step: etching the source coating through the first etching mask, thereby forming at least one first through-hole in the source coating, the source coating cooperating with the at least one first through-hole being called a structured coating.

[0013] d) a second etching step: enlarging at least one second through-hole in the structure on top of the structured coating after the first etching step has been completed and thereby forming a second etching mask.

[0014] e) implanting a recipient-doping element into the semiconductor substrate through the through-holes in the second etching mask, the recipient-doping element locally passing through the structured coating.

[0015] f) activating and diffusing the recipient-doping element to form at least one P-doped region in the semiconductor substrate.

[0016] g) a selective interdiffusion annealing of cadmium, implemented after or at least partially simultaneously with step f), during which cadmium atoms diffuse from the structured coating towards the at least one P-doped region, so as to form in each P-doped region a concentrated well having at least one intermediate gap region and at least one high gap region, the average concentration of cadmium in the intermediate gap region being strictly lower than the average concentration of cadmium in the high gap region.

[0017] h) depositing a metal layer in contact with the semiconductor substrate at at least one first via in the structured coating, so as to form at least one electrical contact pad.

[0018] The basic idea of the invention is to make a photodiode based on P / N type Cd x Hg 1-x Te, wherein the P-doped region comprises a cadmium-rich concentrated well in which the cadmium concentration has a lateral gradient. As in the prior art, the average concentration of cadmium in the concentrated well is higher than the average concentration of cadmium in the N-doped region (forming a respective PN junction with each P-doped region). The average gap in the concentrated well is therefore greater than the average gap in the N-doped region. In operation, the space charge region extends at least partially in the concentrated well, which makes it possible to reduce the dark current. In each P-doped region, the concentrated well comprises at least one intermediate gap region and at least one high gap region. In operation, the space charge region extends partially in the intermediate gap region and partially in the high gap region. The average concentration of cadmium in the intermediate gap region is strictly lower than the average concentration of cadmium in the high gap region. The average gap in the intermediate gap region is therefore less than the average gap in the high gap region. The collection of charge carriers is ensured by the electrical contact pad, which is in direct physical contact with the P-doped region in the intermediate gap region. It is therefore only necessary for the average gap in the intermediate gap region not to form a barrier to the diffusion of minority charge carriers in order to make it possible to maintain the collection of charge carriers. However, the average gap in the high gap region does not hinder the diffusion of minority charge carriers. In other words, the reduction in the dark current is ensured at least by the intermediate gap region, while the collection of charge carriers is ensured at least by the intermediate gap region. In the high gap region, we are therefore freed from the difficulties associated with the trade-off between pursuing a high gap that maximizes the reduction in the dark current and a low gap that still makes it possible to collect charge carriers. Furthermore, since the average gap in the high gap region can exceed a limit threshold beyond which a barrier to minority charge carriers is formed, the average value of the gaps in the concentrated well can be increased compared with the prior art. The dark current is therefore further reduced. Finally, since the high gap region alone ensures a significant reduction in the dark current, the average gap in the intermediate gap region can be sufficiently low to ensure the proper collection of charge carriers regardless of the operating conditions (temperature, flow of photons, etc.). The proper quantum efficiency of the photodetection device according to the invention is therefore ensured.

[0019] Such a concentrated well can be obtained by covering a Cdx Hg 1-x Te semiconductor substrate and by performing a mutual diffusion anneal. During the anneal, the cadmium atoms of the structured layer will diffuse into the substrate, mainly in the P-doped region. A gradient of cadmium concentration is obtained due to the one or several through-holes in the structured layer, each of which is called a "first through-hole". As a result, the areas of the P-doped region that are opposite the through-holes in the structured layer form intermediate gap regions, while the areas of the P-doped region that are opposite the solid areas of the structured layer form high gap regions. After that, the electrical contact pads are placed and are in direct physical contact with the corresponding intermediate gap regions. The difficulty that arises is to ensure a sufficient spacing between the PN junction and the electrical contact pads on the upper surface of the semiconductor substrate, even for small dimensions of the P-doped region, in order to avoid the appearance of tunneling leakage currents.

[0020] Due to the proper alignment between the intermediate gap regions and the electrical contact pads, a sufficient spacing can be obtained. Therefore, in the present invention, a clever manufacturing method is provided that can particularly guarantee this proper alignment between the intermediate gap regions and the electrical contact pads. It comprises the use of a first etching mask configuration to form the layer of cadmium atom reservoirs (step c), and then the injection of a doping element into the semiconductor substrate through the openings of a second etching mask (step e), the second etching mask being obtained by enlarging the openings of the first etching mask or by enlarging the openings of another etching structure that penetrates the first etching mask (step d). The enlarged through-holes planned in step d) are called "second through-holes". As a result, we obtain P-doped regions that are aligned with the openings of the second etching mask, and therefore with the openings of the first etching mask, and therefore with the openings in the layer that forms the cadmium atom reservoirs. The layer that forms the cadmium atom reservoirs and that is configured by penetrating the first etching mask is called a structured coating. Then, the mutual diffusion anneal (step g) forms intermediate gap regions in the P-doped regions that are aligned with the openings in the structured coating. Therefore, the electrical contact pads that are in direct physical contact with the semiconductor substrate at the openings of the structured coating are pairwise aligned with the intermediate gap regions. By the configuration, the alignment is automatically obtained since the doping element is injected in the through-holes of the entire second etching mask obtained from the first etching mask. The proper alignment between the intermediate gap regions and the electrical contact pads avoids the appearance of leakage currents at the PN junction and also provides, when used, a proper uniformity of the polarization of the PN junction in the device.

[0021] According to an advantageous first embodiment, the method according to the invention comprises the following features:

[0022] In step b), the first etching mask is made directly on the source coating on the side opposite the semiconductor substrate; and

[0023] In step d), the structure on top of the structured coating is constituted by the first etching mask at the end of the first etching step, so that the second etching mask is formed in the material of the first etching mask.

[0024] Advantageously, the thickness of the first etching mask is adjusted so that, at the end of step d), the thickness of the second etching mask is greater than or equal to the thickness of a limit threshold below which, in step e), the acceptor doping element will pass through the second etching mask between the through-holes of the second etching mask.

[0025] According to an advantageous second embodiment, the method according to the invention further comprises, between steps a) and b), a step of depositing a sacrificial layer on the source coating and on the side opposite the semiconductor substrate, and,

[0026] In step b), a first etching mask is generated on the sacrificial layer on the side opposite the semiconductor substrate;

[0027] In step c), the sacrificial layer and the source coating are etched together through the first etching mask;

[0028] - in step d), at the end of the first etching step, the structure on top of the coating is structured from the etched sacrificial layer so that a second etching mask is formed in the material of the sacrificial layer.

[0029] The method can further comprise a step of removing the first etching mask implemented after step d) and before step e).

[0030] Preferably, in step d), the etching depth is greater than or equal to 1 pm in a radial direction parallel to the plane of the semiconductor substrate.

[0031] Advantageously, the method according to the invention further comprises a step of filling the mercury gap to form an N-doped region in the semiconductor substrate, the N-doped region forming a respective PN junction with each P-doped region.

[0032] After completion of step d), the second etching mask can comprise as many through-holes as the first etching mask.

[0033] Optionally, at step d), several second through-holes of the structure are combined to form a single through-hole so that, after completion of step d), the second etching mask comprises fewer through-holes than the first etching mask.

[0034] The invention also comprises a photodetection device having at least one pixel obtained using the method according to the invention, the device comprising:

[0035] Cd x Hg 1-x Te semiconductor substrate;

[0036] a structured coating covering the upper surface of the semiconductor substrate and provided with at least one first through-hole; and,

[0037] at least one electrical contact pad made of metal;

[0038] wherein, for each pixel, the semiconductor substrate comprises:

[0039] an N-doped region;

[0040] a P-doped region forming a PN junction with the N-doped region, being flush with the upper surface of the semiconductor substrate, and being in direct physical contact with a respective one of the at least one electrical contact pad; and

[0041] a concentration well located only in the P-doped region and wherein the average concentration of cadmium is higher than the average concentration of cadmium in the N-doped region.

[0042] in each pixel:

[0043] the P-doped region comprises a base extending from the upper surface of the semiconductor substrate and at least one protrusion protruding from the base in a direction opposite to the upper surface of the semiconductor substrate;

[0044] the concentration well has a cadmium concentration gradient in which at least one intermediate gap region and at least one high gap region are defined, wherein the average concentration of cadmium in the intermediate gap region is strictly lower than the average concentration of cadmium in the high gap region; and

[0045] each intermediate gap region is in direct physical contact with a respective one of the electrical contact pads at least at a corresponding first through-hole of the structured coating.

[0046] Preferably, each pixel comprises one single intermediate gap region and one single high gap region, the intermediate gap region being arranged concentrically to the P-doped region and being surrounded by the high gap region. BRIEF DESCRIPTION OF DRAWINGS

[0047] The application will be better understood and other aspects thereof will become more apparent when the following description, given, purely by way of illustrative and non-limiting example, will be read with reference to the enclosed drawings.

[0048] Figure 1A , 1B , 1C, 1D, 1E, 1F, 1G, 1H, 1I and 1J schematically illustrate steps of a method according to a first embodiment of the application.

[0049] Figure 2A , 2B and 2C schematically illustrate steps of a method according to a second embodiment of the application.

[0050] Figure 3 schematically illustrates a variant of the method according to the first embodiment of the application.

[0051] Figure 4A and 4BThe steps of the method according to the third embodiment of the application are schematically illustrated. DETAILED DESCRIPTION

[0052] In the following, the average concentration of cadmium refers to the average volume concentration of cadmium atoms.

[0053] For the sake of legibility, the axes of an orthogonal reference system (Oxyz) are represented in some of the figures.

[0054] Figures 1A to 1J The steps of the method according to the first embodiment of the application are illustrated for manufacturing a photodetection device having at least one pixel, wherein each pixel of the device forms a photodiode.

[0055] In a first step, as illustrated in Figure 1A , a source coating 120 is deposited on a semiconductor substrate 110.

[0056] The semiconductor substrate 110 is composed of an alloy of cadmium, mercury and tellurium of Cd x Hg 1-x Te type, with x between 0 and 1, the limits not included. In this case, it has two large faces parallel to the plane (xOy), which define respectively an upper surface 111 and a lower surface 112 of the substrate 110 (wafer-type thin substrate). Advantageously, the semiconductor substrate 110 is manufactured using epitaxy or chemical vapor deposition on a support substrate 130. For example, the support substrate 130 is a CdZnTe, silicon or germanium-based substrate, etc.

[0057] The average concentration of cadmium in the semiconductor substrate 110 is denoted xi and xi is between 0.15 and 0.7, more preferably xi is between 0.18 and 0.6, for example xi = 0.3. These concentrations are adapted to the absorption of wavelengths from the near infrared to the far infrared.

[0058] The semiconductor substrate 110 also comprises a donor-type doping element, for example indium, with a concentration between 10 13 / cm -3 and 10 17 / cm -3 , for example 10 15 / cm-3.

[0059] In this case, the concentration of cadmium is uniform throughout the semiconductor substrate 110, as is the concentration of the donor doping element. Alternatively, the semiconductor substrate 110 can be composed of a plurality of Cd x Hg 1-xThe Te layer is composed, and each layer has a different average cadmium concentration value, for example so that the photodiode is sensitive in different wavelength ranges. In addition or alternatively, the concentration of the donor-type doping element can vary in the semiconductor substrate 110, for example to make a photodiode with improved collection or noise characteristics.

[0060] The source coating 120 is deposited directly on the semiconductor substrate, for example by physical vapor deposition, chemical vapor deposition or molecular jet. The source coating 120 comprises at least one cadmium-rich layer, in the region of which the average cadmium concentration is higher than the average cadmium concentration of the semiconductor substrate 110, flush with its upper surface 111. Preferably, the average cadmium concentration in the cadmium-rich layer is higher than the average cadmium concentration throughout the semiconductor substrate 110. In this case, the cadmium-rich layer is made of CdTe. Alternatively, the cadmium-rich layer can be made of Cd x Hg 1-x Te, with an average cadmium concentration denoted x2, and x2-x1≥0.1. The cadmium-rich layer extends in the direction of direct physical contact with the semiconductor substrate 110, in this case over the entire upper surface 111 of the semiconductor substrate 110. For example, the thickness of the cadmium-rich layer is between 50 nm and 500 nm, for example 200 nm. In this case, the source coating 120 is composed of this unique cadmium-rich layer. Alternatively, the source coating 120 is composed of a stack of multiple layers including the cadmium-rich layer.

[0061] In a second step, as shown in Figure 1B , a first etching mask 140 is made on the source coating 120. In this case, the first etching mask 140 extends directly on the source coating 120, in direct physical contact with the source coating 120 on the side opposite the semiconductor substrate 110. The first etching mask 140 comprises through-holes 141, each of which extends along an axis (Oz) and through the thickness of the entire first etching mask 140. In this case, the through-holes 141 have a disc-shaped cross-section in a plane parallel to the plane (xOy), the diameter of the disc increasing slightly as it approaches the source coating 120. For example, at the interface between the first etching mask 140 and the source coating 120, the diameter of the through-holes 141 is 2 pm. The through-holes 141 can be other shapes without departing from the scope of the invention. The first etching mask 140 can be made by depositing a layer of photosensitive resin on the source coating 120, then etching the resin layer to form the through-holes 141 therein by photolithography.

[0062] At each step of its manufacture, a pixel can be defined in the photodetection device according to the invention. In this case, for each pixel, there is a through-hole 141 of the first etching mask. In the figures, the pixels are separated by vertical dashed lines.

[0063] In a third step, as shown in Figure 1CAs shown, the source coating 120 is etched through the via 141 of the first etching mask 140 to form a via 121 in the source coating 120, the via 121 being referred to as "first via", each via extending along the axis (Oz) and through the whole thickness of the source coating 120. The source coating provided with the via 121 is referred to as structured coating 122. This step forms a first etching step, which can implement a dry etching or a wet etching, with or without reaction, or a combination of these techniques. Preferably, the first etching step implements a dry etching by ion milling. The first etching step keeps the diameter of the via 141 of the first etching mask 140 substantially unchanged. In this case, the first etching step also etches the semiconductor substrate 110 on the surface (through a thickness of less than 1000 nm, for example 200 nm). The first etching step also causes a slight reduction in the thickness of the first etching mask 140.

[0064] The first etching step allows to manufacture the structured coating 122 forming a reservoir of cadmium, the structured coating 122 being provided with the via 121, each via 121 being aligned with a corresponding via 141 of the first etching mask 140. The pairs of aligned and respectively belonging to the structured coating 120 and to the first etching mask 140, the via 121 and 141 have substantially the same shape and the same dimensions in a plane parallel to the plane (xOy).

[0065] In a fourth step, as shown in Figure 1D and 1E , the first etching mask 140 is etched to enlarge the via 141 of the first etching mask 140 and thereby form a second etching mask 150 from the first etching mask 140. The via 141 of the first etching mask is then referred to as "second via". In Figure 1D , a cross-sectional view of the arrangement obtained when this second etching step is completed is shown, in which the shape of the first etching mask 140 before this second etching step is represented in dotted lines. In Figure 1E , a top view of the arrangement is shown.

[0066] Thus, the second etching step manufactures the second etching mask 150, in which the via 151 of the second etching mask 150 is aligned in pairs with the via 141 of the first etching mask 140, and the via 151 of the second etching mask 150 is larger than the via 141 of the first etching mask 140. Thus, the via 121 of the structured coating 122 is aligned in pairs with the via 151 of the second etching mask 150, and the via 151 of the second etching mask 150 is larger than the via 121 of the structured coating 122. Thus, on each side of the via 151 of the second etching mask 150, there is a region of the surface of the semiconductor 110 exposed, surrounded by a region of the surface exposed by the material of the structured coating 122 (see Figure 1E ).

[0067] The second etching step implements a selective etching of the material of the structured coating 122 which is not etched. This second etching step can implement a reactive dry etching, for example an oxygen-based plasma etching with the addition of Ar, CF4, HBr, Cl2or a combination of these additives. The second etching step can comprise an isotropic etching, in which the vertical extent of the etching (the etching depth according to the axis (Oz)) is equal to the lateral extent of the etching (the radial etching depth lying in the plane (xOy), orthogonal to the tangent to the edge of the through-hole 141 of the first etching mask). Alternatively, the method according to the application can be adapted so that, during the second etching step, the lateral extent of the etching is strictly greater than the vertical extent of the etching, by a factor of between, for example, 1.2 and 2. Thus, for the same width of the through-hole 151 of the second etching mask 150, the reduction in the thickness of the first etching mask 140 brought about by the second etching step can be limited. This etching property can be obtained by hardening of the upper surface of the first etching mask 140, for example by the implementation of an ion flux bombarding the upper surface of the first etching mask during the plasma etching process of the second etching step. Alternatively, this property can be obtained by the deposition of a precursor on the upper surface of the first etching mask 140, thus slowing down the vertical chemical etching.

[0068] In Figure 1D the etching vertical extent e v and the etching radial extent e h of the second etching mask 150 is shown, which has been reduced with respect to the thickness of the first etching mask by the etching vertical extent e v .

[0069] In Figure 1F the fifth step shown, the through-hole 151 of the second etching mask 150, the acceptor doping elements are implanted into the semiconductor substrate 110. For example, the acceptor doping elements consist of arsenic atoms and are implanted by ion implantation at an energy of 400 keV and a dose of 5.1014 / cm-3. After the step of activation and diffusion of the implanted doping elements, they form P-doped regions 160 in the semiconductor substrate.

[0070] The implanted doping elements opposite the solid regions of the second etching mask 150 do not reach the semiconductor substrate 110. To this end, the thickness e1 of the second etching mask 150 must remain greater than or equal to a predetermined threshold. We understand here the relevance of limiting the reduction in the thickness of the first etching mask 140 during the preceding steps. In particular, the thickness e1 must remain greater than or equal to a threshold below which the implanted doping elements opposite the solid regions of the second etching mask 150 would pass through the entire thickness of the second etching mask 150. For example, under the implantation conditions described above, this threshold is 0.8 pm.

[0071] Furthermore, in the regions of the material exposed surface of the structured coating 122 opposite the through-holes 151 of the second etch mask, the implanted dopant elements sink to a first depth P1 in the semiconductor substrate 110.

[0072] Finally, in the regions of the material exposed surface of the semiconductor substrate 110 opposite the through-holes 151 of the second etch mask, the implanted dopant elements sink to a second depth P2 in the semiconductor substrate 110, with P2 strictly greater than P1. To this end, the thickness of the structured coating 122, and thus also of the source coating 120, must remain less than or equal to a predetermined threshold. This predetermined threshold depends on the nature of the implanted dopant elements and the implantation energy. In this case, the thickness of the structured coating 122 is 200 nm, so that arsenic atoms implanted with an energy of 400 keV are able to reach the semiconductor substrate 110.

[0073] Thus, P-doped regions are obtained, each having a base 163 extending from the upper surface 111 of the semiconductor substrate 110 and a protrusion 164 protruding from the base in a direction opposite the upper surface 111 of the semiconductor substrate. The width of the base 163 is defined by the width of the corresponding through-hole 151 in the second etch mask 150. The width of the protrusion 164 is defined by the width of the corresponding through-hole 121 in the structured coating 122. In this case, each P-doped region 160 is centered on the corresponding through-hole 151 of the second etch mask 150 and the corresponding through-hole 121 of the structured coating 122. In each P-doped region, the corresponding through-hole 121 of the structured coating 122 covers a central region, and the material of this structured coating 122 covers a peripheral region. Each P-doped region is associated with a corresponding pixel of the photodetector device being manufactured.

[0074] In a sixth step, as shown in Figure 1G and 1H a selective interdiffusion anneal of cadmium is performed, during which cadmium atoms of the structured coating 122 diffuse towards the semiconductor substrate 110. Preferably, this anneal comprises a high-temperature anneal phase, at a temperature between 100 and 500°C, more preferentially between 300 and 500°C, even between 350 and 450°C, and for a duration longer than 1 minute, preferentially between 10 minutes and 50 hours, more preferentially between 30 minutes and 50 hours, even between 30 minutes and 30 hours, for example 1 hour.

[0075] During this anneal, cadmium preferably diffuses in the P-doped regions 160. We thus discuss a selective interdiffusion. As a result, a distribution of cadmium in the semiconductor substrate 110 is obtained, with a high average concentration of cadmium in the P-doped regions 160 of each pixel. In each pixel, the concentration of cadmium decreases rapidly in an intermediate region 185 extending at the interface between the P-doped region 160 and the rest of the semiconductor substrate (this interface corresponds to the future PN junction). This intermediate region 185 can extend on either side of the future PN junction. Preferably, this intermediate region 185 extends on both sides of the future PN junction. Thus, a respective concentration well 180 can be defined in each P-doped region, with an average concentration of cadmium higher than the average concentration of cadmium in the rest of the semiconductor substrate 110. Each concentration well 180 extends only inside the corresponding P-doped region 160, and thus does not necessarily include the intermediate region 185. Each concentration well 180 and the corresponding P-doped region 160 are arranged concentrically. In the following, we consider that each concentration well 180 is exactly superimposed on the corresponding P-doped region 160.

[0076] The cadmium diffuses from the covered surface between the P-doped regions 160 and the structured coating 122 into the P-doped regions 160. Thus, in each P-doped region 160, the concentration well 180 has a lateral gradient of cadmium. In the concentration well 180, the concentration of cadmium is maximum at the opposite face of the covered surface between the P-doped region 160 and the structured coating 122, then decreases when moving away from this covered surface. Thus, an intermediate gap region can be defined in the concentration well 180, surrounded by a high gap region.

[0077] In Figure 1H , a detailed view of the arrangement obtained at the end of the interdiffusion anneal is shown, as well as the corresponding curve of the cadmium concentration x along an axis AA' parallel to the plane (xOy) and passing through the doped region P. Therein, the cadmium concentration exhibits the following phenomena:

[0078] a low value xi outside the P-doped region and the intermediate region 185, and

[0079] a high value x h .

[0080] As mentioned above, the region from the low value xi to the abrupt transition to the high value x h corresponds to the intermediate region 185. The high value x h is strictly higher than the low value xi, preferably xi h ≥ (xi + 0.1). Furthermore, the high value x h is advantageously 1.5 to 5 times higher than xi. There is no restrictive limit to limit the maximum value assigned to x h , which can reach x h = 0.95.

[0081] Relative to the opening 121 of the structured coating 122, the cadmium concentration ranges from a high value x h Gradually changing downwards to the median value x m The median value x m Strictly below x h Preferably, the intermediate value x m Further satisfy x ab ≤x m ≤

[0082] (x ab +0.1), where x ab This refers to the cadmium concentration in the region of the semiconductor substrate 110 specifically designed for absorbing incident photons. For simplicity, x1 can be considered as x ab The intermediate gap region can be defined as the volume 181 in the concentration trap 180 opposite the through-hole 121 in the structured coating 122. Similarly, the high gap region can be defined as the volume 182 in the concentration trap opposite the solid region of the structured coating 122.

[0083] In operation, in the resulting photodetector, each P-doped region defines a PN junction with the remainder of the semiconductor substrate 110, and a space charge region extends on either side of this PN junction, partially extending into the enrichment trap 180. An N-doped region of the semiconductor substrate forms an absorption region dedicated to absorbing incident photons. The wavelength of the absorbed photons depends on the gaps in the N-doped region. Due to the high average cadmium concentration in the enrichment trap 180, the photodetector can detect long-wavelength photons while exhibiting reduced dark current. In each P-doped region, charge carrier collection occurs at the intermediate gap region 181. Therefore, the potential barrier that may exist at the high gap region 182 does not hinder efficient charge carrier collection. Thus, compared to the prior art, it is possible to increase the average value of the gaps in the space charge region and therefore further reduce the dark current even for the same spectral sensitivity range.

[0084] Remove the second etch mask 150 during or before the annealing process. Then, in Figure 1I In the seventh step shown, the obtained arrangement is covered with, for example, a metal layer 170 deposited by evaporation. The metal layer 170 may consist of a single layer or multiple layers stacked together, and may include one or more elements such as gold, titanium, nickel, or metal alloys. The metal layer 170 covers the structured coating 122 and penetrates the interior of the vias 121 in the structured coating 122. Therefore, the metal layer 170 only has direct physical contact with the P-doped region at the vias 121 in the structured coating, opposite the intermediate gap region.

[0085] exist Figure 1JIn the eighth step shown, the metal layer 170 is locally etched, for example by lithography and etching, to define the electrical contact pads 171.

[0086] As an alternative to the seventh and eighth steps, the metal layer is deposited on the mask formed on the structured coating, then the mask is removed, so as to leave only the electrical contact pads (so-called lift-off technique).

[0087] In all cases, the electrical contact pads are thus made with a narrow contact surface between the electrical contact pads and the P-doped regions, and are automatically aligned on the intermediate gap region. The efficient collection of charge carriers is thus ensured in operation. Furthermore, sufficient spacing between the electrical contact pads and the PN junction is ensured, preventing the appearance of tunnel leakage currents.

[0088] In the second etching step (see Figure 1D and 1E ), the spacing between the electrical contact pads and the PN junction is defined by the radial extent e h (or the etching depth in the radial direction parallel to the plane (xOy) of the semiconductor substrate 110) of the etching. Preferably, this radial extent e h is greater than or equal to 1 pm, even greater than or equal to 1.5 pm, for example equal to 2 pm. In other words, in the second etching step, the at least one via is enlarged such that its diameter increases by at least 2 pm, even by at least 3 pm, for example by 4 pm (where the diameter of the via is the maximum width of the section of the via in the plane (xOy) parallel to the plane of the semiconductor substrate).

[0089] This radial extent e h also defines the size of the exchange surface between the solid region of the structured coating 122 and the P-doped region, and thus the radial extent e h also relates to the curve that defines the gap gradient in the concentration well and the maximum threshold of the gap in the concentration well.

[0090] The method according to the application also comprises an annealing step (not shown) at low temperature under saturated mercury vapor pressure, which fills the mercury gap formed in the semiconductor substrate 110 and forms the corresponding PN junction between the P-doped region 160 and the rest of the semiconductor substrate 110. This annealing can be implemented after the selective interdiffusion annealing of cadmium. Alternatively, this annealing can form the final low-temperature stage of the selective interdiffusion annealing of cadmium. The low-temperature annealing is carried out at a temperature of, for example, between 150°C and 200°C.

[0091] Similarly, the steps of activating and diffusing the acceptor-doped elements of the aforementioned implantation can be implemented before or at least partially during the selective interdiffusion annealing of cadmium.

[0092] Hybridization on the reading circuit, optional removal of the support substrate, subsequent steps of deposition of optical functions such as anti-reflection layers and / or filters on the front face, although not described, can be implemented without departing from the scope of the application.

[0093] In an advantageous embodiment, the first etching mask 140 has a thickness of 3 μιη and has circular through-holes with a diameter of 2 μιη, uniformly distributed in the plane (xOy) with a distribution step equal to 10 μιη. In the first etching step, the source coating is etched by ion milling to form the structured coating. This first etching step also reduces the thickness of the first etching mask 140. For example, the first etching step etches the through-holes in the source coating having a thickness of 0.2 μιη and causes a reduction in the thickness of the first etching mask 140 of 0.2 μιη. Then, the first etching mask is etched with a double oxygen plasma, with an etching range of 2 μιη in all directions. Thus, a second etching mask 150 having a thickness of 0.8 μιη is obtained, with circular through-holes having a diameter of 6 μιη, with a distribution step equal to 10 μιη. The thickness of the second etching mask 150 is sufficient to stop the implantation of arsenic, which is implanted by ion implantation with an energy of 400 keV and a dose of 5.1014 / cm"3. In the final photodetector device, the spacing between the edge of the electrical contact pad 171 and the edge of the PN junction is thus greater than or equal to 2 μιη in the plane of the upper surface 111 of the semiconductor substrate.

[0094] Figure 1J A photodetector device 100 obtained using the method described above is shown. The photodetector device 100 comprises a Cd x Hg 1-xThe semiconductor substrate 110 is of Te. The structured coating comprises at least one cadmium-rich layer in direct physical contact with the semiconductor substrate 110. Even after interdiffusion annealing, the average concentration of cadmium in the cadmium-rich layer is higher than the average concentration of cadmium in the semiconductor substrate 110 (cadmium having diffused only in a portion of the semiconductor substrate). In each pixel of the device 100, the corresponding P-doped region 160 extends in the semiconductor substrate 110 and defines a PN junction with the rest of the semiconductor substrate 110. As previously described, each P-doped region comprises a base 163 and a protrusion. Each protrusion 164 is aligned with a corresponding via 121 of the structured coating 122 and has substantially the same cross-section as this via 121 in a plane parallel to the plane (xOy). The volume of the protrusion 164 is strictly less than the volume of the base 163. As previously described, each P-doped region 160 receives a corresponding condensed well 180 having a high-gap region and an intermediate-gap region. In this case, the intermediate-gap region is arranged concentrically with the P-doped region 160 and is surrounded by the high-gap region. The intermediate-gap region is in direct physical contact with the corresponding electrical contact pad 171 at the corresponding via 121 of the structured coating. At the upper surface 111 of the semiconductor substrate 110, the edge of the electrical contact pad 171 is spaced apart from the PN junction defined by the P-doped region 160.

[0095] In each pixel, the distance between the edge of the via 121 in the structured coating and the edge of the PN junction, in the plane of the upper surface 111 of the semiconductor substrate 110 and in a radial direction, is advantageously greater than or equal to a threshold value D. In this case, the radial direction is the direction orthogonal to the tangent of the edge of the via 121 in the plane of the upper surface 111 of the semiconductor substrate 110. Similarly, the distance between the edge of the PN junction and the edge of the electrical contact pad 171, in the plane of the upper surface 111 of the semiconductor substrate 110 and in a radial direction, is advantageously greater than or equal to the threshold value D. The threshold value is preferably 1.0 pm, 1.5 pm, or even 2.0 pm. Similarly, the distance between the edge of the base 163 and the edge of the protrusion 164, in the orthogonal projection of the P-doped region 160 in a plane parallel to the plane (xOy), is advantageously greater than or equal to the threshold value D.

[0096] The method according to the application thus allows the manufacture of photodetection devices having a low noise level. The method simplifies the number of manufacturing steps, which improves the robustness of the manufactured devices and increases the manufacturing productivity.

[0097] The structured coating 122 forms a passivation layer protecting the semiconductor substrate 120. In the method according to the application, the P-doped regions 160 are produced after etching the through-holes 121 of the structured coating. Thus, interface state constraints are limited, which allows the through-holes 121 to be etched by means of a very precise etching process, for example an anisotropic dry etching process. Thus, it is possible to reduce the contact surface between the electrical contact pads and the corresponding P-doped regions and to reduce the pixel pitch of the device according to the application.

[0098] Figures 2A to 2C The steps of the method according to the second embodiment of the application are shown and will only be described with respect to their differences from the method according to the first embodiment of the application. In this second embodiment, the method comprises the following steps:

[0099] A sacrificial layer 290 is deposited on the source coating and on the side opposite the semiconductor substrate 210. In this case, the sacrificial layer 290 is in direct physical contact with the source coating over its entire extent in the plane (xOy).

[0100] As previously described, in this case, a first etching mask 240 is produced on the sacrificial layer 290 on the side opposite the semiconductor substrate 210. In this case, the etching mask 240 is in direct physical contact with the sacrificial layer 290.

[0101] Through-holes 241 through the first etching mask 240, the sacrificial layer 290 and the source coating are jointly etched (see Figure 2A ). This first etching step forms through-holes 291 in the sacrificial layer 290, wherein the through-holes 241 of the first etching mask 240 and the through-holes 291 of the sacrificial layer 290 are pairwise aligned and have substantially the same width. This first etching step further forms a structured coating 222 as previously described, wherein the through-holes of the structured coating 222 and the through-holes 291 of the sacrificial layer 290 are pairwise aligned and have substantially the same width.

[0102] A second etching step for enlarging the through-holes 291 of the sacrificial layer 290 (see Figure 2B ). The through-holes 291 of the sacrificial layer 290 are then referred to as "second through-holes". The sacrificial layer, whose through-holes are enlarged, forms a second etching mask 250 as previously described. For example, the sacrificial layer is made of SiO2and is etched by wet etching in a hydrofluoric acid-based acid solution.

[0103] After removal of the first etching mask 240, through-holes are made through the second etching mask and acceptor-doped elements are implanted as previously described Figure 2C .

[0104] These steps are followed by the previously described steps of cadmium-selective interdiffusion annealing, removal of the second etching mask and production of the electrical contact pads.

[0105] The dimensions of the second etch mask must meet the same requirements as in the first embodiment. In particular, the thickness of the sacrificial layer 290 must be sufficient to prevent the implanted acceptor doping element from reaching the semiconductor substrate 210. For an arsenic ion implantation of 400 keV, a sacrificial layer made of Si02 with a thickness greater than or equal to 500 nm can be used, for example.

[0106] In the second etching step, the sacrificial layer 290 intended to form the second etch mask is etched only in the radial direction. The extent of the etching in the radial direction can be easily adjusted, in particular by the duration of the contact with the acid solution and / or the acid concentration. In the vertical direction, the sacrificial layer is protected by the first etch mask, so that its thickness remains unchanged. Thus, the second embodiment facilitates the adjustment of the dimensions of the through-holes of the second etch mask.

[0107] Figure 3 A variant of the method according to the first embodiment of the application is illustrated, in which the etching source coating (first etching step) does not etch the material of the semiconductor substrate 310. The upper surface 311 of the semiconductor substrate remains flat overall. This fully selective etching can also be achieved in the variant of the method according to the second embodiment of the application.

[0108] Figure 4A and 4B The steps of the method according to the third embodiment of the application are illustrated schematically. Only the differences of this embodiment with respect to the first embodiment will be described. In this embodiment, the first etch mask comprises, for each pixel of the photodetector device, a plurality of through-holes. The etching source coating is formed so as to form a structured coating 422 having as many through-holes as the first etch mask. Thus, the structured coating 422 comprises, in each pixel, a plurality of through-holes 421.

[0109] In the second etching step, in each pixel, the several through-holes of the structure at the top of the structured coating are combined to form a single through-hole. In this case, the structure is formed by the first etch mask. Alternatively, as in the embodiment of Figures 2A to 2C it can be formed by a sacrificial layer. Thus, the second etching step forms a second etch mask 450, and there is one through-hole per pixel of the photodetector device. Thus, in the photodetector device finally obtained, the P-doped region comprises several protrusions, each protrusion being opposite a respective through-hole of the structured coating. In addition, the concentration well of each P-doped region comprises several intermediate doped areas, each intermediate doped area being opposite a respective through-hole of the structured coating. Finally, in each pixel, the electrical contact pad comprises several excrescences, each excrescence being in contact with a respective intermediate doped area through a respective through-hole of the structured coating. This embodiment ensures optimal collection of charge carriers and provides an appropriate modulation transfer function.

[0110] The invention is neither limited to arsenic as acceptor-doping element nor to the implantation energies and doses mentioned in the examples. Other acceptor-doping elements such as Li, Na, K, Rb, Cs, Ag, Au, Cu, N, P, Sb, etc. can be used in particular, and the implantation energy is advantageously between 50 keV and 1000 keV for structured coatings with a thickness between 50 nm and 1000 nm. Similarly, the invention is not limited to the dimensions and materials mentioned as examples. It is neither limited to one shape nor to the number of through-holes per pixel in the structured coating. For example, it is possible that each pixel in the structured coating has one annular through-hole, and thus a P-doped region with an annular protrusion and a concentration well with an annular intermediate gap region.

[0111] The invention thus provides a method for manufacturing at least one low-noise P / N photodiode. In each pixel, the contact surface between the electrical contact made of metal and the P-doped region is automatically aligned with the intermediate gap region dedicated to the collection of charge carriers in the P-doped region by its structure alone. Preferably, the electrical contact is centered on the P-doped region by its structure alone. The invention is particularly suitable for the manufacture of matrix-type photodetection devices with a distribution step of the pixels less than or equal to 10 pm.

Claims

1. A method for manufacturing a photoelectric detection device (100), comprising the following steps: a) In Cd x Hg 1-x A source coating (120) is deposited on a semiconductor substrate (110, 210, 310) of Te, the source coating comprising at least a cadmium-rich layer having a higher average cadmium concentration than the semiconductor substrate, the cadmium-rich layer being in direct physical contact with the upper surface (111, 311) of the semiconductor substrate. b) Generate a first etch mask (140, 240) superimposed on the source coating on the side opposite to the semiconductor substrate; c) First etching step: Etching the source coating through the first etching mask to form at least one first via (121) in the source coating, the source coating cooperating with at least one first via is referred to as a structured coating (122, 222, 422); d) Second etching step: After completing the first etching step, at least one second through hole (141, 291) is enlarged in the structure (140, 290) on top of the structured coating (122, 222), thereby forming a second etching mask (150, 250, 450). e) By penetrating a via (151) in the second etch mask (150, 250, 450), an acceptor dopant element is implanted into the semiconductor substrate (110, 210, 310), the acceptor dopant element partially penetrating the structured coating. f) Activate and diffuse the acceptor doping element to form at least one P-doped region (160) in the semiconductor substrate; g) Selective interdiffusion annealing of cadmium is performed after or at least partially concurrently with step f), during which cadmium atoms diffuse from the structured coating into the at least one P-doped region, thereby forming a concentration trap (180) in each P-doped region having at least one intermediate gap region (181) and at least one high gap region (182), wherein the average concentration of cadmium in the intermediate gap region is strictly lower than the average concentration of cadmium in the high gap region; and h) Deposit a metal layer (170) in contact with the semiconductor substrate (110, 210, 310) at at least one first via in the structured coating to form at least one electrical contact pad (171).

2. The method according to claim 1, wherein, In step b), the first etch mask (140) is fabricated directly on the source coating (120) on the side opposite to the semiconductor substrate (110); and In step d), upon completion of the first etching step, the structure on top of the structured coating (122) is formed by the first etching mask (140), such that the second etching mask (150) is formed in the material of the first etching mask.

3. The method according to claim 2, wherein, The thickness of the first etch mask (140) is adjusted such that when step d) is completed, the thickness of the second etch mask (150) is greater than or equal to a limit threshold thickness, below which, in step e), the acceptor dopant element will pass through the second etch mask between the vias of the second etch mask.

4. The method according to claim 1, further comprising: Between steps a) and b), a sacrificial layer (290) is deposited over the source coating and on the side opposite to the semiconductor substrate (210), wherein, In step b), a first etch mask (240) is formed on the side opposite to the semiconductor substrate, above the sacrificial layer (290); In step c), the sacrificial layer and the source coating are etched together through the first etch mask; In step d), after the first etching step is completed, the structure on top of the structured coating (222) is composed of the etched sacrificial layer, such that the second etching mask (250) is formed in the material of the sacrificial layer.

5. The method of claim 4, further comprising the step of removing the first etch mask (140, 240) after step d) and before step e).

6. The method according to claim 1, wherein, In step d), the etching depth is greater than or equal to 1 μm in the radial direction parallel to the plane of the semiconductor substrate.

7. The method of claim 1, further comprising the step of filling the mercury gap to form an N-doped region in the semiconductor substrate (110, 210, 310), the N-doped region forming a corresponding PN junction with each P-doped region (160).

8. The method according to claim 1, wherein, After step d), the second etch mask (150, 250) includes the same number of vias as the first etch mask (140, 240).

9. The method according to claim 1, wherein, In step d), a plurality of second vias of the structure are combined to form a single via, such that after step d), the second etch mask (450) includes fewer vias than the first etch mask.

10. A photoelectric detection device (100) having at least one pixel, obtained by using the method of claim 1, the device comprising: Cd x Hg 1-x Te semiconductor substrates (110, 210, 310); A structured coating (122, 222) covers the upper surface (11, 311) of the semiconductor substrate and is provided with at least one first through-hole (121); as well as At least one electrical contact pad (171) made of metal; For each pixel, the semiconductor substrate comprises: N-doped region; A P-doped region (160) forming a PN junction with the N-doped region, flush with the upper surface (111, 311) of the semiconductor substrate, and in direct physical contact with a corresponding electrical contact pad in at least one electrical contact pad (171); and A concentration trap (180) located only in the P-doped region, wherein the average concentration of cadmium is higher than that in the N-doped region; In each pixel: The P-doped region (160) includes a substrate (163) extending from the upper surface (111, 311) of the semiconductor substrate and at least one protrusion (164) protruding from the substrate in a direction opposite to the upper surface of the semiconductor substrate. The concentration trap (180) has a cadmium concentration gradient, defining at least one intermediate gap region (181) and at least one high gap region (182) within the cadmium concentration gradient, wherein the average cadmium concentration in the intermediate gap region is strictly lower than the average cadmium concentration in the high gap region; and At least at one corresponding first through-hole (121) of the structured coating (122, 222), each intermediate gap region (181) is in direct physical contact with the corresponding electrical contact pad (171).

11. The photoelectric detection device according to claim 10, wherein, Each pixel includes a single intermediate gap region and a single high gap region, the intermediate gap region being concentrically arranged with the P-doped region and surrounded by the high gap region.

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