Sampling-and-Hold-Based Retimer Supporting Link Training

Abstract

A linear retimer (300) includes an equalizer (310), a clock recovery circuit (315), a sample and hold (S / H) circuit (320), and a linear driver (370). The equalizer receives an input signal (305) and outputs an equalized signal. The clock recovery circuit receives the equalized signal and outputs a clock signal (330). The S / H circuit receives the equalized signal and the clock signal, and outputs a retimed signal. The linear driver receives the retimed signal and outputs a recovered signal (375). The S / H circuit is configured to hold the voltage of the equalized signal in the retimed signal. In some examples, the S / H circuit is part of a three-tap feedforward equalizer, and the linear driver receives the output of the feedforward equalizer. The linear retimer can be placed between a transmitter and a channel or after the channel.

Description

BACKGROUND OF THE INVENTION

[0001] Wired communication systems use link training to tune finite impulse response (FIR) filters in transmitters and receivers. However, non-linear retimers cannot pass link training information directly from input to output. Instead, a digital signal processor detects the FIR coefficients of the transmitter from the input signal and reconstructs them in the retimer output signal. Complex signal processing consumes a large amount of power. SUMMARY OF THE INVENTION

[0002] A retimer includes an equalizer, a clock recovery circuit, a sample and hold (S / H) circuit, and a linear driver. The equalizer receives an input signal and outputs an equalized signal. The clock recovery circuit receives the equalized signal and outputs a clock signal. The S / H circuit receives the equalized signal and the clock signal, and outputs a retimed signal. The linear driver receives the retimed signal and outputs a recovered signal. The S / H circuit is configured to hold the voltage of the equalized signal in the retimed signal. The retimer can be placed between the transmitter and the channel or after the channel.

[0003] In some examples, the S / H circuit is part of a three-tap feed-forward equalizer, and the linear driver receives the output of the feed-forward equalizer. In some examples, the S / H circuit is a first S / H circuit, and the retimed signal is a first retimed signal. The three-tap FFE may include a second S / H circuit, a third S / H circuit, a first amplifier, a second amplifier, a third amplifier, and an adder. The second S / H circuit and the first amplifier receive the first retimed signal. The second S / H circuit outputs a second retimed signal, and the first amplifier outputs a first weighted signal. The third S / H circuit and the second amplifier receive the second retimed signal. The third S / H circuit outputs a third retimed signal, and the second amplifier outputs a second weighted signal. The third amplifier receives the third retimed signal and outputs a third weighted signal. The adder receives the first, second, and third weighted signals and combines them to obtain an FFE output signal.

[0004] In some examples, the S / H circuit includes two track and hold (T / H) circuits. One of the T / H circuits may include a preamplifier and a switched emitter follower. In some examples, the preamplifier includes a degeneration capacitor having a capacitance selected to extend the bandwidth of the preamplifier. In some examples, the T / H circuit includes a feed-forward capacitor coupled between the preamplifier and the switched emitter follower. The capacitance of the feed-forward capacitor may be selected to reduce hold-mode feedthrough. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] A detailed description of various examples will now be made with reference to the accompanying drawings, in which:

[0006] Figure 1 An example communication system incorporating a non-linear retimer is described.

[0007] Figure 2 An example communication system incorporating a linear retimer is described.

[0008] Figure 3 A block diagram of an example linear retimer having a sample-and-hold circuit is described.

[0009] Figure 4 A block diagram of an example linear retimer having a three-tap feed-forward equalizer is described.

[0010] Figure 5 An example track-and-hold amplifier for use in a sample-and-hold circuit is described. Detailed Description

[0011] The disclosed retimer includes a sample-and-hold (S / H) circuit for retiming a received signal, which preserves link training information during jitter in the retimed signal. Any suitable S / H circuit can be used. The transmitter finite impulse response (FIR) coefficients are passed directly from the input of the disclosed retimer to the output without any complex digital signal processing. The retimer can be placed before or after the channel. A discrete-time linear feed-forward equalizer can be implemented by cascading S / H circuits with weighted adders to reduce both precursor and postcursor inter-symbol interference.

[0012] Figure 1 An example communication system 100 incorporating a non-linear retimer 130 having a D flip-flop 140 is described. The communication system 100 includes a transmitter 110, a non-linear retimer 130, and a receiver 150. A signal Vin 105 is provided to the transmitter 110 including a finite impulse response (FIR) filter 115. The FIR filter 115 adds link training information to the signal 120 output by the transmitter 110, as shown in signal diagrams 120A to B, which represent the voltage of the signal 120 at time t1 and the voltage of the signal 120 at time t2, respectively. The non-linear retimer 130 includes an equalization module 135 and a D flip-flop 140. The D flip-flop 140 limits the voltage of the signal 120 and cannot pass the link training information to the signal 145 output from the non-linear retimer 130.

[0013] The signal diagram 145A illustrates a constant voltage of the signal 145 at time t1, contrary to the varying voltage of the signal 120 at time t1 shown in the signal diagram 120A. The signal diagram 145B illustrates a constant voltage of the signal 145 at time t2, contrary to the varying voltage of the signal 120 at time t2. As illustrated in the signal diagrams 145A to B, the voltage of the signal 145A at time t1 is the same as the voltage of the signal 145B at time t2, masking the link training information injected into the signal 120 by the FIR 115 in the transmitter 110. The signal 145 is provided to the receiver 150 of the output signal Vout 155. The receiver 150 cannot recover the link training information in the signal 120 from the FIR 115 in the transmitter 110. A digital signal processor and a second FIR filter may be included in the non-linear retimer 130 to detect the link training information and reconstruct it at the second FIL filter, as described in U.S. Patent No. 9,210,008. However, the digital signal processor and the second FIR filter cause the non-linear retimer 130 to consume a large amount of power.

[0014] Figure 2 Illustrate an example communication system 200 including a linear retimer 230 and a sample and hold (S / H) circuit 240. The communication system 200 is generally similar to Figure 1 the communication system 100 shown in, but includes a linear retiming timer 230 instead of the non-linear retimer 130. The linear retimer 230 includes an S / H circuit 240 as a retiming element instead of a flip-flop (such as the D flip-flop 140). The S / H circuit 240 is transparent to link training and can reliably transmit the transmitter FIR information without complex digital processing, while still retiming jitter, making the linear retimer 230 consume less power than the non-linear retimer 130. Additionally, since it is linear, the retimer 230 can be placed before or after the channel, enabling the transmitter FIR filter 115 to equalize the channel before and after the linear retimer 230.

[0015] The signal 245 output from the linear retimer 230 is represented by the signal diagram 245A to B, which illustrates the voltage variations of the signal 245A at time t1 and the signal 245B at time t2, compared to the constant voltage of the signal 145 output from the non-linear retimer 130. The receiver 150 receives the signal 245 from the linear retimer 230 and outputs the signal Vout 255. As illustrated by the signal diagram 245A to B, the receiver 150 is capable of preserving the voltage variations of the signal 120 output from the transmitter 110 in the output signal 255. Although the examples shown herein include signals having two voltage levels, the S / H circuit 240 linearly transfers voltage information, and the linear retimer 230 can also be extended to signals having three, four, or more voltage levels.

[0016] Figure 3 Block diagram illustrating an example linear retimer 300 having a sample and hold circuit 320. The linear retimer 300 includes an equalizer 310, a clock and data recovery module 315, an S / H circuit 320, and a linear driver 370. The equalizer 310 can be any suitable equalizer, such as a continuous time linear equalizer. In this example, the S / H circuit 320 includes two track and hold (T / H) amplifiers 325 and 350. The T / H amplifier 325 includes a switch 335 and a capacitor 340, and the T / H amplifier 350 includes a switch 360 and a capacitor 365. In the T / H amplifier 325, the switch 335 receives the clock signal CK 330 from the clock and data recovery module 315 and is coupled between the output of the equalizer 310 and the output of the T / H amplifier 350. The capacitor 340 is coupled to the switch 335 and ground 345.

[0017] In the T / H amplifier 350, the switch 360 receives the clock signal Ck 355 that is inverted with respect to the clock signal CK 330 and is coupled between the output of the T / H amplifier 325 and the input of the linear driver 370. The capacitor 365 is coupled to the switch 360 and ground 345. The linear driver 370 receives the output from the track and hold amplifier 350 and outputs the signal Vout 375. Since the S / H circuit 320 is linear, the driver 370 is also linear to preserve the transmitter FIR information.

[0018] Figure 4 Block diagram illustrating an example linear retimer 400 having a three-tap feed-forward equalizer (FFE) 450. The linear retimer 400 is the same as Figure 3The linear retimer 300 shown therein is generally the same, but includes a three-tap FFE 450 instead of the S / H circuit 320. The three-tap FFE 450 includes three S / H circuits 420A to C, three linear amplifiers 425A to C, and a linear adder 440. Each of the three S / H circuits 420A to C receives the clock signal CK 430 from the clock and data recovery module 415. The S / H circuit 420A is coupled to the output of the equalizer 410 and provides its output to the S / H circuit 420B and the amplifier 425A, which multiplies the output from the S / H circuit 420A by the weight α - 1.

[0019] The S / H circuit 420B provides its output to the S / H circuit 420C and the amplifier 425B, which multiplies the output from the S / H circuit 420B by the weight α0. The S / H circuit 420C provides its output to the amplifier 425C, which multiplies the output from the S / H circuit 420C by the weight α + 1. The adder 440 subtracts the outputs of the amplifiers 425A and 425C from the output of the amplifier 425B, substantially canceling the preamble and post-ISI. The output of the adder 440 is provided to the linear driver 470, which outputs the signal Vout 475.

[0020] Figure 5 Describes an example T / H amplifier 500 for use in an S / H circuit (such as Figure 3 the S / H circuit 320 shown therein). The T / H amplifier 500 includes a preamplifier 540 having two switched emitter followers 550A to B. The preamplifier 540 includes a degeneration capacitor Cs 560 coupled in parallel with a degeneration resistor Rs. The preamplifier 540 exhibits poles at approximately:

[0021]

[0022] where C1 represents the input capacitance of the switched emitter follower 550A or 550B, and the poles are at approximately:

[0023]

[0024] where Gm represents the transconductance of the transistors Q1 and Q2. The preamplifier 540 exhibits zeros at

[0025]

[0026] The capacitance of Cs 560 can be selected such that the zeros are at

[0027]

[0028] canceling the poles at

[0029]

[0030] Thereby expanding the bandwidth of the T / H amplifier 500. The feedforward capacitors Cf 570A to B are respectively coupled between the preamplifier 540 and the switched emitter followers 550A to B, and cancel the hold-mode feedthrough by counteracting the effects of the base-emitter capacitances of the transistors QEF1, 2 respectively.

[0031] The term "coupled" is used throughout this specification. The term can encompass connections, communications, or signal paths that enable a functional relationship consistent with the description of the present disclosure. For example, if device A generates a signal to control device B to perform an action, then in a first instance, device A is coupled to device B, or in a second instance, if an intermediate component C does not substantially change the functional relationship between device A and device B, then device A is coupled to device B through the intermediate component C such that device B is controlled by device A via the control signal generated by device A.

[0032] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A retimer, comprising: An equalizer configured to receive an input signal and output an equalized signal; A clock recovery circuit configured to receive the equalized signal and output a clock signal; A sample and hold (S / H) circuit configured to receive the equalized signal and the clock signal and output a retimed signal; And A linear driver configured to receive the retimed signal and output a recovered signal.

2. The retimer according to claim 1, wherein the S / H circuit is further configured to hold the voltage of the equalized signal in the retimed signal.

3. The retimer according to claim 1, wherein the S / H circuit includes a first track and hold (T / H) circuit and a second T / H circuit.

4. The retimer according to claim 3, wherein at least one of the first and second T / H circuits includes: A preamplifier; And A switched emitter follower.

5. The retimer according to claim 4, wherein the preamplifier further includes a degeneration capacitor, and the capacitance of the degeneration capacitor is selected to extend the bandwidth of the preamplifier.

6. The retimer according to claim 4, wherein at least one of the first and second T / H circuits further includes a feed-forward capacitor coupled between the preamplifier and the switched emitter follower, and the capacitance of the feed-forward capacitor is selected to reduce hold mode feedthrough.

7. The retimer according to claim 1, wherein the retimer is configured to be placed between a transmitter and a channel.

8. The retimer according to claim 1, wherein the retimer is configured to be placed after the channel.

9. The retimer according to claim 1, wherein the S / H circuit includes a linear three-tap feed-forward equalizer (FFE), and the linear driver is configured to receive the FFE output signal.

10. The retimer according to claim 9, wherein the S / H circuit is a first S / H circuit, the retimed signal is a first retimed signal, and the linear three-tap FFE further includes: A second S / H circuit configured to receive the first retimed signal and output a second retimed signal; A third S / H circuit configured to receive the second retimed signal and output a third retimed signal; A first amplifier configured to receive the first retimed signal and output a first weighted signal; A second amplifier configured to receive the second retimed signal and output a second weighted signal; A third amplifier configured to receive the third retimed signal and output a third weighted signal; and An adder configured to: Receive the first, second, and third weighted signals; and Combine the first, second, and third weighted signals to obtain the FFE output signal.

11. A retimer, comprising: An equalization circuit coupled to an input; A clock recovery circuit coupled to an output of the equalization circuit; A sample and hold (S / H) circuit, which is coupled to the output of the clock recovery circuit and the output of the equalization circuit; and A linear driver, which is coupled to the output of the S / H circuit and coupled to the output.

12. The retimer according to claim 11, wherein the S / H circuit includes: A first track and hold (T / H) circuit, which is coupled to the output of the clock recovery circuit and the output of the equalization circuit; and A second T / H circuit, which is coupled to the output of the clock recovery circuit and the output of the first T / H circuit.

13. The retimer according to claim 12, wherein at least one of the first and second T / H circuits includes: A preamplifier, which is coupled to the input of at least one of the first and second T / H circuits; A switched emitter follower, which is coupled to the output of the preamplifier and the output of at least one of the first and second T / H circuits; and A feedforward capacitor, which is coupled between the preamplifier and the switched emitter follower.

14. The retimer according to claim 13, wherein the capacitance of the feedforward capacitor is selected to reduce hold mode feedthrough.

15. The retimer according to claim 13, wherein the poles exhibited by the preamplifier are at: where RL represents the resistance of the load resistor in the preamplifier, and C1 represents the capacitance of the switched emitter follower at the output of the preamplifier, wherein the preamplifier further includes a degeneration capacitor, and the zeros exhibited by the preamplifier are at: where Rs represents the resistance of the degeneration resistor in the preamplifier, and Cs represents the capacitance of the degeneration capacitor, and the capacitance Cs is selected such that the zero cancels the pole.

16. The retimer according to claim 11, which further includes a linear feedforward equalizer (FFE), which is coupled to the output of the clock recovery circuit and the output of the equalization circuit, wherein the linear FFE includes the S / H circuit.

17. A retimer, which includes: A first sample and hold (S / H) circuit, which is configured to generate a first retimed signal; A first amplifier, which is configured to generate a first weighted signal based on the first retimed signal; A second S / H circuit, which is configured to generate a second retimed signal based on the first retimed signal; A second amplifier, which is configured to generate a second weighted signal based on the second retimed signal; A third S / H circuit, which is configured to generate a third retimed signal based on the second retimed signal; A third amplifier, which is configured to generate a third weighted signal based on the third retimed signal; An adder, which is configured to combine the first, second, and third weighted signals; An equalization circuit, which is configured to generate an input signal for the first S / H circuit; A clock recovery circuit, which is configured to generate a clock signal for the first, second, and third S / H circuits; and A linear driver, which is configured to generate an output signal based on the output from the adder.

18. The retimer according to claim 17, wherein at least one of the first, second, and third S / H circuits includes a first track and hold (T / H) circuit and a second T / H circuit.

19. The retimer according to claim 18, wherein at least one of the first and second T / H circuits includes: A preamplifier; And A switched emitter follower.

20. The retimer according to claim 19, wherein the preamplifier further includes a degeneration capacitor configured to extend the bandwidth of the preamplifier.

21. The retimer according to claim 19, wherein at least one of the first and second T / H circuits further includes a feedforward capacitor coupled between the preamplifier and the switched emitter follower, wherein the capacitance of the feedforward capacitor is configured to reduce hold mode feedthrough.

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