Frame synchronization system, frame synchronization circuit and frame synchronization method

Abstract

The frame synchronization system (1) according to the present invention comprises: a frame signal generating circuit (20) for generating a frame signal including a plurality of first frame signals, the first frame signal including a first frame synchronization signal and a first payload signal, the first frame synchronization signal including at least one symbol and having an average amplitude set to be lower than the first payload signal; and a frame synchronization circuit (60) for receiving the frame signal via an optical transmission path (70), detecting the first frame synchronization signal from the received signal, dividing the received signal into frames of a symbol length of the first frame signal, adding coordinate values ​​of signals at the same symbol position of the plurality of divided frames on an IQ plane over the plurality of frames, and determining that a symbol identified by comparing the size in the frame based on the addition result is the first frame synchronization signal. Even in the case of a high transmission rate, the probability of erroneous synchronization can be reduced, and the time before frame synchronization can be shortened.

Description

Technical Field

[0001] The invention relates to a frame synchronization system, a frame synchronization circuit and a frame synchronization method in data communication. Background Art

[0002] In coherent optical communications, the receiving side attempts to increase capacity by compensating for transmission characteristics through precise timing synchronization, and transmission of 100Gbps or higher is currently possible. In timing synchronization, a frame synchronization pattern pre-inserted for each frame of the received signal is used, and whether the synchronization pattern can be accurately and quickly detected affects the performance of increasing capacity.

[0003] Since in optical communication, the symbol error rate becomes high due to dispersion, polarization dispersion, signal-to-noise ratio degradation, etc., thereby deteriorating the transmission characteristics, it is important to accurately detect the synchronization pattern even in this state. Specifically, in a system with a further increase in capacity (for example, 1 Tbps or more), it is important to reliably detect the synchronization pattern and establish frame synchronization faster and more accurately even in a state where the error rate is high.

[0004] In optical communication, generally, if a signal is received, frame synchronization is performed by correlating the received signal with a fixed pattern prepared on the receiving side on the time axis. When the signal patterns coincide with each other, the correlation value is maximum. Note that if two polarizations are used as in optical communication, correlation is performed independently for each polarization.

[0005] In this synchronization method, in a state where the error rate increases, the probability of erroneous synchronization detection is high. If it is determined that the detected synchronization is erroneous, the process of establishing synchronization is performed again. Therefore, the higher the error rate, the greater the number of times the process of establishing synchronization is performed again. In this state, it takes time to finally establish correct synchronization. Therefore, even in a state where the error rate is high, a synchronization method that can quickly and reliably establish synchronization is required.

[0006] Patent document 1 discloses a method for generating a frame pattern by not sending an optical signal of at least 1 bit in the time domain, generating a histogram by integrating the data at the same bit position in the frame divided on the receiving side, and detecting the position of the frame pattern from the histogram. The method is associated with an optical communication system before coherent optical communication is performed, and is used for performing optical pulse transmission for communication by turning on / off an optical signal. After the on / off of the optical signal is determined as 0 / 1 data, an integration operation is performed. In this method, in a state where the error rate is low, the reliability of the determination result of the data is high, so synchronization can be established relatively reliably. However, in a state where the error rate increases, the probability of erroneously detecting synchronization is high.

[0007] Patent document 2 discloses an optical communication system that performs frame synchronization using a synchronization signal pattern set with an average light intensity lower than the average light intensity of the payload area. In this frame synchronization method, the synchronization signal pattern is detected from the received bit string to determine the start of the frame. In this case, since the average light intensity of the synchronization signal pattern is set to be lower than the average light intensity of the payload area, the nonlinear distortion of the synchronization signal pattern can be reduced, thereby correctly determining the start of the frame. However, the synchronization signal pattern needs to be detectable in a state where the signal-to-noise ratio is not significantly degraded.

[0008] The frame synchronization device according to Patent Document 3 detects the synchronization pattern by detecting a pattern in which the average value of the distance between the symbol of the synchronization pattern and the received signal on the IQ plane is minimized. In coherent optical communication, the synchronization state can be correctly determined even if the received symbol error rate is high.

[0009] Related technical literature

[0010] Patent Literature

[0011] Patent Document 1: Japanese Patent Application Publication No. 2009-218744

[0012] Patent Document 2: Japanese Patent Application Publication No. 2016-019030

[0013] Patent Document 3: Japanese Patent Application Publication No. 2019-213218 Summary of the invention

[0014] Technical Problems to be Solved by the Invention

[0015] However, the conventional frame synchronization method described above has the following problems. According to Patent Document 1, in a state where the error rate is degraded, the probability of erroneous synchronization is high, and the frame synchronization method cannot be used as a synchronization method at an increased transmission rate of 1 Tbps or higher. In the frame synchronization method described in Patent Document 2, it is difficult to detect the synchronization signal pattern in a state where the S / N ratio is greatly degraded, so the method cannot be used as a synchronization method at an increased transmission rate of 1 Tbps or higher. In addition, in the frame synchronization method described in Patent Document 3, in a state where the error rate is high, erroneous synchronization increases, and the method is difficult to use at an increased transmission rate of 1 Tbps or higher. The above-mentioned 1 Tbps is an example of an indicator indicating the degree of high transmission rate. For example, conditions of 500 Gbps or higher are also included in the high transmission rate.

[0016] As described above, in the conventional frame synchronization method, if the transmission rate is high, the probability of false synchronization of falsely detecting synchronization increases under the condition of high error rate. If the probability of false synchronization is high, the synchronization process is repeated until synchronization is correctly detected, so it takes a lot of time to establish synchronization.

[0017] The present invention has been made to solve the above-mentioned problems, and provides a frame synchronization system which shortens the time until frame synchronization is established by reducing the probability of erroneous synchronization even if the transmission rate is high.

[0018] Solutions to the problem

[0019] In order to solve the above-mentioned problem, a frame synchronization system according to the present invention includes: a frame signal generating circuit, which is configured to generate a frame signal including a plurality of first frame signals, each first frame signal including a first frame synchronization signal and a first payload signal, wherein the first frame synchronization signal is formed by at least one symbol and is set to have an average amplitude lower than the average amplitude of the first payload signal; and a frame synchronization circuit, which is configured to receive the frame signal generated by the frame signal generating circuit via an optical transmission path, and detect the first frame synchronization signal from the received signal, wherein the received signal is divided into frames having a symbol length of the first frame signal, and the absolute values ​​of the coordinate values ​​of the signals at the same symbol position of the plurality of frames on the IQ plane are added on the divided plurality of frames, and the symbol specified by performing amplitude comparison in the frame based on the addition result is determined as the first frame synchronization signal.

[0020] In order to solve the above-mentioned problems, a frame synchronization method according to the present invention is a frame synchronization method in a frame synchronization system including a frame signal generating circuit and a frame synchronization circuit, the frame synchronization method including: a frame signal generating step, which generates a frame signal including a plurality of first frame signals, each first frame signal including a first frame synchronization signal and a first payload signal, wherein the first frame synchronization signal is formed by at least one symbol and is set to have an average amplitude lower than the average amplitude of the first payload signal; and a frame synchronization step, which receives the frame signal generated by the frame signal generating circuit via an optical transmission path, and detects the first frame synchronization signal from the received signal, wherein the received signal is divided into frames having a symbol length of the first frame signal, and the absolute values ​​of the coordinate values ​​of the signals at the same symbol positions of the plurality of frames on the IQ plane are added on the divided plurality of frames, and the symbol specified by performing amplitude comparison in the frame based on the addition result is determined as the first frame synchronization signal.

[0021] Effects of the Invention

[0022] According to the present invention, it is possible to provide a frame synchronization system which can shorten the time until frame synchronization is established by reducing the probability of erroneous synchronization even if the transmission rate is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a view showing an example of a configuration of a frame synchronization system according to an embodiment of the present invention;

[0024] Figure 2 is a view for explaining the operation of the frame signal generating circuit according to the embodiment of the present invention;

[0025] Figure 3 is a diagram showing signal points of a short frame synchronization signal and a payload signal according to an embodiment of the present invention;

[0026] Figure 4 is a view showing an example of the arrangement of a frame synchronization circuit according to an embodiment of the present invention;

[0027] Figure 5 is a flow chart showing a frame synchronization method according to an embodiment of the present invention;

[0028] Figure 6 is a view for explaining a method for detecting a short frame synchronization signal according to an embodiment of the present invention;

[0029] Figure 7 is a graph showing the output of a cumulative adding circuit according to an embodiment of the present invention;

[0030] Figure 8 is a graph showing the result of measuring the probability of false synchronization in short frame synchronization detection according to an embodiment of the present invention; and

[0031] Fig. 9 is a view for explaining a method of detecting a long frame synchronization signal according to the present invention. DETAILED DESCRIPTION

[0032] The embodiments of the present invention will be described below with reference to the accompanying drawings. The present invention can be implemented in many different ways, but is not limited to the embodiments of the present invention to be described below.

[0033] <Overview of the Invention>

[0034] According to the present invention, frame synchronization is performed in two stages of short frame synchronization and long frame synchronization. The short frame signal is formed by a short frame signal (first frame signal) including a short frame synchronization signal (first frame synchronization signal) and a payload signal (first payload signal). On the other hand, the long frame signal (second frame signal) is formed by a plurality of short frame signals (first frame signal), and a long frame synchronization signal (second frame synchronization signal) indicating a long frame position is set in a predetermined symbol of the short frame. As long as the position of the long frame can be specified, the setting position of the long frame synchronization signal can be arbitrary. The long frame synchronization signal is usually set in the first short frame signal, but can also be set near the center or in the last short frame. Alternatively, the long frame synchronization signal can be set on a plurality of short frame synchronization signals, as will be described later.

[0035] According to the present invention, a short frame synchronization signal is formed of at least one symbol and is set with an average amplitude lower than the average amplitude of a payload signal to distinguish it from the payload signal. With respect to a signal point obtained by mapping the symbol of the short frame synchronization signal on an IQ plane, random data is temporarily set in the payload signal, cumulative addition of amplitude values ​​is performed over a plurality of frames, and the cumulative addition of the amplitude values ​​is compared with a value obtained by cumulative addition of the amplitude values ​​of the short frame synchronization signal, so that a signal point having a cumulative addition value as an average amplitude lower than the average amplitude of the payload signal can be set. Cumulative addition of symbol amplitudes is equivalent to averaging, so the obtained value can be regarded as an average amplitude. Therefore, a short frame synchronization signal having an average amplitude lower than the average amplitude of the payload signal can be set.

[0036] On the receiving side, short frame synchronization is established, and then long frame synchronization is established. In the short frame synchronization, the received signal is divided into a plurality of frames having a symbol length of a short frame, and the absolute values ​​of the symbol amplitudes of the divided frames are cumulatively added for each symbol over the plurality of frames. Since the short frame synchronization signal is set with an average amplitude lower than that of the payload signal, the symbol specified by amplitude comparison in the short frame width based on the cumulative addition result can be determined as the short frame synchronization signal.

[0037] For example, if a short frame is formed of one symbol, the symbol with the smallest cumulative addition result is the short frame synchronization signal. Since the cumulative addition of symbol amplitudes over a plurality of frames is equivalent to an average, the results of the cumulative addition of symbol amplitudes are compared with each other, thereby making it possible to detect a short frame synchronization signal having an average amplitude lower than that of a payload signal.

[0038] The amplitudes to be cumulatively added are the absolute values ​​of the I coordinate value and the Q coordinate value on the IQ plane. These values ​​are data before the data determined as "0" or "1", and are values ​​in a state where information indicating reliability (likelihood information) is added. Next, in long frame synchronization, a check (cross-correlation synchronization) with the long frame synchronization pattern is performed for each short frame, thereby detecting the long frame synchronization signal to establish long frame synchronization.

[0039] In short frame synchronization, an I coordinate and a Q coordinate whose average amplitude is lower than that of a payload signal on the IQ plane are used. Since the average amplitude can be observed by a simple method of cumulatively adding the I coordinate value and the Q coordinate value, the synchronization pattern can be detected reliably and stably. In addition, by using the coordinate value on the IQ plane in a state where reliability is added before the data determined as "0" or "1", the short frame synchronization signal can be detected with high reliability even in a state where the error rate is degraded.

[0040] In addition, in long frame synchronization, the synchronization signal is detected in units of a plurality of short frames forming a long frame. Therefore, compared with the case where correlation is performed on all symbols while shifting one symbol as in the conventional method, the time until synchronization is established can be greatly shortened.

[0041] <Frame Synchronization System>

[0042] Figure 1 1 is a view showing an example of the configuration of a frame synchronization system according to an embodiment of the present invention. The transmission side of the frame synchronization system 1 includes a transmission signal processing circuit 10, a frame signal generating circuit 20, and an optical transmission circuit 30. The receiving side of the frame synchronization system 1 includes an optical receiving circuit 40, a receiving signal processing circuit 50, and a frame synchronization circuit 60. The optical receiving circuit 40 on the receiving side receives the frame signal generated on the transmission side via an optical transmission path such as an optical fiber 70.

[0043] The transmission signal processing circuit 10 divides the transmission data into horizontal polarization signals (XI, XQ) and vertical polarization signals (YI, YQ), and performs error correction coding or other processing for each signal. The frame signal generation circuit 20 generates a frame signal based on the transmission data of each of the horizontal polarization signals (XI, XQ) and the vertical polarization signals (YI, YQ). Each frame signal is added with a frame synchronization signal for frame synchronization. The frame signal is converted into an optical signal in the optical transmission circuit 30, and the horizontal polarization signal and the vertical polarization signal are combined and provided to the optical fiber 70. As the transmission rate of the transmission data in the present embodiment, for example, it is assumed that several hundred Gbps to 1Tbps or higher.

[0044] The signal received via the optical fiber 70 is supplied to the optical receiving circuit 40. The optical receiving circuit 40 separates the optical signal into a horizontal polarization signal (XI, XQ) and a vertical polarization signal (YI, YQ), and the separated optical signal is converted into an electrical signal and supplied to the reception signal processing circuit 50.

[0045] Each of the horizontal polarization signal (XI, XQ) and the vertical polarization signal (YI, YQ) is represented by an I component and a Q component on the IQ plane. XI and XQ represent the I component and the Q component of the horizontal polarization signal, respectively, and YI and YQ represent the I component and the Q component of the vertical polarization signal, respectively. That is, when the received signal is represented by a complex number, the I component and the Q component correspond to the I coordinate and the Q coordinate, respectively.

[0046] The reception signal processing circuit 50 performs compensation processing for distortion occurring in the reception signal during transmission, and performs decoding processing. The compensation processing may include, for example, dispersion compensation, polarization dispersion compensation, and frequency offset compensation. The decoding processing may include, for example, error correction processing.

[0047] The signal components XI, XQ, YI, and YQ are supplied to the frame synchronization circuit 60 and are subjected to a frame synchronization establishment process. The result of the frame synchronization is used for various compensation processes and decoding processes in the reception signal processing circuit 50.

[0048] Note that the present embodiment has described the case where the optical signal is divided into a horizontal polarization signal and a vertical polarization signal and then transmitted. However, the present invention is not limited thereto and can be applied to the case where only one of the horizontal polarization signal and the vertical polarization signal is transmitted.

[0049] <Operation of Frame Generation Circuit>

[0050] Figure 2 FIG. 2 is a diagram for explaining the operation of the frame signal generating circuit 20 according to the embodiment of the present invention. Figure 2 In the illustrated example, description will be given of a case where a common frame synchronization signal is set for the horizontal polarization signal X and the vertical polarization signal Y. However, the frame synchronization signal may also be set in a different form.

[0051] The "symbol" described in this embodiment indicates the changing timing of the signal point (constellation) on the IQ plane in the modulation scheme in coherent optical communication. For example, in 64QAM, the signal point switches every 6 bits, and the timing of the switch is one symbol. That is, the period of one symbol is 6 bits.

[0052] exist Figure 2In the example shown, a short-period short frame signal and a long-period long frame signal formed by multiple short frame signals are defined. The short frame signal is formed by a short frame synchronization signal (hereinafter referred to as an SFS signal) of one symbol and a payload signal of 128 symbols. The long frame signal is formed by multiple short frame signals (for example, hundreds of short frame signals). For example, Figure 2 As shown, a long frame synchronization signal (hereinafter referred to as an LFS signal) of a long frame signal may be formed by some data of a payload signal of a first short frame signal.

[0053] The SFS signal is set to have an average amplitude lower than the average amplitude of the payload signal. In the present embodiment, among the signal points on the IQ plane, the signal points with low amplitude are used as SFS signals. For example, for a 64QAM signal, 16 signal points around the origin are used as SFS signals. For a 16QAM signal, four signal points around the origin are used as SFS signals. In this case, the same signal point can be used as the SFS signal for any short frame. As long as the average amplitude and the average amplitude of the payload signal can be distinguished, different signal points can be used for each short frame. Different signal points with the same amplitude can also be used. By shortening the frame length and facilitating the distinction between the synchronization signal and the payload signal, short frame synchronization can be reliably performed even in high error rate situations.

[0054] The SFS signal is not limited to one symbol and may be formed of a plurality of symbols. From the perspective of data transmission efficiency, one symbol is more preferred, but when the SFS signal is formed of a plurality of symbols, the reliability of synchronization can be improved. By appropriately selecting the number of symbols of the SFS signal, the SFS signal can be formed while taking both synchronization reliability and transmission efficiency into consideration. In synchronization detection on the receiving side, when the SFS signal is formed of a plurality of symbols, a plurality of continuous symbols having relatively low values ​​as a result of amplitude comparison of the result of accumulating and adding symbol amplitudes over a plurality of frames are detected and specified, and these symbols are determined to be SFS signals.

[0055] The LFS signal may be formed of predetermined symbols of one or more short frame signals. Similar to the SFS signal, if the number of symbols of the LFS signal is large, the reliability of synchronization may be improved. However, using a complete short frame signal as the LFS signal is effective in synchronization processing.

[0056] The LFS signal may be formed of a plurality of SFS signals instead of a payload signal of a short frame. In the SFS signal, not a single signal point on the IQ plane but a plurality of signal points may be converted. Therefore, by converting the signal point using a plurality of SFS signals, a synchronization pattern of the LFS signal may be formed. When the LFS signal is formed of a plurality of SFS signals, it is not necessary to set the payload signal of the short frame as the LFS signal, and thus data transmission efficiency may be further improved.

[0057] The SFS signal can be shared with a conventional phase compensation pilot signal (PS). This can also be used for lane identification and transmission path variation compensation. As an LFS signal, a conventional long frame synchronization signal (TS) can be set. Conventionally, a phase compensation pilot signal (PS) or a long frame synchronization signal (TS) with different modulation schemes is inserted into the payload. However, since reliable short frame synchronization can be established by the SFS signal, there is no need to use a PS or TS with different modulation schemes.

[0058] <Signal point of short frame synchronization signal>

[0059] Figure 3 1 is a diagram showing signal points of a short frame synchronization signal and a payload signal according to an embodiment of the present invention. Figure 3 Let's take 64QAM as an example. In 64QAM, 64 signal points are kept on the IQ plane. Figure 3 In the example shown, only 16 signal points located at the center are used as SFS signals. On the other hand, since all 64 signal points are used as payload signals, the average amplitude of the SFS signal can be made lower than the average amplitude of the payload signal.

[0060] As mentioned above, the LFS signal can be formed from multiple SFS signals. Figure 3 In the example shown, the amplitude of the SFS signal can be changed in four levels in the I-axis direction and the Q-axis direction. With this, the coordinate values ​​on the IQ plane are converted to form a synchronization pattern. By using this synchronization pattern as an LFS signal, a predetermined SFS signal can be used as an LFS signal among a plurality of SFS signals forming a short frame.

[0061] Note that signal points with low amplitude are not limited to Figure 3 16 points are shown. Any signal point can be used if an average amplitude lower than the amplitude of the payload can be detected. The signal points of the SFS signal and the LFS signal do not need to be the same in the X polarization and the Y polarization. In addition, the signal points of the SFS signal do not need to be symmetrical on the IQ plane. It is sufficient to detect symbols with low average amplitude.

[0062] <Frame Synchronization Circuit>

[0063] Figure 4 1 is a diagram showing an example of the arrangement of a frame synchronization circuit according to an embodiment of the present invention. Figure 4 In the example of the arrangement shown, the optical receiving circuit 40 provides the received signal processing circuit 50 with received signals XI and XQ as the I component and Q component of the horizontal polarization signal X, and received signals YI and YQ as the I component and Q component of the vertical polarization signal Y, respectively.

[0064] The received signals XI, XQ, YI and YQ are respectively provided to the frame synchronization circuits XI, XQ, YI and YQ, and these circuits respectively perform short frame synchronization processing and long frame synchronization processing. Each of the frame synchronization circuits XI, XQ, YI and YQ includes a cumulative addition circuit 61, a short frame synchronization signal detection circuit 62 and a long frame synchronization signal detection circuit 63.

[0065] Cumulative addition circuit 61 uses the length of the short frame (in Figure 1 In the example shown, each of the provided received signals XI, XQ, YI, and YQ is divided every 129 symbols, and the absolute values ​​of the coordinate values ​​on the IQ plane in the symbols at the same symbol position of the plurality of divided frames are cumulatively added over a plurality of frames. At this time, the cumulative addition circuit 61 adds the absolute values ​​of the values ​​(I coordinate, Q coordinate) on the IQ plane, which are the values ​​before being determined as "0" or "1".

[0066] The short frame synchronization signal detection circuit 62 detects the SFS signal based on the cumulative addition result of the cumulative addition circuit 61. The absolute values ​​of the amplitudes of the respective symbols of the short frame width are cumulatively added over a plurality of frames, and a symbol specified by amplitude comparison in the frame based on the cumulative addition result is determined as the SFS signal. For example, if the SFS signal is formed of one symbol, the symbol having the smallest cumulative addition result is detected as the SFS signal.

[0067] The long frame synchronization signal detection circuit 63 detects the LFS signal from each of the reception signals XI, XQ, YI, and YQ using the SFS signal detection result of the short frame synchronization signal detection circuit 62. In the long frame synchronization, the reception signal and the reference long frame synchronization signal are correlated for each short frame divided by the SFS signal, thereby detecting the LFS signal. As the reception signal after the short frame synchronization correlated with the reference long frame synchronization signal, the coordinate value on the IQ plane can be used as it is, but data after being determined as "0" or "1" (described later) can also be used.

[0068] The received signals XI, XQ, YI, and YQ are also provided to the long frame synchronization signal detection circuit 63 as values ​​on the IQ plane. Data obtained after the signal is determined to be "0" or "1" may also be provided. By using the data obtained after the signal is determined to be "0" or "1", correlation can be performed by comparing with the reference long frame synchronization signal. Since the LFS signal is detected after the short frame synchronization is established, the LFS signal can be detected more efficiently by comparing the data obtained after being determined to be "0" or "1" with the reference signal, compared with the process using the coordinate values ​​on the IQ plane. For example, if the LFS signal is long, by comparing the data "0" or "1", the calculation process when performing the comparison can become more efficient.

[0069] Note that the above-mentioned short frame synchronization processing and long frame synchronization processing can be performed independently for each of the received signals XI, XQ, YI and YQ. However, by processing the signals XI and XQ together as complex numbers, and processing the signals YI and YQ together as complex numbers, synchronization processing can be performed for two signals of the horizontal polarization signal X and the vertical polarization signal y.

[0070] <Frame synchronization method>

[0071] Will refer to Figures 5 to 9 A frame synchronization method according to an embodiment of the present invention is described. The frame synchronization method according to an embodiment of the present invention includes: a frame signal generation step, which generates a frame signal including a plurality of short frame signals, each short frame signal including an SFS signal and a payload signal; and a frame synchronization step, which detects the SFS signal from the received frame signal, and establishes short frame synchronization by detecting the SFS signal. In the frame signal generation step, an LFS signal is set in a predetermined symbol of the short frame signal. In the frame synchronization step, long frame synchronization is established by detecting the LFS signal.

[0072] Figure 5 is a flow chart showing a frame synchronization method according to an embodiment of the present invention. Figure 5 The above frame synchronization steps of the frame synchronization method are explained.

[0073] In the cumulative addition process (step S1), the cumulative addition circuit 61 performs the summing of the short frame length (in Figure 1 In the example shown, each of the provided received signals XI, XQ, YI and YQ is divided every 129 symbols, and the absolute values ​​of the values ​​of the signals at the same symbol positions of the multiple divided frames on the IQ plane are accumulated and added over multiple frame signals.

[0074] In the short frame synchronization process (step S2), the short frame synchronization signal detection circuit 62 detects the SFS signal based on the result of the cumulative addition process in step S1. The absolute values ​​of the amplitudes of the respective symbols of the short frame width are cumulatively added over a plurality of frames, and the symbol specified by comparing the amplitudes in the frame based on the addition result is determined as the SFS signal. For example, if the SFS signal is formed of one symbol, the symbol having the smallest cumulative addition result is detected as the SFS signal.

[0075] In the long frame synchronization process (step S3), the long frame synchronization signal detection circuit 63 detects an LFS signal from each of the reception signals XI, XQ, YI and YQ using the result of the short frame synchronization process detected by the SFS signal in the short frame synchronization process in step S2.

[0076] As described above, in the frame synchronization method of the present embodiment, a short frame synchronization signal is detected to establish short frame synchronization, and a long frame synchronization signal is detected to perform long frame synchronization processing on a reception signal for which short frame synchronization has been established.

[0077] <Short Frame Sync>

[0078] Figure 6 1 is a view for explaining a method for detecting a short frame synchronization signal according to an embodiment of the present invention. Figure 5 As described in step S1, in order to detect the short frame synchronization signal, each of the received signals XI, XQ, YI and YQ provided to the cumulative addition circuit 61 is divided by the length of the short frame, and the absolute values ​​of the values ​​of the signals at the same symbol positions of multiple divided frames are added over multiple frames.

[0079] exist Figure 6 In the example shown, a short frame of this length is formed by 129 symbols, so Figure 6 As shown in the uppermost layer of , each of the received signals XI, XQ, YI, and YQ is divided for every 129 symbols. The absolute value of the amplitude of the symbol is cumulatively added for each of the 129 symbols from the first symbol (symbol A) to the 129th symbol over multiple frames, and then the addition results of the respective symbols are expressed as amplitude addition value 1, amplitude addition value 2, ..., amplitude addition value 129. Since the SFS signal is formed by one symbol, the symbol having the minimum value among the amplitude addition value 1, the amplitude addition value 2, ..., the amplitude addition value 129 is determined as the SFS signal.

[0080] The number of frames to be added may be, for example, but not limited to, approximately 30. The number of frames to be added may be appropriately determined according to the state of the transmission path or the like.

[0081] In the short frame synchronization detection of the present embodiment, the value to be added is the absolute value of the coordinate value of each of the received signals XI, XQ, YI and YQ on the IQ plane. These values ​​are values ​​indicating the coordinates on the IQ plane and are values ​​before being determined as "0" or "1". The IQ plane is also called a complex plane.

[0082] Generally, when the coordinate value on the IQ plane is determined to be "0" or "1", a complex error correction circuit is required. However, in the short frame synchronization detection according to the present embodiment, since the value indicating the coordinate on the IQ plane is used, such a complex error correction circuit is not required. In addition, in the value determined to be "0" or "1", the information indicating the reliability of the value (also called likelihood information) is lost, for example, "0" is close to "1" or "1" is close to "0". By using the coordinate value on the IQ plane that retains the likelihood information, a highly reliable synchronization signal detection result can be obtained even in a state where the error rate is high.

[0083] Figure 7 1 is a graph showing the output of the cumulative addition circuit according to an embodiment of the present invention. The horizontal axis represents the order of symbols when dividing. The vertical axis represents the cumulative addition value, and the reference Figure 6 Describes the amplitude addition value from 1 to 129. Figure 7 , the number of cumulatively added frames is 32. Note that the cumulatively added value on the ordinate is a normalized value.

[0084] exist Figure 7 In , since the SFS signal is formed by one symbol, the symbol having the minimum value among the amplitude addition values ​​1 to 129 is detected. Figure 7 As shown, since the amplitude added value of the 126th symbol is the minimum value, the 126th symbol in the divided frame can be estimated as the SFS signal.

[0085] exist Figure 6 and Figure 7 The case where the SFS signal is formed by one symbol has been described in the example shown. If the SFS signal is formed by a plurality of symbols, a plurality of continuous symbols having relatively small values ​​as a result of amplitude comparison of the result of accumulating and adding symbol amplitudes over a plurality of frames are detected and specified, and these symbols are determined as SFS signals. For example, if there are a plurality of symbols having the minimum cumulative addition value, the symbol can be determined as an SFS signal. Alternatively, a plurality of symbols included in a predetermined value range around the minimum value can be determined as SFS signals. The determination condition of the SFS signal can be appropriately determined according to the state of the transmission path, etc.

[0086] In addition, the above-mentioned cumulative addition process and minimum value detection process for 32 frames are regarded as one SFS signal estimation process, and the process is repeated multiple times. Therefore, if the same result is obtained N times (for example, twice) in succession, it is formally determined that synchronization has been established, and the symbol is set as the finalized symbol of the SFS signal and is determined as the boundary of the short frame.

[0087] On the other hand, if the above-mentioned SFS signal estimation process is repeated thereafter and different results are obtained M times (for example, five times) in succession, it is determined that synchronization is lost. For example, if different symbols such as the 123rd symbol, the 96th symbol, the 56th symbol, the 3rd symbol, and the 45th symbol are estimated in succession, it is determined that synchronization is lost. For example, after the synchronization loss is detected, the synchronization establishment process is performed again in response to an instruction from the reception signal processing circuit.

[0088] Note that in the process of detecting the minimum value of the cumulative addition value, in 64QAM, the cumulative addition value cannot take the maximum value or greater of the coordinates of the 64 signal points. If the cumulative addition value takes a value equal to or greater than the maximum value, even in a state where the error rate is high, an inventive design that improves detection reliability as much as possible can be performed, for example, by setting a maximum value or setting a threshold value as a detection condition.

[0089] Figure 8 The result of measuring the probability of false synchronization in short frame synchronization detection according to an embodiment of the present invention is shown. The horizontal axis represents the number of frames to be cumulatively added, and the vertical axis represents the probability of false synchronization. Under a given error rate, the probability of false synchronization is the ratio of the number of times the result of establishing synchronization is finally determined (for example, the same result is obtained N times in a row) to the number of times the short frame synchronization process is performed. For example, if the detection process is performed 100 times, then the number of times synchronization cannot be detected is 10, the number of times synchronization can be correctly detected is 10, and the number of times synchronization is detected incorrectly is 80, then the probability of false synchronization is 0.8. Generally, under the same detection conditions, the higher the error rate, the greater the probability of false synchronization.

[0090] The measurement was performed for three error rates of BER = 4.5e-1, 4.5e-2, and 4.5e-3. Error rate = 4.5e-1 indicates a degraded state in which an average of 45 symbols are erroneous among 100 symbols.

[0091] like Figure 8 As shown, when short frame synchronization detection is used, if the number of frames to be cumulatively added is 32 or more, the probability of erroneous synchronization can be suppressed to 0.01 or less even in a degraded state of error rate = 4.5e-1. In the short frame synchronization according to the present embodiment, synchronization can be stably detected even in a state of degraded error rate. This can reduce the number of times the synchronization process is retried, thereby reducing the time until synchronization is established. For example, the synchronization time can be reduced to about 1 / 100 of the conventional synchronization time.

[0092] <Long Frame Synchronization>

[0093] Will refer to Fig. 9 A method for detecting the LFS signal is described. In this embodiment, long frame synchronization is established based on the short frame synchronization established by detecting the SFS signal. Fig. 9 After establishing short frame synchronization, the LFS signal inserted into the payload of the short frame is detected to establish long frame synchronization. Fig. 9 In the example shown, the LFS signal is set in the payload of the first short frame of a long frame formed by a plurality of short frames.

[0094] In the long frame synchronization, as a synchronization method, for each short frame divided by the SFS signal, the payload signal provided with the LFS signal is correlated with the reference long frame synchronization signal, thereby detecting the LFS signal. As a received signal after the short frame synchronization correlated with the reference long frame synchronization signal, a coordinate value on the IQ plane can be used and compared with the reference long frame synchronization signal.

[0095] The coordinate value on the IQ plane can be used to determine the received signal as data of "0" or "1", and the data of "0" or "1" can be compared with the reference long frame synchronization signal. In the long frame synchronization process, after the short frame synchronization is established, the comparison with the reference signal is performed for each short frame. Therefore, by the method of comparing the data of "0" or "1" with the reference signal, the correlation detection can be performed more efficiently. For example, if the LFS signal is long, by comparing the data of "0" or "1" with the reference signal, the calculation process when performing the comparison can be made more efficient.

[0096] Unlike conventional frame synchronization, in the long frame synchronization according to the present embodiment, since it is not necessary to perform correlation for all symbols while shifting one symbol, and check is performed for each short frame, the time until the frame synchronization is established can be greatly reduced. For example, if the short frame is formed of 129 symbols, the number of executions of the synchronization process for the long frame can actually be reduced to 1 / 129 of the conventional number.

[0097] Note that reference has been Fig. 9 The case where the LFS signal inserted into the payload of the short frame is detected to establish long frame synchronization is described. However, as described above, the LFS signal can be formed by a plurality of SFS signals. A plurality of SFS signals forming a short frame can be used as an LFS signal by forming a synchronization pattern by converting the coordinate values ​​on the IQ plane under the condition satisfied by the SFS signal and using the synchronization pattern as the LFS signal.

[0098] As described above, the frame synchronization system of this embodiment is configured to reliably perform synchronization detection processing on the IQ plane using a simple synchronization signal in short frame synchronization. Therefore, even in a state where the error rate is high, the detection of erroneous synchronization can be reduced, and short frame synchronization can be performed reliably and stably.

[0099] Furthermore, since frame synchronization is performed in two stages of short frame synchronization and long frame synchronization, i.e., long frame synchronization is performed for each short frame after short frame synchronization is established, long frame synchronization can be established in a very short time compared to the conventional method of directly performing long frame synchronization.

[0100] Since the short frame synchronization signal of the present embodiment is set to have an average amplitude lower than that of the payload signal, low-amplitude symbols are periodically inserted to reduce the average amplitude value, thereby achieving a power saving effect. A similar effect can be achieved by a coding called probability shaping, which can make the probability of occurrence of the amplitude value of the signal point on the IQ plane close to a normal distribution to improve noise tolerance.

[0101] Industrial Applicability

[0102] The present invention can be used as a frame synchronization device for determining a frame synchronization state in an optical communication device for coherent optical communication.

[0103] Description of Reference Numerals

[0104] 1...frame synchronization system, 10...transmission signal processing circuit, 20...frame signal generating circuit, 30...optical transmission circuit, 40...optical receiving circuit, 50...receiving signal processing circuit, 60...frame synchronization circuit, 70...optical fiber.

Claims

1. A frame synchronization system, comprising: a frame signal generating circuit configured to generate a frame signal including a plurality of first frame signals, each of the first frame signals including a first frame synchronization signal and a first payload signal, wherein the first frame synchronization signal includes at least one symbol, is set to have an average amplitude lower than an average amplitude of the first payload signal, and uses a signal point on an IQ plane; and A frame synchronization circuit is configured to receive the frame signal generated by the frame signal generation circuit as a coordinate value on the IQ plane via an optical transmission path, and detect the first frame synchronization signal from the received signal, the frame synchronization circuit divides the received signal into frames each having a symbol length of the first frame signal, adds the absolute values ​​of the I coordinate value and the Q coordinate value of the signal at the same symbol position in each of the multiple frames on the IQ plane over the divided multiple frames, and determines a symbol specified by amplitude comparison based on the addition result in the frame as the first frame synchronization signal.

2. The frame synchronization system according to claim 1, wherein: The first frame synchronization signal is formed of one symbol, and a symbol having a minimum addition result specified by amplitude comparison in a frame is determined as the first frame synchronization signal.

3. The frame synchronization system according to claim 1 or 2, wherein: The frame signal generating circuit is configured to: set a second frame synchronization signal indicating a position of a second frame signal having a cycle longer than that of the first frame signal to a predetermined symbol of the first frame signal in the second frame signal, and The frame synchronization circuit performs determination of the first frame synchronization signal using the coordinate value addition during at least one cycle of the second frame signal, and detects the second frame synchronization signal by correlating with a reference frame synchronization frame at the predetermined symbol for each of the first frame signals obtained by the determination.

4. The frame synchronization system according to claim 3, wherein: The second frame synchronization signal is set to at least some of the symbols of the first payload signal.

5. The frame synchronization system according to claim 3, wherein: The second frame synchronization signal is set to a plurality of symbols of the first frame synchronization signal.

6. The frame synchronization system according to claim 5, wherein: The synchronization pattern of the second frame synchronization signal is formed by converting the coordinate values ​​on the IQ plane from the first frame synchronization signal.

7. A frame synchronization method in a frame synchronization system, the frame synchronization system comprising a frame signal generating circuit and a frame synchronization circuit, the frame synchronization method comprising: a frame signal generating step of generating a frame signal including a plurality of first frame signals, each of the first frame signals including a first frame synchronization signal and a first payload signal, wherein the first frame synchronization signal includes at least one symbol, is set to have an average amplitude lower than an average amplitude of the first payload signal, and uses a signal point on an IQ plane; and A frame synchronization step, receiving the frame signal generated by the frame signal generating circuit as a coordinate value on the IQ plane via an optical transmission path, and detecting the first frame synchronization signal from the received signal, the frame synchronization step comprising the following steps: dividing the received signal into frames each having a symbol length of the first frame signal, adding the absolute values ​​of the I coordinate value and the Q coordinate value of the signal at the same symbol position of each of the multiple frames on the IQ plane over the divided multiple frames, and determining a symbol specified by amplitude comparison based on the addition result in the frame as the first frame synchronization signal.

Images