Film for reflective mask and method for manufacturing the same

Abstract

A film for a reflective light mask and a method for manufacturing the same. The film for a reflective light mask comprises a frame, a core layer having a front surface and a rear surface and arranged above the frame, a first covering layer arranged on the front surface of the core layer, an anti-reflection layer arranged on the first covering layer, a barrier layer arranged on the anti-reflection layer, and a thermal emission layer arranged on the barrier layer.

Description

Technical Field

[0001] The present disclosure relates to a film for a reflective mask and a method for manufacturing the same. Background Art

[0002] A pellicle is a transparent film stretched over a frame structure that is glued to one side of the reticle to protect it from damage, dust and / or moisture. In extreme ultra violet (EUV) lithography, a pellicle with high transparency, high mechanical strength and low thermal expansion in the EUV wavelength region is often required. Summary of the invention

[0003] According to some embodiments of the present disclosure, a film for a reflective mask includes a frame; a core layer having a front surface and a rear surface and disposed above the frame; a first covering layer disposed on the front surface of the core layer; an anti-reflection layer disposed on the first covering layer; a barrier layer disposed on the anti-reflection layer; and a thermal emission layer disposed on the barrier layer.

[0004] According to some embodiments of the present disclosure, a film for a reflective mask includes a core layer having a front surface and a rear surface; a first covering layer disposed on the front surface of the core layer; a second covering layer disposed on the rear surface of the core layer; an anti-reflection layer disposed on the first covering layer; and a thermal emission layer directly disposed on the anti-reflection layer, wherein: the anti-reflection layer is made of a molybdenum alloy, and the thermal emission layer is made of a ruthenium alloy.

[0005] According to some embodiments of the present disclosure, a method for manufacturing a thin film for a reflective mask includes the following steps: forming a first covering layer over a front surface of a substrate; forming a core layer on the first covering layer; forming a second covering layer on the core layer; forming a protective layer on the covering layer; forming a hard mask layer on a rear surface of the substrate; forming a first opening in the hard mask by patterning the hard mask; forming a second opening in the substrate by etching the substrate through the first opening, thereby exposing the first covering layer in the second opening; removing the protective layer; after removing the protective layer, forming an anti-reflection layer on the first covering layer in the second opening; forming a barrier layer on the anti-reflection layer in the second opening; and forming a thermal emission layer on the barrier layer in the second opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0007] Figure 1A and Figure 1B A cross-sectional view showing a pellicle for an EUV mask according to an embodiment of the present disclosure;

[0008] Figure 2A and Figure 2B A cross-sectional view showing a pellicle for an EUV mask according to an embodiment of the present disclosure;

[0009] Figure 3 shows the lifespan of various thin films according to embodiments of the present disclosure;

[0010] Figure 4 A cross-sectional view showing one of the various stages for manufacturing a pellicle for an EUV photomask according to an embodiment of the present disclosure;

[0011] Figure 5 A cross-sectional view showing one of the various stages for manufacturing a pellicle for an EUV photomask according to an embodiment of the present disclosure;

[0012] Figure 6 A cross-sectional view showing one of the various stages for manufacturing a pellicle for an EUV photomask according to an embodiment of the present disclosure;

[0013] Figure 7 A cross-sectional view showing one of the various stages for manufacturing a pellicle for an EUV photomask according to an embodiment of the present disclosure;

[0014] Figure 8 A cross-sectional view showing one of the various stages for manufacturing a pellicle for an EUV photomask according to an embodiment of the present disclosure;

[0015] Fig. 9 A cross-sectional view showing one of the various stages for manufacturing a pellicle for an EUV photomask according to an embodiment of the present disclosure;

[0016] Fig.10 A cross-sectional view showing one of the various stages for manufacturing a pellicle for an EUV photomask according to an embodiment of the present disclosure;

[0017] Fig.11 A cross-sectional view showing one of the various stages for manufacturing a pellicle for an EUV photomask according to an embodiment of the present disclosure;

[0018] Fig.12 A cross-sectional view showing one of the various stages for manufacturing a pellicle for an EUV photomask according to an embodiment of the present disclosure;

[0019] Fig.13 A cross-sectional view showing one of the various stages for manufacturing a pellicle for an EUV photomask according to an embodiment of the present disclosure;

[0020] Fig.14 A cross-sectional view showing one of the various stages for manufacturing a pellicle for an EUV photomask according to an embodiment of the present disclosure;

[0021] Fig.15 A cross-sectional view showing one of the various stages for manufacturing a pellicle for an EUV photomask according to an embodiment of the present disclosure;

[0022] Fig.16 A cross-sectional view showing a pellicle for an EUV mask according to another embodiment of the present disclosure;

[0023] Fig.17 X-ray diffraction patterns of various materials of a thermal emissive layer of a thin film according to an embodiment of the present disclosure are shown;

[0024] Fig.18 shows a cross-sectional view of a pellicle attached to an EUV reticle according to an embodiment of the present disclosure;

[0025] Fig.19A A flowchart showing a method of manufacturing a semiconductor device, and Fig.19B , Fig.19C , Fig.19D and Fig.19E Sequential manufacturing operations of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure are shown.

[0026]

Explanation of symbols

[0027] 10: Framework structure

[0028] 10S:Substrate

[0029] 20: First covering layer

[0030] 30: Core layer

[0031] 40: Second covering layer

[0032] 50: Protective layer

[0033] 70: Hard Mask Layer

[0034] 80: Photoresist layer

[0035] 90: First Opening

[0036] 95: Second opening / cavity

[0037] 101, 200: Peak

[0038] 110: Anti-reflection layer

[0039] 120: Barrier layer

[0040] 130: Thermal emission layer DETAILED DESCRIPTION

[0041] It should be understood that the following disclosure provides several different embodiments or examples for implementing the different features of the present disclosure. The following describes specific embodiments or examples of components and arrangements to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the size of the component is not limited to the disclosed range or value, but may depend on the process conditions and / or the desired characteristics of the device. In addition, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first and second features are directly contacted, and may also include an embodiment in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. For simplicity and clarity, various features may be arbitrarily drawn in different proportions. In the accompanying drawings, some layers / features may be omitted for simplicity.

[0042] In addition, for ease of description, spatially relative terms such as "below", "under", "below", "above", "above" and the like may be used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. In addition to the orientation shown in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can also be interpreted accordingly. In addition, the term "composed of" may mean "including" or "consisting of". In addition, in the following manufacturing process, there may be one or more additional operations between the described operations, and the order of the operations may change. In the present disclosure, the phrase "at least one of A, B and C" refers to any one of A, B, C, A+B, A+C, B+C or A+B+C, and does not mean one from A, one from B, and one from C, unless otherwise specified. In the present disclosure, unless otherwise specified, a layer made of element X or a layer including element X means that the purity of element X in the layer is greater than 99 atomic %.

[0043] A pellicle is a transparent film stretched on a frame structure that is glued to one side of the mask and protects the mask from particles, dust, damage and / or contamination. Pellicles generally require high transparency and low reflectivity. In UV or DUV lithography, pellicles are made of transparent resin films. However, in EUV lithography, resin-based films are not suitable and non-organic materials such as polysilicon, silicide or graphite are used.

[0044] In the present disclosure, the film for EUV photomask has a stacked structure of various dielectric, semiconductor and / or metal materials to improve EUV transmittance, reduce EUV reflectivity, improve mechanical strength and / or improve thermal properties. In particular, the film according to the present disclosure has an EUV transmittance greater than about 85% in some embodiments, and greater than about 87% in other embodiments, and has an EUV reflectivity less than about 0.25% in some embodiments, and less than about 0.10% in other embodiments.

[0045] Figure 1A and Figure 1B A cross-sectional view of a pellicle for an EUV photomask according to an embodiment of the present disclosure is shown.

[0046] In some embodiments, Figure 1A As shown, the film includes a frame structure 10, a core layer 30 having a front surface and a rear surface and disposed on the frame structure 10, a first cover layer 20 disposed on the rear surface of the core layer 30, a second cover layer 40 disposed on the front surface of the core layer 30, an anti-reflection layer 110 disposed on the second cover layer 40, a barrier layer 120 disposed on the anti-reflection layer 110, and a thermal emission layer 130 disposed on the barrier layer 120. In addition, in some embodiments, the hard mask layer 70 remains at the bottom of the frame structure 10. In some embodiments, the anti-reflection layer 110, the barrier layer 120, and the thermal emission layer 130 are collectively referred to as functional layers.

[0047] In other embodiments, Figure 1B As shown, in the cavity 95 formed by the frame structure 10 , the anti-reflection layer 110 is disposed on the first cover layer 20 , the barrier layer 120 is disposed on the anti-reflection layer 110 , and the thermal emission layer 130 is disposed on the barrier layer 120 .

[0048] In some embodiments, the core layer 30 includes one or more layers of semiconductor materials, such as Si, SiC, and SiGe; metal alloys, such as silicides (WSi, ZrSi, NiSi, TiSi, CoSi, MoSi, etc.); or dielectric materials, such as silicon nitride. In some embodiments, the silicide layer undergoes a nitridation operation or an oxidation operation to form, for example, MoSiN, ZrSiN, MoSiO, or ZrSiO. The semiconductor material may be single crystal, polycrystalline, or amorphous. In some embodiments, polycrystalline silicon or amorphous silicon is used as the core layer 30. In some embodiments, the thickness of the core layer 30 is in the range of about 10 nm to about 50 nm, and in other embodiments, in the range of about 20 nm to about 40 nm.

[0049] In some embodiments, the first capping layer 20 and the second capping layer 40 each include one or more layers of dielectric material or metal material. In some embodiments, one or more of silicon oxide, silicon nitride, silicon oxynitride, SiC, Ni, Al, Cu, Ta, Ti, TaN, or TiN is used as the capping layer. In some embodiments, the thickness of the capping layer is in the range of about 0.5 nm to about 10 nm and in other embodiments in the range of about 2 nm to about 5 nm. In some embodiments, the material of the first capping layer 20 is the same as the material of the second capping layer 40, while in other embodiments, the first capping layer 20 and the second capping layer 40 are made of different materials from each other.

[0050] In some embodiments, the anti-reflection layer 110 includes Mo (purity greater than 99 atomic %) or a Mo alloy. In some embodiments, the Mo alloy is a Mo nitride, a Mo oxide, or a Mo oxynitride. The Mo alloy includes Mo and one or more of C, B, Si, or P. In some embodiments, the amount of Mo in the Mo alloy is in the range of about 50 atomic % to about 99 atomic %. When the amount of Mo is less than this range, the anti-reflection performance will be insufficient. In some embodiments, the Mo nitride, the Mo oxide, or the Mo oxynitride further includes one or more of C, B, Si, or P in an amount of 1 atomic % to about 20 atomic %. In some embodiments, the thickness of the anti-reflection layer 110 is in the range of about 0.5 nm to about 10 nm, and in other embodiments, in the range of about 1 nm to about 5 nm.

[0051] The thermal emission layer 130 is the topmost layer of the film and has a higher thermal emissivity (heat dissipation) than the anti-reflection layer 110 to protect the film from cracking, which would otherwise be caused by exposure to EUV light. In some embodiments, the thermal emission layer 130 includes ruthenium Ru (ruthenium, purity greater than 99 atomic %) or a Ru alloy. In some embodiments, the Ru alloy includes Ru and at least one element selected from the group consisting of Ir, Nb, Ti, V, Mo, Zr, B, P and Si, wherein the majority (more than 50 atomic %) of the alloy is Ru. In some embodiments, the Ru alloy is composed of Ru 1-x M x , wherein M is at least one selected from the group consisting of Ir, Nb, Ti, V, Mo, and Zr. In some embodiments, x is greater than zero and equal to or less than 0.4. In other embodiments, x is in the range of about 0.1 to about 0.2. When the amount of M is less than the disclosed range, as described below, Mo diffusion suppression will be insufficient, and when the amount of M is greater than the range, heat dissipation will be reduced.

[0052] In some embodiments, Ru 1-x M xThe Ru alloy represented further includes at least one dopant selected from the group consisting of B, P, and Si. In some embodiments, the amount of the dopant is in the range of about 0.1 atomic % to about 10 atomic %, and in other embodiments in the range of about 1 atomic % to about 5 atomic %.

[0053] In certain embodiments, the thermal emission layer 130 is made of one or more layers of RuNb, RuMo, RuV, RuTi, or RuZr, wherein the amount of Ru is in the range of about 60 atomic % or more and about 99 atomic % or less.

[0054] When the anti-reflection layer 110 is made of Mo or a Mo alloy with a high Mo concentration, Mo may diffuse into the thermal emission layer 130 and may reduce the performance (e.g., crack strength) of the thermal emission layer 130 made of Ru or a Ru alloy with a high Ru concentration. In some embodiments of the present disclosure, the barrier layer 120 is disposed between the anti-reflection layer 110 and the thermal emission layer 130 to prevent or inhibit Mo from diffusing into the thermal emission layer 130.

[0055] In some embodiments, the barrier layer 120 is made of a different material (different composition) than the thermal emission layer. In some embodiments, the barrier layer 120 comprises a Ru alloy. In some embodiments, the Ru alloy comprises Ru and at least one element selected from the group consisting of Ir, Nb, Ti, V, Mo, and Zr, wherein a majority (greater than 50 atomic %) of the alloy is Ru. In some embodiments, the Ru alloy is composed of Ru 1-y M y , wherein M is at least one selected from the group consisting of Ir, Nb, Ti, V, Mo, and Zr, and y>x. In some embodiments, y is greater than zero and equal to or less than 0.5. In some embodiments, the thickness of the barrier layer 120 is in a range of about 0.5 nm to about 5 nm, and in other embodiments, in a range of about 1 nm to about 2 nm.

[0056] In some embodiments, at least one of the thermal emission layer 130 and the barrier layer 120 is a mixture of amorphous and polycrystalline.

[0057] In some embodiments, the functional layer of the thin film includes an anti-reflection layer 110 made of Mo, a barrier layer 120 made of the above-mentioned Ru alloy, and a thermal emission layer 130 made of Ru. In some embodiments, the functional layer of the thin film includes an anti-reflection layer 110 made of Mo, a barrier layer 120 made of the above-mentioned Ru alloy, and a thermal emission layer 130 made of the above-mentioned Ru alloy. In some embodiments, the functional layer of the thin film includes an anti-reflection layer 110 made of the above-mentioned Mo alloy, a barrier layer 120 made of the above-mentioned Ru alloy, and a thermal emission layer 130 made of the above-mentioned Ru alloy.

[0058] Figure 2A and Figure 2B A cross-sectional view of a pellicle for an EUV photomask according to an embodiment of the present disclosure is shown.

[0059] In some embodiments, no barrier layer is used, and the thermal emission layer 130 is disposed directly on the anti-reflection layer 110, such as Figure 2A and Figure 2B However, in this case, in order to prevent Mo from diffusing into the thermal emission layer 130, at least one of the anti-reflection layer or the thermal emission layer is made of a Mo alloy or a Ru alloy.

[0060] In some embodiments, the functional layer of the thin film includes an anti-reflection layer 110 made of Mo and a thermal emission layer 130 made of the above-mentioned Ru alloy. In some embodiments, the functional layer of the thin film includes an anti-reflection layer 110 made of the above-mentioned Mo alloy and a thermal emission layer 130 made of Ru. In some embodiments, the functional layer of the thin film includes an anti-reflection layer 110 made of the above-mentioned Mo alloy and a thermal emission layer 130 made of the above-mentioned Ru alloy.

[0061] Figure 3 The lifetimes of various thin films according to embodiments of the present disclosure are shown. Figure 3 The number of wafers processed by the EUV lithography equipment before replacing the pellicle is shown to avoid destructive cracking of the pellicle. When an EUV reflective mask with a pellicle is used in an EUV lithography equipment, EUV light irradiating the pellicle causes heating, which reduces the strength of the pellicle and may cause cracking of the pellicle. Therefore, the pellicle must be regularly replaced with a new pellicle after a certain number of EUV exposures. In some embodiments, the life of the pellicle is defined as the number of wafers processed by using the EUV mask with the pellicle. Since the wafer includes multiple exposure areas, the number of exposures of the pellicle is greater than the number of wafers processed.

[0062] When the film does not include a barrier layer and an anti-reflection layer made of Mo and a thermal emission layer made of Ru, the life of the film is about 20,000 wafers. When the film does not include a barrier layer, an anti-reflection layer made of Mo and a thermal emission layer made of the above Ru alloy, the life of the film increases to about 50,000 wafers. When the film includes a barrier layer made of the above Ru alloy, an anti-reflection layer made of the above Mo alloy and a thermal emission layer made of the above Ru alloy, the life of the film increases to about 80,000 wafers. Figure 3 As shown, using an alloy layer as a thermal emission layer and / or using a barrier layer can significantly increase the lifetime of the thin film by preventing Mo from diffusing into the thermal emission layer.

[0063] Figures 4 to 15 1 shows sequential manufacturing operations for a pellicle for an EUV mask according to an embodiment of the present disclosure. It should be understood that Figures 4 to 15Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes may be interchanged. Figure 1A , Figure 1B , Figure 2A and Figure 2B The described materials, configurations, dimensions and / or operations are applied to the following embodiments, and a detailed description thereof may be omitted.

[0064] like Figure 4 As shown, a substrate 10S, such as a Si wafer, is prepared. In some embodiments, the thickness of the substrate 10S is in a range of about 500 μm to about 1000 μm.

[0065] On the substrate 10S, a first covering layer 20 is formed, such as Figure 5 As shown. In some embodiments, the first capping layer 20 is used as an etch stop layer in subsequent substrate etching operations. The first capping layer 20 includes one or more layers of semiconductor materials, such as SiC, SiGe, SiCN, Ge, or dielectric materials, such as silicon oxide, silicon nitride and silicon oxynitride, or any other suitable material. In other embodiments, the first capping layer 20 may be an amorphous or polycrystalline SiC, SiGe or Ge layer. In certain embodiments, the first capping layer 20 is silicon nitride. In some embodiments, the thickness of the first capping layer is in the range of about 0.5 nm to about 20 nm, and in other embodiments, in the range of about 2 nm to about 5 nm. The first capping layer 20 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE) and any other suitable film forming method.

[0066] After forming the first cover layer 20, a core layer 30 is formed on the first cover layer 20. Figure 6 As shown. The core layer 30 includes one or more layers of semiconductor materials, such as Si, SiC, SiGe; metal alloys, such as silicides (WSi, NiSi, TiSi, CoSi, MoSi, etc.); or dielectric materials, such as silicon nitride. The semiconductor material may be single crystal, polycrystalline or amorphous. In other embodiments, polycrystalline silicon or amorphous silicon is used as the core layer 30. The core layer 30 may be formed by CVD, PVD, ALD, MBE, and any other suitable film forming method.

[0067] Then, a second covering layer 40 is formed as a covering layer on the core layer 30, such as Figure 7In some embodiments, the second capping layer 40 includes one or more layers of silicon nitride, SiC or SiCN. In other embodiments, the second capping layer 40 is formed by implanting impurities in the Si core layer. The impurities may be boron, phosphorus and / or arsenic. In some embodiments, the dosage of the impurities is about 10 17 ions / cm -2 Up to 10 20 ions / cm -2 In some embodiments, the thickness of the second capping layer 40 is in the range of about 0.5 nm to about 10 nm, and in other embodiments, in the range of about 2 nm to about 5 nm. The second capping layer 40 can be formed by CVD, PVD, ALD, MBE, and any other suitable film forming method.

[0068] Then, if Figure 8 As shown, a protective layer 50 is formed over the second capping layer 40. The protective layer 50 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, silicon oxide is used. In some embodiments, the thickness of the protective layer 50 is in the range of about 100 nm to about 10 μm. The protective layer 50 can be formed by CVD, PVD, ALD, MBE, and any other suitable film forming method. In some embodiments, the protective layer 50 includes one or more layers of metal-based materials, such as Al, Cu, Ta, Ti, Co, Fe, Ni, TaN or TiN and alloys thereof. In some embodiments, the protective layer 50 may also be a metal oxide, a metal nitride, such as SiN, SiO, or SiON. In some embodiments, multiple layers with different materials are used as the protective layer 50.

[0069] Then, if Fig. 9 As shown, a hard mask layer 70 is formed over the back side of the substrate 10S. The hard mask layer 70 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or SiCN. In some embodiments, silicon nitride is used. In some embodiments, the thickness of the hard mask layer 70 is in the range of about 100 nm to about 1000 nm, and in other embodiments, in the range of about 200 nm to about 500 nm. The hard mask layer 70 can be formed by CVD, PVD, ALD, MBE, and any other suitable film forming method.

[0070] Then, a photoresist layer 80 is formed on the hard mask layer 70. Fig.10 In some embodiments, the thickness of the photoresist layer 80 is in the range of about 1 μm to about 3 μm. One or more lithography operations are performed to pattern the photoresist layer 80, and then, one or more etching operations are performed to pattern the hard mask layer 70 to form a Fig.11 A first opening 90 is shown. The photoresist layer 80 is removed by a suitable photoresist removal operation.

[0071] Then, the substrate 10S is etched to form a second opening (cavity) 95 surrounded by the frame structure 10, as shown in FIG. Fig.12 As shown. In some embodiments, wet etching using KOH, TMAH (tetramethylammonium hydroxide) or EDP (ethylenediamine catechol) is performed to etch the Si substrate 10S. The substrate 10S may also be etched by a dry etching process using one or more of SF6, CF4 and Cl2 gases mixed with N2 and / or O2 gases. In some embodiments, the substrate below the first opening 90 is etched to expose the first capping layer 20 used as an etching stop layer. Through the etching operation, a portion of the substrate 10S and a portion of the hard mask layer 70 form a frame structure of a thin film. In some embodiments, a hard mask layer is not used, a photoresist layer 80 is formed on the back side of the substrate 10S, and the back side of the substrate 10S is etched to form a second opening 95.

[0072] Then, the protective layer 50 is removed by one or more etching operations, such as Fig.13 In some embodiments, a wet etching operation is used.

[0073] Then, if Fig.14 As shown, functional layers including an anti-reflection layer 110, a barrier layer 120, and a thermal emission layer 130 are sequentially formed above the second capping layer 40. In some embodiments, a barrier layer is not formed, and the thermal emission layer 130 is directly formed on the anti-reflection layer 110. The functional layers 110, 120, and 130 can be formed by CVD, PVD, ALD, electroplating, and any other suitable film forming method, respectively. In some embodiments, when the functional layers are formed by sputtering, the functional layers are sequentially formed by changing the sputtering target in the same processing chamber (or equipment) without breaking the vacuum. In some embodiments, the hard mask layer 70 is removed. In some embodiments, the functional layers are formed by a sputtering method at a substrate temperature of about 500° C. to about 700° C.

[0074] exist Figure 1B and Figure 2B In other embodiments of the structure, after removing the protective layer 50, flipping Fig.13 The structure shown in FIG. 1 is a structure in which the functional layer is formed on the first cover layer 20 within the second opening 95 surrounded by the frame structure 10. In some embodiments, the hard mask layer 70 on which the functional layer is deposited is removed.

[0075] Fig.16 A cross-sectional view of a pellicle for EUV photomask according to an embodiment of the present disclosure is shown. In this embodiment, the frame structure 10 has a tapered shape with a larger opening on the hard mask layer 70 side than on the first cover layer 20 side. The taper angle is less than 90 degrees and equal to or greater than 70 degrees.

[0076] Fig.17 FIG. 1 shows X-ray diffraction patterns of various materials of the thermal emission layer of the thin film according to an embodiment of the present disclosure. When the thermal emission layer 130 is made of Ru, the Ru layer generally has Fig.17 In contrast, when the thermal emission layer 130 is made of a Ru alloy, the Ru alloy includes about 15 atomic % of Ru and one of Mo, Zr, Ti or Nb, and the Ru alloy layer is a mixture of amorphous and crystalline (polycrystalline), such as Fig.17 As shown in the XRD pattern of ((101) peak is smaller than (110) and (200) peaks)). In some embodiments, the Ru alloy layer is formed at a temperature of about 600°C. By adjusting the deposition conditions, the amount of amorphous phase in the Ru alloy layer can be controlled. In the present disclosure, by using a Ru alloy layer including an amorphous and crystalline (polycrystalline) structure, Mo diffusion can be suppressed and the breaking strength and heat dissipation performance can be improved.

[0077] The EUV transmittance and reflectance values ​​of the thin film at a wavelength of 13.5 nm can be adjusted by selecting the material and / or thickness of the stacked structure of the thin film. By selecting the material and / or thickness of the stacked layers of the EUV thin film, an EUV transmittance of more than about 85% in some embodiments, and more than about 87% (and up to about 90%) in other embodiments, and an EUV reflectivity of less than 0.25% in some embodiments, and less than 0.10% (or even less than 0.05% and as little as 0.01%) in other embodiments can be obtained.

[0078] Fig.18 A cross-sectional view of a film attached to an EUV mask according to an embodiment of the present disclosure is shown. The frame structure of the film is attached to the surface of the EUV mask using a suitable adhesive material. The adhesive material is an adhesive such as an acrylic or silicone-based adhesive or an AB cross-linked adhesive. The size of the frame structure is larger than the black border area of ​​the EUV mask, so that the film covers not only the circuit pattern area of ​​the mask, but also the black border.

[0079] Fig.19A A flowchart showing a method of manufacturing a semiconductor device, and Fig.19B , Fig.19C , Fig.19D and Fig.19E Sequential manufacturing operations of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure are shown. A semiconductor substrate or other suitable substrate to be patterned to form an integrated circuit thereon is provided. In some embodiments, the semiconductor substrate comprises silicon. Alternatively or additionally, the semiconductor substrate comprises germanium, silicon germanium, or other suitable semiconductor material, such as a III-V semiconductor material. Fig.19AAt S101, a target layer to be patterned is formed above a semiconductor substrate. In some embodiments, the target layer is a semiconductor substrate. In some embodiments, the target layer includes: a conductive layer, such as a metal layer or a polysilicon layer; a dielectric layer, such as silicon oxide, silicon nitride, SiON, SiOC, SiOCN, SiCN, hafnium oxide, or aluminum oxide; or a semiconductor layer, such as an epitaxially formed semiconductor layer. In some embodiments, the target layer is formed on an underlying structure, such as an isolation structure, a transistor, or a wiring. Fig.19A At S102, a photoresist layer is formed on the target layer, such as Fig.19B As shown. In the subsequent lithography exposure process, the photoresist layer is sensitive to radiation from the exposure source. In this embodiment, the photoresist layer is sensitive to EUV light used in the lithography exposure process. The photoresist layer can be formed on the target layer by spin coating or other suitable techniques. The coated photoresist layer can be further baked to drive out the solvent in the photoresist layer. Fig.19A At S103, the photoresist layer is patterned using an EUV reflective mask, such as Fig.19B As shown. The step of patterning the photoresist layer includes the following steps: performing a lithography exposure process using an EUV mask through an EUV exposure system. In the exposure process, the integrated circuit (IC) design pattern defined on the EUV mask is imaged onto the photoresist layer to form a latent pattern thereon. The step of patterning the photoresist layer further includes the following steps: developing the exposed photoresist layer to form a patterned photoresist layer having one or more openings. In an embodiment in which the photoresist layer is a positive photoresist layer, the exposed portion of the photoresist layer is removed in the development process. The step of patterning the photoresist layer may further include other process steps, such as various baking steps at different stages. For example, a post-exposure-baking (PEB) process may be implemented after the lithography exposure process and before the development process.

[0080] exist Fig.19A At S104, the target layer is patterned using the patterned photoresist layer as an etching mask, such as Fig.19D In some embodiments, the step of patterning the target layer includes the following steps: applying an etching process to the target layer using the patterned photoresist layer as an etching mask. Etching the portion of the target layer exposed within the opening of the patterned photoresist layer, while the remaining portion is exempted from etching. Further, the patterned photoresist layer may be removed by wet stripping or plasma ashing, such as Fig.19E shown.

[0081] In the present disclosure, the functional layer of the film for the EUV reflective mask includes a barrier layer between the anti-reflection layer and the thermal emission layer to prevent Mo from diffusing from the anti-reflection layer to the thermal emission layer. Therefore, the life of the film can be extended without reducing the EUV transmittance of the film. In other embodiments, even without the barrier layer, the functional layer of the film includes an anti-reflection layer made of a Mo alloy and / or a thermal emission layer made of a Ru alloy, which can prevent Mo from diffusing from the anti-reflection layer to the thermal emission layer. Therefore, the life of the film can be extended without reducing the EUV transmittance of the film. The film according to the embodiment of the present disclosure can provide higher strength and thermal conductivity (heat dissipation) as well as higher EUV transmittance and lower EUV reflectivity.

[0082] It should be understood that not all advantages are necessarily discussed herein, that a particular advantage is not required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

[0083] According to another aspect of the present disclosure, a film for a reflective mask includes a frame, a core layer having a front surface and a rear surface and disposed above the frame, a first covering layer disposed on the front surface of the core layer, an anti-reflection layer disposed on the first covering layer, a barrier layer disposed on the anti-reflection layer, and a thermal emission layer disposed on the barrier layer. In one or more of the foregoing and following embodiments, the thermal emission layer includes ruthenium (Ru) and at least one selected from the group consisting of iridium (Ir), niobium (Nb), titanium (Ti), vanadium (V), molybdenum (Mo), zirconium (Zr), boron (B), P, and silicon (Si). In one or more of the foregoing and following embodiments, the thermal emission layer includes Ru 1-x M x , wherein M is at least one selected from the group consisting of iridium (Ir), niobium (Nb), titanium (Ti), vanadium (V), molybdenum (Mo) and zirconium (Zr). In one or more of the foregoing and following embodiments, x is greater than zero and equal to or less than 0.4. In one or more of the foregoing and following embodiments, the thermal emission layer further includes at least one selected from the group consisting of boron (B), phosphorus (P) and silicon (Si). In one or more of the foregoing and following embodiments, the barrier layer is made of a material different from that of the thermal emission layer and includes a ruthenium (Ru) alloy. In one or more of the foregoing and following embodiments, the ruthenium (Ru) alloy is at least one selected from the group consisting of ruthenium iridium (RuIr), niobium baht (BuNb), ruthenium titanium (RuTi), ruthenium zirconium (RuZr) and ruthenium vanadium (RuV). In one or more of the foregoing and following embodiments, the barrier layer includes Ru 1-y M y, wherein M is at least one selected from the group consisting of iridium (Ir), niobium (Nb), titanium (Ti), vanadium (V), molybdenum (Mo) and zirconium (Zr), and y>x. In one or more of the foregoing and following embodiments, the anti-reflection layer includes molybdenum (Mo) and at least one selected from the group consisting of carbon (C), boron (B), silicon (Si) and phosphorus (P). In one or more of the foregoing and following embodiments, the thin film further includes a second capping layer disposed on the rear surface of the core layer. In one or more of the foregoing and following embodiments, the first capping layer and the second capping layer each include at least one of silicon nitride or silicon carbide. In one or more of the foregoing and following embodiments, the thermal emission layer is a mixture of polycrystalline and amorphous.

[0084] According to another aspect of the present disclosure, a film for a reflective mask includes a core layer having a front surface and a rear surface, a first covering layer disposed on the front surface of the core layer, a second covering layer disposed in the rear surface of the core layer, an anti-reflection layer disposed on the first covering layer, and a thermal emission layer disposed directly on the anti-reflection layer. The anti-reflection layer is made of a molybdenum (Mo) alloy, and the thermal emission layer is made of a ruthenium (Ru) alloy. In one or more of the foregoing and following embodiments, the thermal emission layer includes Ru 1-x M x , wherein M is at least one selected from the group consisting of iridium (Ir), niobium (Nb), titanium (Ti), vanadium (V), molybdenum (Mo), and zirconium (Zr). In one or more of the foregoing and following embodiments, x is greater than zero and equal to or less than 0.4. In one or more of the foregoing and following embodiments, the anti-reflection layer includes molybdenum (Mo) and at least one selected from the group consisting of carbon (C), boron (B), silicon (Si), and phosphorus (P). In one or more of the foregoing and following embodiments, the thickness of the thermal emission layer is in the range of 0.2 nm to 5 nm. In one or more of the foregoing and following embodiments, the thickness of the anti-reflection layer is in the range of 0.2 nm to 5 nm.

[0085] According to another aspect of the present disclosure, a film for a reflective mask includes a frame structure having a cavity, a first cover layer disposed on the frame, a core layer disposed on the first cover layer, a second cover layer disposed on the core layer, an anti-reflection layer disposed on the first cover layer in the cavity, a barrier layer disposed on the anti-reflection layer in the cavity, and a thermal emission layer disposed on the barrier layer in the cavity. In one or more of the above and following embodiments, the anti-reflection layer is made of molybdenum (Mo) or a molybdenum (Mo) alloy, the thermal emission layer is made of ruthenium (Ru) or a first ruthenium (Ru) alloy, and the barrier layer is made of a second ruthenium (Ru) alloy and has a lower ruthenium (Ru) concentration than the thermal emission layer.

[0086] According to one aspect of the present disclosure, in a method for manufacturing a thin film for a reflective mask, a first capping layer is formed over a front surface of a substrate, a core layer is formed over the first capping layer, a second capping layer is formed over the core layer, a protective layer is formed over the second capping layer, a hard mask layer is formed over a rear surface of the substrate, a first opening is formed in the hard mask by patterning the hard mask, a second opening is formed in the substrate by etching the substrate through the first opening, the protective layer is removed, an anti-reflection layer is formed on the second capping layer after removing the protective layer, a barrier layer is formed on the anti-reflection layer, and a thermal emission layer is formed on the barrier layer. In one or more of the foregoing and following embodiments, the thermal emission layer includes ruthenium (Ru) and at least one selected from the group consisting of iridium (Ir), niobium (Nb), titanium (Ti), vanadium (V), molybdenum (Mo), zirconium (Zr), boron (B), phosphorus (P), and silicon (Si). In one or more of the foregoing and following embodiments, the thermal emission layer includes Ru 1-x M x , wherein M is at least one selected from the group consisting of iridium (Ir), niobium (Nb), titanium (Ti), vanadium (V), molybdenum (Mo) and zirconium (Zr). In one or more of the foregoing and following embodiments, x is greater than zero and equal to or less than 0.4. In one or more of the foregoing and following embodiments, the thermal emission layer further includes at least one selected from the group consisting of boron (B), phosphorus (P) and silicon (Si). In one or more of the foregoing and following embodiments, the barrier layer is made of a material different from that of the thermal emission layer and includes a ruthenium (Ru) alloy. In one or more of the foregoing and following embodiments, the ruthenium (Ru) alloy is at least one selected from the group consisting of ruthenium iridium (RuIr), niobium baht (BuNb), ruthenium titanium (RuTi), ruthenium zirconium (RuZr) and ruthenium vanadium (RuV). In one or more of the foregoing and following embodiments, the barrier layer includes Ru 1-y M y , wherein M is at least one selected from the group consisting of iridium (Ir), niobium (Nb), titanium (Ti), vanadium (V), molybdenum (Mo) and zirconium (Zr), and y>x. In one or more of the foregoing and following embodiments, the anti-reflection layer includes molybdenum (Mo) and at least one selected from the group consisting of carbon (C), boron (B), silicon (Si) and phosphorus (P). In one or more of the foregoing and following embodiments, the first capping layer and the second capping layer each include at least one of silicon nitride or silicon carbide. In one or more of the foregoing and following embodiments, the thermal emission layer is a mixture of polycrystalline and amorphous.

[0087] According to another aspect of the present disclosure, in a method for manufacturing a thin film for a reflective mask, a first covering layer is formed over a front surface of a substrate, a core layer is formed over the first covering layer, a second covering layer is formed over the core layer, a protective layer is formed over the second covering layer, a hard mask layer is formed over a rear surface of the substrate, a first opening is formed in the hard mask by patterning the hard mask, a second opening is formed in the substrate by etching the substrate through the first opening, the protective layer is removed, an anti-reflection layer is formed on the second covering layer after the protective layer is removed, and a thermal emission layer is formed directly on the anti-reflection layer. The anti-reflection layer is made of a molybdenum (Mo) alloy, and the thermal emission layer is made of a ruthenium (Ru) alloy. In one or more of the foregoing and following embodiments, the thermal emission layer includes Ru 1-x M x , wherein M is at least one selected from the group consisting of iridium (Ir), niobium (Nb), titanium (Ti), vanadium (V), molybdenum (Mo), and zirconium (Zr). In one or more of the foregoing and following embodiments, x is greater than zero and equal to or less than 0.4. In one or more of the foregoing and following embodiments, the anti-reflection layer includes molybdenum (Mo) and at least one selected from the group consisting of carbon (C), boron (B), silicon (Si), and phosphorus (P). In one or more of the foregoing and following embodiments, the thickness of the thermal emission layer is in the range of 0.2 nm to 5 nm. In one or more of the foregoing and following embodiments, the thickness of the anti-reflection layer is in the range of 0.2 nm to 5 nm.

[0088] According to another aspect of the present disclosure, in a method for manufacturing a thin film for a reflective mask, a first capping layer is formed over a front surface of a substrate, a core layer is formed over the first capping layer, a second capping layer is formed over the core layer, a protective layer is formed over the second capping layer, a hard mask layer is formed over a rear surface of the substrate, a first opening is formed in the hard mask by patterning the hard mask, a second opening is formed in the substrate by etching the substrate through the first opening, thereby exposing the first capping layer in the second opening, the protective layer is removed, and after removing the protective layer, an anti-reflection layer is formed on the first capping layer in the second opening, a barrier layer is formed on the anti-reflection layer in the second opening, and a thermal emission layer is formed on the barrier layer in the second opening. In one or more of the foregoing and following embodiments, the anti-reflection layer is made of molybdenum (Mo) or a molybdenum (Mo) alloy, the thermal emission layer is made of ruthenium (Ru) or a first ruthenium (Ru) alloy, and the barrier layer is made of a second ruthenium (Ru) alloy having a lower ruthenium (Ru) concentration than the thermal emission layer. In one or more of the foregoing and following embodiments, the anti-reflection layer is made of a molybdenum (Mo) alloy, the thermal emission layer is made of a first ruthenium (Ru) alloy, and the barrier layer is made of a second ruthenium (Ru) alloy, wherein the ruthenium (Ru) concentration of the second ruthenium (Ru) alloy is lower than that of the first ruthenium (Ru) alloy.

[0089] The features of several embodiments or examples are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that those skilled in the art can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments or examples introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and these equivalent constructions can be variously changed, substituted and modified without departing from the spirit and scope of the present disclosure.

Claims

1. A film for a reflective mask, characterized in that: Include: A framework; a core layer having a front surface and a rear surface and disposed above the frame; a first covering layer disposed on the front surface of the core layer, wherein the first covering layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, nickel, aluminum, copper, tantalum, titanium, tantalum nitride or titanium nitride; an anti-reflection layer disposed on the first covering layer, wherein the anti-reflection layer comprises molybdenum or a molybdenum alloy; a barrier layer disposed on the anti-reflection layer; and A thermal emission layer is disposed on the barrier layer, wherein the thermal emission layer includes ruthenium or a first ruthenium alloy, and the barrier layer includes a second ruthenium alloy, and the ruthenium concentration of the second ruthenium alloy is lower than the ruthenium concentration of the first ruthenium alloy.

2. The film according to claim 1, characterized in that The thermal emission layer includes ruthenium and at least one selected from the group consisting of iridium, niobium, zirconium, titanium, vanadium, molybdenum, boron, phosphorus and silicon.

3. The film according to claim 1, characterized in that The thermal emission layer includes Ru 1-x M x , wherein M is at least one selected from the group consisting of iridium, niobium, titanium, vanadium, molybdenum and zirconium.

4. The film according to claim 3, characterized in that x is greater than zero and equal to or less than 0.

4.

5. The film according to claim 3, characterized in that The thermal emission layer further includes at least one selected from the group consisting of boron, phosphorus, and silicon.

6. The film according to claim 4, characterized in that x is in the range of 0.1 to 0.

2.

7. The film according to claim 1, characterized in that The first ruthenium alloy is at least one selected from the group consisting of ruthenium iridium, ruthenium niobium, ruthenium titanium, ruthenium zirconium and ruthenium vanadium.

8. The film according to claim 3, characterized in that The barrier layer includes Ru 1-y M y , wherein M is at least one selected from the group consisting of iridium, niobium, titanium, vanadium, molybdenum and zirconium.

9. The film according to claim 1, characterized in that The anti-reflection layer further includes at least one selected from the group consisting of carbon (C), boron (B), silicon (Si) and phosphorus (P).

10. The film according to claim 1, characterized in that Further comprising a second covering layer disposed on the rear surface of the core layer, wherein the second covering layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, nickel, aluminum, copper, tantalum, titanium, tantalum nitride or titanium nitride.

11. The film according to claim 10, characterized in that The first capping layer and the second capping layer each include at least one of silicon nitride or silicon carbide.

12. The film according to claim 1, characterized in that The heat emission layer is a mixture of polycrystalline and amorphous.

13. A film for a reflective mask, characterized in that: Include: a core layer having a front surface and a rear surface; a first covering layer disposed on the front surface of the core layer, wherein the first covering layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, nickel, aluminum, copper, tantalum, titanium, tantalum nitride or titanium nitride; a second covering layer disposed on the rear surface of the core layer, wherein the second covering layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, nickel, aluminum, copper, tantalum, titanium, tantalum nitride or titanium nitride; an anti-reflection layer disposed on the first covering layer; and A thermal emission layer is directly disposed on the anti-reflection layer, wherein: The anti-reflection layer is made of a molybdenum alloy, and The heat emission layer is made of a ruthenium alloy.

14. The film according to claim 13, characterized in that The thermal emission layer includes Ru 1-x M x , wherein M is at least one selected from the group consisting of iridium, niobium, titanium, vanadium, molybdenum and zirconium.

15. The film according to claim 14, characterized in that x is greater than zero and equal to or less than 0.

4.

16. The film according to claim 13, characterized in that The anti-reflection layer includes molybdenum and at least one selected from the group consisting of carbon, boron, silicon and phosphorus.

17. The film according to claim 13, characterized in that The thickness of the thermal emission layer is in the range of 0.2 nm to 5 nm.

18. The film according to claim 13, characterized in that The thickness of the anti-reflection layer is in the range of 0.2 nm to 5 nm.

19. A method for manufacturing a thin film for a reflective mask, characterized in that: The following steps are involved: forming a first capping layer over a front surface of a substrate, wherein the first capping layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, nickel, aluminum, copper, tantalum, titanium, tantalum nitride, or titanium nitride; forming a core layer on the first cover layer; forming a second capping layer on the core layer, wherein the second capping layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, nickel, aluminum, copper, tantalum, titanium, tantalum nitride, or titanium nitride; forming a protective layer on the second covering layer; forming a hard mask layer on a rear surface of the substrate; forming a first opening in the hard mask by patterning the hard mask; forming a second opening in the substrate by etching the substrate through the first opening, thereby exposing the first capping layer in the second opening; removing the protective layer; After removing the protective layer, forming an anti-reflection layer on the first covering layer in the second opening, wherein the anti-reflection layer comprises molybdenum or a molybdenum alloy; forming a barrier layer on the anti-reflection layer in the second opening; and A thermal emission layer is formed on the barrier layer in the second opening, wherein the thermal emission layer includes ruthenium or a first ruthenium alloy, and the barrier layer includes a second ruthenium alloy, and the ruthenium concentration of the second ruthenium alloy is lower than the ruthenium concentration of the first ruthenium alloy.

20. The method of claim 19, wherein: The thermal emission layer includes ruthenium and at least one selected from the group consisting of iridium, niobium, zirconium, titanium, vanadium, molybdenum, boron, phosphorus and silicon.

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