A system and method for optimizing DDS output signal spurious by switching system clock

Abstract

The present invention provides a system and method for optimizing DDS output signal spuriousness by switching the system clock. A switching filter is added after the DDS, and the referenced phase-locked loop (PLL) switches between two or more frequency points. DDS clock switching is achieved by switching the PLL frequency points. The signal is then filtered in sections through filtering. By switching the DDS clock, a relatively wide output signal is achieved while minimizing output signal spuriousness.

Description

Technical Field

[0001] The invention relates to a system and method for switching system clocks to optimize DDS output signal spuriousness, belonging to the field of control technology. Background Art

[0002] One implementation of a broadband source is to use DDS to generate a signal of a certain bandwidth, then mix and filter the signal in sections (possibly multiple mixings) to output a broadband signal. Figure 1 Limited by the spurious characteristics of DDS itself, under the premise of ensuring the spurious indicators, the DDS output frequency range is relatively small and the bandwidth is very narrow, which causes great trouble for the subsequent mixing and filtering.

[0003] Specifically, the reference signal enters the phase-locked loop (PLL), generating a 3.5GHz dot-frequency signal that is output to the DDS as the system clock. The DDS chip model is the AD9914. Software control of the DDS can output a 0-1.4GHz signal. However, due to the inherent performance characteristics of the DDS, the output signal bandwidth is limited while ensuring spurious performance. For example, a 250-490MHz output is used. This signal is then mixed with frequency hopping source 1 and segmented filtered to produce a higher-frequency, wider-bandwidth signal, such as 3-5GHz. The 3-5GHz signal is then mixed with frequency hopping source 2, further widening the bandwidth to, for example, 6-18GHz. This results in a 6-18GHz wideband signal.

[0004] Therefore, the existing technology is limited by the bandwidth of the DDS output signal, and the mixing with the frequency hopping source 1 and the subsequent segmented filtering design are relatively complex and have many segments. Summary of the Invention

[0005] In response to the above technical problems, the purpose of the present invention is to provide a system and method for switching the system clock to optimize the DDS output signal spuriousness, which can increase the bandwidth of the DDS output signal and reduce the design difficulty of subsequent mixing with the frequency hopping source 1 and segmented filtering.

[0006] In order to solve the above problems, the technical solution adopted by the present invention is:

[0007] First, a system for switching system clock to optimize DDS output signal spuriousness is provided, which includes a PLL, a DDS, and a filter group in sequence. At least two mixers connected to a frequency hopping source are connected to the filter group in sequence, and a filter group is provided between the mixers connected to the frequency hopping source.

[0008] The present invention also provides a method for switching the system clock to optimize the DDS output signal spuriousness. A level of switch filtering is added after the DDS. At the same time, the phase-locked loop after the reference is changed into two or more point frequency switching. The DDS clock switching is achieved by switching the frequency of the phase-locked loop; and then the signal is segmented and filtered through filtering.

[0009] The method provided by the present invention increases the bandwidth of the DDS output signal by switching the clock, reduces the difficulty of the mixing and filter group of the frequency hopping source 1, and mainly has the advantage of cost.

[0010] In addition, clock switching requires changing the PPL output frequency, which only requires modifying the program and has no hardware cost. The added filter group after the DDS has a low switching cost due to its low frequency, and the filter can be designed with LC, so the total cost is very low.

[0011] In summary, the present invention obtains a relatively wide output signal by switching the DDS clock while ensuring that the output signal is spurious. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is the principle diagram of broadband source of prior art;

[0013] Figure 2 It is a schematic diagram of the broadband source generation scheme of the present invention. DETAILED DESCRIPTION

[0014] The embodiments of the present invention are further described below with reference to the accompanying drawings, but the present invention is not limited to the following embodiments:

[0015] like Figure 2 As shown, a system for switching system clock to optimize DDS output signal spurious includes a PLL, a DDS, and a filter group in sequence. The filter group is connected in sequence to at least two mixers connected to a frequency hopping source, and a filter group is provided between the mixers connected to the frequency hopping source.

[0016] A method for switching the system clock to optimize DDS output signal spuriousness. A switch filter is added after the DDS. At the same time, the phase-locked loop after the reference is switched into two or more frequency points. The DDS clock switching is achieved by switching the frequency of the phase-locked loop. The signal is then filtered in sections.

[0017] The present invention adds a switching filter group behind the DDS, and at the same time, the referenced phase-locked loop is changed into two or more frequency switching points. The DDS clock switching is realized by switching the frequency point of the phase-locked loop, avoiding some spurious signals. Then, the signal is segmented and filtered through the subsequent switching filter group to ensure the output signal spurious signals.

[0018] DDS spurious characteristic analysis:

[0019] The spurious signal of the DDS output is related to the system clock and output signal frequency of the DDS. 杂散 =m*f 时钟 +n*f 输出，Where m and n are integers. The spurious relationship shows that the frequency difference between the output signal and the system clock's frequency division is very small and cannot be filtered out. Therefore, while ensuring spurious control, the DDS output signal cannot be near the system clock's frequency division. For example, if the clock is 3.5 GHz, the output signal cannot be near 500 MHz. If it is 499.9 MHz, the spurious frequency is: 3500 - 6 * 499.9 = 500.6 MHz. The frequency difference between this signal and 499.9 MHz is too small to be filtered out by the subsequent segmented filtering.

[0020] In addition, the power of the output signal spurious is related to f 杂散 =m*f 时钟 +n*f 输出 The values ​​of m and n are related. When the sum of m and n is greater than 7, the spurious signal is better than 60dBc and can be ignored. (The conclusion comes from the actual measurement of the AD9914 output signal)

[0021] The present invention switches the DDS clock to avoid the output frequency point being near the clock frequency division annex, and then uses the filter group behind the DDS to perform segmented filtering, ultimately obtaining a signal with a relatively wide bandwidth, thereby reducing the difficulty of mixing and segmented filtering of the subsequent frequency hopping source 1.

[0022] Example: Switching between DDS clock frequencies of 3.5GHz and 3.2GHz to achieve an output frequency of 230-630MHz. The specific correspondence is:

[0023]

[0024]

[0025] According to the corresponding relationship in the above table, according to f 杂散 =m*f 时钟 +n*f 输出 By calculating the output spurious signals, it can be concluded that the frequency difference between the output spurious signals and the output signal is large, and they can be filtered out by the subsequent filter group to ensure the spurious indicators.

Claims

1. A system for optimizing DDS output signal spurious by switching the system clock, characterized by: The method comprises a PLL, a DDS, and a filter group in sequence, wherein at least two mixers connected to a frequency hopping source are connected in sequence after the filter group, and a filter group is provided between the mixers connected to the frequency hopping source; A switch filter is added after the DDS, and the reference phase-locked loop is switched into two or more frequency points. The DDS clock is switched by switching the frequency of the phase-locked loop. The DDS clock frequency switches between 3.5GHz and 3.2GHz to achieve an output frequency of 230-630MHz. Then filter the signal in sections.

Images