Memory detection method and device, storage medium and electronic equipment

Abstract

The application relates to the technical field of hardware detection, in particular to a memory detection method and device, a storage medium and an electronic equipment, which comprises the following steps: loading a pre-compiled memory detection program; setting test parameters of the memory detection program; acquiring a maximum address range of a system environment currently where the memory detection program is located, and converting the maximum address range into a format taking bytes and megabytes as units; dynamically applying for a memory space, and performing address alignment with the maximum address range; performing memory address data bus cycle detection and memory address data sensitivity detection, and outputting a final memory detection result. The pre-compiled detection program can quickly detect abnormal addresses in the memory, realizes the function of quickly and effectively detecting the stability of DDR memory in a VxWorks operating system, and reduces the complexity and development cost of the system.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of hardware detection, in particular to a memory detection method and device, a storage medium and an electronic device. BACKGROUND

[0002] In the control based on the VxWorks operating system, all data needs to pass through memory interaction, and all programs run in the memory. The DDR memory is an important part of the operating system. With the increasing work frequency of the master control, the frequency of the matched memory is also increasing, and the signal integrity requirement of the memory on the system is also increasing. After the DDR is configured, the DDR needs to be tested first to ensure the stability of the DDR. Otherwise, if the DDR has a problem, it may cause data errors or even system crashes.

[0003] The existing memory detection method tests the stability of the DDR memory through aging and boiling. The aging and boiling method consumes a lot of time and has low detection efficiency. SUMMARY

[0004] To solve the problem that the existing memory detection method consumes a lot of time and has low detection efficiency, the present application provides a memory detection method and device, a storage medium and an electronic device.

[0005] In a first aspect, the present application provides a memory detection method, which comprises:

[0006] loading a pre-compiled memory detection program;

[0007] setting test parameters of the memory detection program;

[0008] obtaining a maximum address range of a system environment where the memory detection program currently locates, and converting the maximum address range into a format with byte and megabyte as units;

[0009] dynamically applying memory space and performing address alignment with the maximum address range;

[0010] performing memory address data bus cycle detection to obtain a first memory detection result;

[0011] performing memory address data sensitivity detection to obtain a second memory detection result;

[0012] combining the first memory detection result and the second memory detection result to output a final memory detection result.

[0013] In some embodiments, the loading of the pre-compiled memory detection program comprises:

[0014] The pre-compiled memory detection program is loaded through a command parser shell.

[0015] In some embodiments, the test parameters of the memory detection program include:

[0016] The test memory size parameter and the test loop number parameter of the memory detection program are set.

[0017] In some embodiments, after the test parameters of the memory detection program are set, the method further includes:

[0018] It is judged whether the system environment in which the memory detection program is currently located supports a POSIX interface;

[0019] If the system environment does not support the POSIX interface, a prompt that the test is unsuccessful is output;

[0020] If the system environment supports the POSIX interface, a step of acquiring the maximum address range of the system environment in which the memory detection program is currently located is performed.

[0021] In some embodiments, the memory address data bus loop detection is performed to obtain a first memory detection result, including:

[0022] Random data is written in the memory space, and the random data is written in the storage locations in the memory space in the order of sequentially adding 1;

[0023] The random data is read out, and it is compared whether the written data and the read data are the same;

[0024] The memory space is written and the data is read in the same way, and the comparison is repeated 16 times in a loop;

[0025] If the written data and the read data are not the same within the period, it is determined that data abnormality occurs, and an abnormal address value is returned;

[0026] From the next position of the abnormal address value in the memory space, the memory space is written and the data is read in the same way, and the comparison is repeated 16 times in a loop;

[0027] If the written data and the read data are not the same within the period, it is determined that data abnormality occurs, and an abnormal address value is returned;

[0028] All abnormal address values are finally obtained as the first memory detection result.

[0029] In some embodiments, the memory address data sensitivity detection is performed to obtain a second memory detection result, including:

[0030] Two buffer units are set in the memory space, and the same random value is written at the same time;

[0031] XOR comparing the random values after writing in the two buffer units, if the two random values are not equal, returning the address information of the two buffer units;

[0032] repeatedly reading and writing the addresses of the two buffer units, and comparing the read and write data to determine whether there is data loss;

[0033] if there is data loss, determining that the addresses of the two buffer units are abnormal, and taking the addresses of the two buffer units as the second memory detection result.

[0034] In some embodiments, the two buffer units are input buffer units and output buffer units.

[0035] In a second aspect, a memory detection device is provided, and the device comprises:

[0036] a loading unit configured to load a pre-compiled memory detection program;

[0037] a setting unit configured to set test parameters of the memory detection program;

[0038] an obtaining unit configured to obtain a maximum address range of a system environment in which the memory detection program is currently located, and convert the maximum address range into a format in bytes and megabytes;

[0039] an applying unit configured to dynamically apply memory space and perform address alignment with the maximum address range;

[0040] a first detection unit configured to perform memory address data bus cycle detection to obtain a first memory detection result;

[0041] a second detection unit configured to perform memory address data sensitivity detection to obtain a second memory detection result;

[0042] an output unit configured to output a final memory detection result after merging the first memory detection result and the second memory detection result.

[0043] In a third aspect, a storage medium is provided, and the storage medium stores a computer program that can be executed by one or more processors and can be used to implement the memory detection method of the first aspect.

[0044] In a fourth aspect, an electronic device is provided, and the electronic device comprises a memory and a processor, the memory stores a computer program, and the memory and the processor are communicatively connected, and the computer program is executed by the processor to execute the memory detection method of the first aspect.

[0045] The application provides a memory detection method, device, storage medium and electronic equipment, which comprises the following steps: loading a pre-compiled memory detection program; setting test parameters of the memory detection program; obtaining a maximum address range of a system environment in which the memory detection program is currently located, and converting the maximum address range into a format with byte and megabyte as units; dynamically applying for a memory space, and performing address alignment with the maximum address range; performing memory address data bus cycle detection to obtain a first memory detection result; performing memory address data sensitivity detection to obtain a second memory detection result; and combining the first memory detection result and the second memory detection result to output a final memory detection result. The pre-compiled detection program can quickly detect abnormal addresses in the memory, realizes the function of quickly and effectively detecting the stability of the DDR memory in the VxWorks operating system, and reduces the complexity and development cost of the system. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.

[0047] Figure 1 A flowchart of a memory detection method provided by the embodiment of the present application;

[0048] Figure 2 An interface diagram of a command parser shell loading a DDR memory detection program provided by the embodiment of the present application;

[0049] Figure 3 A diagram of a final memory detection result provided by the embodiment of the present application;

[0050] Figure 4 A structural diagram of a memory detection device provided by the embodiment of the present application;

[0051] Figure 5 A connection block diagram of an electronic equipment provided by the embodiment of the present application. DETAILED DESCRIPTION

[0052] The embodiments of the present application will be described in detail below with reference to the drawings and embodiments, so that how the present application applies technical means to solve technical problems and achieves corresponding technical effects can be fully understood and implemented. The embodiments of the present application and each feature in the embodiments can be combined with each other without conflict, and the formed technical solutions are all within the protection scope of the present application.

[0053] As known from the background art, the existing memory detection method is to test the stability of the DDR memory by aging and boiling the machine, which consumes a large amount of time and has low detection efficiency.

[0054] Therefore, the present application provides a memory detection method, device, storage medium and electronic equipment, which solves the technical problem of consuming a large amount of time and having low detection efficiency in related art by aging and boiling the machine to detect the memory.

[0055] Example One

[0056] Figure 1 A flowchart of a memory detection method provided by an embodiment of the present application is shown in FIG. 1, which includes the following steps. Figure 1

[0057] S101, loading a pre-compiled memory detection program.

[0058] In some embodiments, the loading of the pre-compiled memory detection program includes:

[0059] loading the pre-compiled memory detection program through a command parser shell.

[0060] It should be noted that the command parser shell is a software that can provide an operation interface for users and can load and run a pre-compiled program.

[0061] As shown in FIG. 2, it is an interface diagram of loading a DDR memory detection program for a command parser shell. Figure 2

[0062] It should be noted that the memory detection method of the present application is mainly applied to a VxWorks operating system.

[0063] S102, setting test parameters of the memory detection program.

[0064] In some embodiments, the test parameters of the memory detection program include:

[0065] setting test memory size parameters and test cycle number parameters of the memory detection program.

[0066] Specifically, the test memory size parameters and test cycle number parameters can be set according to the memory size and performance of the test target and other factors.

[0067] In some embodiments, after the setting of the test parameters of the memory detection program, the method further includes:

[0068] judging whether a system environment in which the memory detection program is currently located supports a POSIX interface; ​​

[0069] If the system environment does not support the POSIX interface, output a prompt that the test is unsuccessful;

[0070] If the system environment supports the POSIX interface, perform a step of acquiring a maximum address range of a system environment in which the memory detection program currently resides.

[0071] It should be noted that, in order to ensure that the detection program is correctly and successfully run, it is necessary to determine that the memory detection program is executed under the condition of supporting the POSIX interface.

[0072] S103, acquiring a maximum address range of a system environment in which the memory detection program currently resides, and converting the maximum address range into a format in bytes and megabytes.

[0073] S104, dynamically applying for memory space, and performing address alignment with the maximum address range.

[0074] It should be noted that, in order to ensure that the memory detection program is correctly run in the system, it is necessary to first acquire the maximum address range of the system for reference of the dynamically applied memory space, and on the other hand, the address format is changed into a unified format, which can facilitate the alignment of the address of the applied memory space with the address in the maximum address range.

[0075] S105, performing memory address data bus cycle detection to obtain a first memory detection result.

[0076] In some embodiments, the memory address data bus cycle detection is performed to obtain the first memory detection result, including:

[0077] writing random data in the applied memory space, and writing the random data in the memory space in a storage location in a sequence of sequentially adding 1;

[0078] reading out the random data, and comparing whether the written data and the read data are the same;

[0079] writing the memory space and reading the data in the same way, and repeating the comparison for 16 times;

[0080] if the written data and the read data are not the same within the period, it is determined that data abnormality occurs, and an abnormal address value is returned;

[0081] starting from a next position of the abnormal address value in the memory space, writing the memory space and reading the data in the same way, and repeating the comparison for 16 times;

[0082] if the written data and the read data are not the same within the period, it is determined that data abnormality occurs, and an abnormal address value is returned;

[0083] Finally, all abnormal address values are obtained as the first memory detection result.

[0084] It should be noted that the existence of data abnormality can be verified by sequentially repeating comparison and checking, and all abnormal address values in the memory are obtained as one of the memory checking results.

[0085] S106, memory address data sensitivity detection is performed to obtain a second memory detection result.

[0086] In some embodiments, the memory address data sensitivity detection is performed to obtain the second memory detection result, including:

[0087] Two buffer units are set in the memory space of the application, and the same random value is written into the two buffer units at the same time;

[0088] After the random value written into the two buffer units is compared by XOR, if the two random values are not equal, the address information of the two buffer units is returned;

[0089] The addresses of the two buffer units are repeatedly read and written, and the read and written data are compared to determine whether there is data loss;

[0090] If there is data loss, it is determined that the addresses of the two buffer units are abnormal, and the addresses of the two buffer units are taken as the second memory detection result.

[0091] It should be noted that in order to test the data sensitivity of the DDR memory caused by some effective input data, if there is data that cannot be normally processed, the random values written into the two buffer units will not be equal during the test process, specifically, the difference between the two random values is a non-zero value, indicating that there is a data loss condition, at this time, the corresponding address information of the data loss is obtained, and then the random number read and write of the address are repeatedly performed in a short time to further verify whether there is really an abnormal situation of data loss, if so, it is considered that the address is abnormal, and it is taken as one of the memory checking results.

[0092] S107, the first memory detection result and the second memory detection result are combined to output a final memory detection result.

[0093] Specifically, in another embodiment of the application, the final memory detection result output is as shown in Figure 3 .

[0094] As can be seen from the above, the detection result of the DDR memory indicates that there is no abnormality, value = 0 = 0 * 0.

[0095] In some embodiments, the two buffer units are input buffer units and output buffer units.

[0096] In summary, the embodiment of the application provides a memory detection device, comprising: loading a pre-compiled memory detection program; setting test parameters of the memory detection program; acquiring a maximum address range of a system environment in which the memory detection program currently locates, and converting the maximum address range into a format in byte and mega; dynamically applying for a memory space, and performing address alignment with the maximum address range; performing memory address data bus cycle detection to obtain a first memory detection result; performing memory address data sensitivity detection to obtain a second memory detection result; merging the first memory detection result and the second memory detection result, and outputting a final memory detection result. The pre-compiled detection program can quickly detect abnormal addresses in the memory, realize the function of quickly and effectively detecting the stability of the DDR memory in the VxWorks operating system, and reduce the complexity and development cost of the system.

[0097] Embodiment two

[0098] Based on the memory detection method disclosed in the embodiment of the application, Figure 4 The memory detection device applying the memory detection method is specifically disclosed.

[0099] As Figure 4 shown, the embodiment of the application discloses a memory detection device, which comprises:

[0100] The loading unit 401 is used for loading a pre-compiled memory detection program.

[0101] The setting unit 402 is used for setting test parameters of the memory detection program.

[0102] The acquiring unit 403 is used for acquiring a maximum address range of a system environment in which the memory detection program currently locates, and converting the maximum address range into a format in byte and mega.

[0103] The applying unit 404 is used for dynamically applying for a memory space, and performing address alignment with the maximum address range.

[0104] The first detection unit 405 is used for performing memory address data bus cycle detection to obtain a first memory detection result.

[0105] The second detection unit 406 is used for performing memory address data sensitivity detection to obtain a second memory detection result.

[0106] The output unit 407 is used for merging the first memory detection result and the second memory detection result, and outputting a final memory detection result.

[0107] The specific working processes of the loading unit 401, the setting unit 402, the obtaining unit 403, the applying unit 404, the first detecting unit 405, the second detecting unit 406 and the output unit 407 in the memory detection device disclosed in the above embodiments of the application can refer to the corresponding contents in the memory detection method disclosed in the above embodiments of the application, and will not be repeated here.

[0108] In summary, the embodiments of the application provide a memory detection device, which comprises the following steps: loading a pre-compiled memory detection program; setting test parameters of the memory detection program; obtaining a maximum address range of a system environment in which the memory detection program currently locates, and converting the maximum address range into a format in byte and mega; dynamically applying a memory space, and performing address alignment with the maximum address range; performing memory address data bus cycle detection to obtain a first memory detection result; performing memory address data sensitivity detection to obtain a second memory detection result; and merging the first memory detection result and the second memory detection result to output a final memory detection result. The pre-compiled detection program can quickly detect abnormal addresses in the memory, realizes the function of quickly and effectively detecting the stability of the DDR memory in the VxWorks operating system, and reduces the complexity and development cost of the system.

[0109] Embodiment three

[0110] The embodiment also provides a computer readable storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory (for example, an SD or DX memory, etc.), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, an optical disk, a server, an App application mall, etc., which stores a computer program. The computer program can realize the method steps of the embodiment one when executed by a processor. The embodiment will not be repeated here.

[0111] Embodiment four

[0112] Figure 5 A connection block diagram of an electronic device 500 provided by the embodiments of the application is shown in FIG. 5, which can include a processor 501, a memory 502, a multimedia component 503, an input / output (I / O) interface 504, and a communication component 505. Figure 5

[0113] ​The processor 501 is configured to execute all or part of the memory detection method in Embodiment One. The memory 502 is configured to store various types of data, which can include, for example, instructions of any application program or method in the electronic device, and application-related data.

[0114] The processor 501 can be an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a Programmable Logic Device (PLD), a Field Programmable Gate Array (FPGA), a controller, a microcontroller, a microprocessor, or other electronic components, which are configured to execute the memory detection method in Embodiment One.

[0115] The memory 502 can be implemented by any type of volatile or non-volatile storage devices or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0116] The multimedia component 503 can include a screen, which can be a touch screen, and an audio component for outputting and / or inputting audio signals. For example, the audio component can include a microphone for receiving external audio signals. The received audio signals can be further stored in the memory or transmitted through the communication component. The audio component also includes at least one speaker for outputting audio signals.

[0117] The I / O interface 504 provides an interface between the processor 501 and other interface modules, which can be a keyboard, a mouse, a button, or the like. The buttons can be virtual buttons or physical buttons.

[0118] The communication component 505 is configured to perform wired or wireless communication between the electronic device 500 and other devices. The wireless communication, for example, Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G or 4G, or a combination of one or more of them, and thus the corresponding communication component 505 can include a Wi-Fi module, a Bluetooth module, an NFC module.

[0119] To sum up, the application provides a memory detection method, device, storage medium and electronic device. The method comprises: loading a pre-compiled memory detection program; setting test parameters of the memory detection program; obtaining a maximum address range of a system environment in which the memory detection program is currently located, and converting the maximum address range into a format in byte and mega; dynamically applying a memory space, and performing address alignment with the maximum address range; performing memory address data bus cycle detection to obtain a first memory detection result; performing memory address data sensitivity detection to obtain a second memory detection result; merging the first memory detection result and the second memory detection result, and outputting a final memory detection result. The pre-compiled detection program can quickly detect abnormal addresses in the memory, realize the function of quickly and effectively detecting the stability of the DDR memory in the VxWorks operating system, and reduce the complexity and development cost of the system.

[0120] In the several embodiments provided in the present application, it should be understood that the disclosed method can also be implemented by other ways. The embodiment of the method described above is only illustrative.

[0121] It should be noted that, in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusions, such that processes, methods, articles, or devices including a series of elements not only include those elements, but also include other elements not explicitly listed, or further include elements inherent in such processes, methods, articles, or devices. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article, or device including the element.

[0122] Although the embodiments disclosed in the present application are as above, the above content is only the embodiment adopted for the convenience of understanding the present application, and is not intended to limit the present application. Any person skilled in the art without departing from the spirit and scope of the present application can make any modification and change in the form and details of the implementation, but the patent protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A memory detection method, characterized by, The method comprises: loading a pre-compiled memory detection program; setting test parameters of the memory detection program; obtaining a maximum address range of a system environment in which the memory detection program currently exists, and converting the maximum address range into a format in bytes and megabytes; dynamically applying memory space with reference to the maximum address range, and performing address alignment with the maximum address range; performing memory address data bus cycle detection to obtain a first memory detection result; performing memory address data sensitivity detection to obtain a second memory detection result; combining the first memory detection result and the second memory detection result to output a final memory detection result; wherein the memory address data sensitivity detection to obtain the second memory detection result comprises: setting two buffer units in the applied memory space, and writing the same random value into the two buffer units at the same time; performing XOR comparison on the random values written into the two buffer units, and if the two random values are not equal, returning address information of the two buffer units; repeatedly reading and writing data in the address of the two buffer units, and comparing the read and written data to determine whether there is data loss; if there is data loss, determining that the address of the two buffer units is abnormal, and taking the address of the two buffer units as the second memory detection result.

2. The method of claim 1, wherein, The loading of the pre-compiled memory detection program comprises: loading the pre-compiled memory detection program through a command parser shell.

3. The method of claim 1, wherein, The test parameters of the memory detection program comprise: setting test memory size parameters and test cycle number parameters of the memory detection program.

4. The method of claim 1, wherein, After setting the test parameters of the memory detection program, the method further comprises: judging whether the system environment in which the memory detection program currently exists supports a POSIX interface; if the system environment does not support the POSIX interface, outputting a prompt that the test is unsuccessful; if the system environment supports the POSIX interface, performing the step of obtaining the maximum address range of the system environment in which the memory detection program currently exists.

5. The method of claim 1, wherein, The memory address data bus cycle detection to obtain the first memory detection result comprises: writing random data into the applied memory space, and writing the random data into storage locations in the memory space in the order of sequentially adding 1; reading out the random data, and comparing whether the written data and the read data are the same; writing data into the memory space and reading data in the same way, and repeatedly comparing 16 times; if the written data and the read data are not the same within a period of time, determining that data abnormality occurs, and returning an abnormal address value; starting from a next position of the abnormal address value in the memory space, writing data into the memory space and reading data in the same way, and repeatedly comparing 16 times; if the written data and the read data are not the same within a period of time, determining that data abnormality occurs, and returning an abnormal address value; finally obtaining all abnormal address values as the first memory detection result.

6. The method of claim 1, wherein, The two buffer units are an input buffer unit and an output buffer unit.

7. A memory detection device, comprising: The device comprises: a loading unit configured to load a pre-compiled memory detection program; a setting unit configured to set test parameters of the memory detection program; An acquisition unit is configured to acquire a maximum address range of a system environment in which the memory detection program is currently located, and convert the maximum address range into a format in bytes and megabytes; An application unit is configured to dynamically apply for a memory space with reference to the maximum address range, and perform address alignment with the maximum address range; A first detection unit is configured to perform memory address data bus cycle detection, and obtain a first memory detection result; A second detection unit is configured to perform memory address data sensitivity detection, and obtain a second memory detection result; An output unit is configured to output a final memory detection result after merging the first memory detection result and the second memory detection result. The memory address data sensitivity detection includes: Two buffer units are set in the applied memory space, and the same random value is written into the two buffer units; XOR comparison is performed on the random values written into the two buffer units, and if the two random values are not equal, address information of the two buffer units is returned; Repeated reading and writing are performed on the addresses of the two buffer units, and comparison is performed on the read and written data to determine whether there is data loss; If there is data loss, it is determined that the addresses of the two buffer units are abnormal, and the addresses of the two buffer units are taken as the second memory detection result.

8. A storage medium, characterized by The computer program stored in the storage medium can be executed by one or more processors, and can be used to implement the memory detection method according to any one of claims 1-6.

9. An electronic device, comprising: The computer program stored in the storage medium can be executed by one or more processors, and can be used to implement the memory detection method according to any one of claims 1-6.

Images