Partial block erase operations in memory devices

Abstract

Systems and methods for performing partial block erase operations are described. An example memory device includes a memory array comprising a plurality of memory cells electrically coupled to a plurality of word lines, and a controller coupled to the memory array, the controller to perform operations comprising: identifying, in a memory device, a block comprising a plurality of memory cells; estimating, in the block, a number of pages having a predefined programmed state; determining, based on the number of pages having the predefined programmed state, an erase verify voltage to be applied to the block; causing an erase operation to be performed with respect to the block; and causing an erase verify operation to be performed with respect to the block using the erase verify voltage.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to implementing partial block erase operations in memory devices. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof.

[0004] Figure 1 The description includes an example computing system containing a memory subsystem operating according to aspects of this disclosure.

[0005] Figure 2 A block diagram of a memory device for communicating with a memory subsystem controller operating according to aspects of this disclosure.

[0006] Figure 3A A set of memory cells arranged in a memory device operating according to aspects of this disclosure is illustrated schematically.

[0007] Figure 3B The source-drain current of two memory cells in a memory device operating according to aspects of this disclosure is schematically illustrated to depend on the control gate voltage.

[0008] Figure 3C An example distribution of threshold control gate voltage of a memory cell in a memory device operating according to aspects of this disclosure is illustrated schematically.

[0009] Figure 4 An example memory array operating according to aspects of this disclosure is illustrated schematically.

[0010] Figure 5 This illustration schematically depicts a partial block erasure operation performed according to aspects of this disclosure.

[0011] Figure 6 An example threshold voltage distribution in a block of a memory device operating according to aspects of this disclosure is illustrated schematically.

[0012] Figure 7 Several blocks of a memory device operating according to aspects of this disclosure are illustrated schematically.

[0013] Figure 8 This is a flowchart of an example method for performing a partial block erasure operation according to an embodiment of the present disclosure.

[0014] Figure 9 A block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0015] This disclosure pertains to implementing partial block erase operations in a memory device. One or more memory devices may be part of a memory subsystem, which may be a storage device, a memory module, or a mixture of a storage device and a memory module. The following is combined with... Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem containing one or more memory devices, such as those for storing data. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0016] The memory subsystem may include high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may contain two or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a set of physical blocks. In some embodiments, each block may contain multiple sub-blocks. Each plane carries a matrix of memory cells formed on a silicon wafer and connected by conductors called word lines and bit lines, such that word lines connect multiple memory cells forming rows of the memory cell matrix, while bit lines connect multiple memory cells forming columns of the memory cell matrix.

[0017] Depending on the cell type, each memory cell can store one or more bits of binary information and has various logical states related to the number of bits being stored. Logical states can be represented by binary values ​​(e.g., "0" and "1") or combinations of such values. A set of memory cells called a memory page can be programmed in a single operation, for example, by selecting consecutive bit lines together.

[0018] Memory cell programming operations, which can be performed in response to a write command received from the host, may involve sequentially applying programming voltage pulses to selected word lines coupled to the target memory page. Conversely, the memory cell should be erased before a new value can be stored in the previously programmed memory cell. Erasing operations are typically performed on a block-by-block basis, thereby erasing all memory pages of the block.

[0019] In some implementations, the erase operation includes applying a preprogrammed voltage to a selected word line addressing a page of the block to be erased, followed by applying one or more erase voltage pulses to the word line addressing the page of the block, and finally followed by an erase verification operation that verifies that the memory cell does not have a threshold voltage distribution that would at least partially extend beyond a predefined erase verification voltage threshold.

[0020] In various applications, the number of programmed pages within a block to be erased can vary, which may result in a fully programmed block in which all pages are programmed, or a partially programmed block in which at least some pages are not programmed (i.e., in an erased state). Unless these differences in the number of programmed pages in the block to be erased are taken into account when performing the erase operation, these differences may result in inaccurate erase verification operations.

[0021] In some implementations, a higher pre-programming voltage may be used for partial programming of the block in an attempt to equalize the threshold voltage distribution across all pages of the block. However, a higher pre-programming voltage may accelerate the degradation of memory cells within the block.

[0022] The methods and systems disclosed herein avoid the additional risk of memory degradation that may result from applying higher preprogramming voltages. According to aspects of this disclosure, the preprogramming voltage remains constant for all blocks, regardless of their fully or partially programmed state, while the erase verification voltage threshold is varied to account for the various fully or partially programmed states of the block being erased. In some embodiments, the erase verification voltage threshold may be adjusted to reflect the ratio of programmed / erased pages (or the ratio of programmed pages to the total number of pages) in the block being erased. In illustrative examples, the memory controller may estimate the number of programmed pages in the block (e.g., by reading memory pages addressable by a predefined set of word lines) and may adjust the base value of the erase verification voltage to reflect the estimated number of programmed pages in the block. In some embodiments, an additive adjustment reflecting the estimated number of programmed pages (or the ratio of the number of programmed pages to the total number of pages) may be applied to the base value of the erase verification voltage, as described in more detail below.

[0023] Therefore, the advantages of this method include, but are not limited to, avoiding memory degradation that may result from memory erasure operations by maintaining the same preprogrammed voltage for all blocks being erased, while taking into account possible differences in their fully or partially programmed states by modifying the erase verification voltage threshold.

[0024] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0025] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0026] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or networked business device), or such a computing device containing memory and processing power.

[0027] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, and magnetic connections.

[0028] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0029] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0030] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0031] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0033] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0034] The memory subsystem controller 115 (“Controller 115”) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0035] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0036] In some embodiments, local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0037] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0038] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0039] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller for media management within the same memory device package (e.g., memory subsystem controller 115). An example of a managed memory device is a managed NAND (MNAND) device.

[0040] In one embodiment, memory subsystem 110 includes memory interface component 113. Memory interface component 113 handles interactions between memory subsystem controller 115 and memory devices (e.g., memory device 130) of memory subsystem 110. For example, memory interface component 113 may send memory access commands corresponding to requests received from host system 120 to memory device 130, such as programming commands, read commands, or other commands. Additionally, memory interface component 113 may receive data from memory device 130, such as data retrieved in response to confirmation of a read command or successful execution of a programming command. For example, memory subsystem controller 115 may include processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein.

[0041] In one embodiment, memory device 130 includes a programming manager 134 configured to perform a corresponding memory access operation in response to receiving a memory access command from memory interface 113. In some embodiments, local media controller 135 includes at least a portion of programming manager 134 and is configured to perform the functionality described herein. In some embodiments, programming manager 134 is implemented on memory device 130 using firmware, hardware components, or a combination thereof. In one embodiment, programming manager 134 receives a request from, for example, a requester of memory interface 113, for programming data into a memory array of memory device 130. The memory array may comprise an array of memory cells formed at the intersection of word lines and bit lines. In one embodiment, for example, memory cells are grouped into blocks, which may be further divided into sub-blocks, wherein a given word line is shared across several sub-blocks. In one embodiment, each sub-block corresponds to a separate plane in the memory array. A group of memory cells associated with a word line within a sub-block is referred to as a physical page.

[0042] In various embodiments, the memory array may comprise multiple portions, including, for example, portions where sub-blocks are configured as SLC memory and / or portions where sub-blocks are configured as multilevel cell (MLC) memory (i.e., containing memory cells capable of storing two or more bits of information per cell, such as TLC cells). The voltage levels of the memory cells in a TLC memory form a set of eight programming distributions, representing eight different combinations of the three bits stored in each memory cell. Depending on how they are configured, each physical page in a sub-block may contain multiple page types. For example, a physical page formed by a single level cell (SLC) has a single page type called a lower logical page (LP). MLC physical page types may include LP and upper logical pages (UP), TLC physical page types are LP, UP, and additional logical pages (XP), and QLC physical page types are LP, UP, XP, and top logical page (TP). For example, a physical page formed by memory cells of the QLC memory type may have a total of four logical pages, wherein each logical page may store data different from the data stored in other logical pages associated with the physical page.

[0043] In an illustrative example, programming manager 134 may receive data to be programmed into memory device 130. In response, programming manager 134 may perform a programming operation to program each memory cell to the desired programming level. In another illustrative example, programming manager 134 may sequentially receive several data items to be programmed into the same location of memory device 130.

[0044] In an illustrative example, a memory cell programming operation that can be performed in response to a write command received from a host may involve sequentially applying programming voltage pulses to selected word lines. In some embodiments, the programming pulse voltage may sequentially ramp up from an initial voltage value (e.g., 0V) to a final voltage value (e.g., V). MAX Unselected word lines can be biased at a specific voltage (e.g., pass voltage) less than the programming voltage during programming operations. After each programming pulse, or after several programming pulses, a programming verification operation can be performed to determine whether the threshold voltage of one or more memory cells has increased to the desired programming level.

[0045] Memory cells should be erased before new values ​​can be stored in previously programmed memory cells. Erasure operations are typically performed on a block-by-block basis, thus erasing all memory pages of a block.

[0046] In some implementations, the erase operation includes applying a pre-programmed voltage to selected word lines addressing pages of the block to be erased in an attempt to equalize the charge held by the memory cells of the block. Following the pre-programming phase, one or more erase voltage pulses may be applied to the word lines addressing pages of the block to bring the charge of all memory cells in the block to the erase voltage level. The memory cell state is verified by a subsequent erase verification operation that determines whether any memory cell has a threshold voltage distribution that at least partially extends beyond a predefined erase verification voltage threshold.

[0047] As mentioned above, the number of programmed pages within a block to be erased can vary across different applications, potentially resulting in a fully programmed block where all pages are programmed, or a partially programmed block where at least some pages are not programmed (i.e., in an erased state). To avoid memory degradation, the preprogramming voltage remains constant for all blocks, regardless of their fully or partially programmed state, while the various fully or partially programmed states of the block being erased are reflected by varying erase verification voltage thresholds.

[0048] In some embodiments, the erase verification voltage threshold may be adjusted to reflect the ratio of programmed / erased pages (or the ratio of programmed pages to the total number of pages) in the block being erased. In an illustrative example, the memory controller may estimate the number of programmed pages in the block (e.g., by reading memory pages addressable by a predefined set of word lines) and may adjust the base value of the erase verification voltage to reflect the estimated number of programmed pages in the block. In some embodiments, an additive adjustment reflecting the estimated number of programmed pages (or the ratio of the number of programmed pages to the total number of pages) may be applied to the base value of the erase verification voltage, as described in more detail below.

[0049] Figure 2 A first device in the form of a presenting memory device 130 according to an embodiment and a presenting memory subsystem (e.g., Figure 1 A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0050] Memory device 130 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 2 (Not shown in the text) can be programmed to one of at least two target data states.

[0051] Row decoding circuitry 108 and column decoding circuitry 111 are provided to decode the address signal. The address signal is received and decoded to access the memory cell array 104. The memory device 130 also includes an input / output (I / O) control circuitry 112 for managing inputs of commands, addresses, and data to the memory device 130, as well as outputs of data and status information from the memory device 130. An address register 114 communicates with the I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 111 to latch the address signal before decoding. A command register 124 communicates with the I / O control circuitry 112 and local media controller 135 to latch incoming commands.

[0052] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 104 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on memory cell array 104. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 111 to control them in response to addresses. In one embodiment, the local media controller 135 includes a programming manager 134 capable of performing memory programming operations relative to memory device 130, as described herein.

[0053] The local media controller 135 also communicates with cache register 118. Cache register 118 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 118 to data register 121 for transfer to memory cell array 104; then, new data can be latched from I / O control circuitry 112 into cache register 118. During read operations, data can be transferred from cache register 118 to I / O control circuitry 112 for output to memory subsystem controller 115; then, new data can be transferred from data register 121 to cache register 118. Cache register 118 and / or data register 121 may form a page buffer (e.g., a portion thereof) of memory device 130. The page buffer may further include sensing devices ( Figure 2 (Not shown) to sense the data status of the memory cells in the memory cell array 104, for example, by sensing the status of the data lines connected to the memory cells. The status register 122 can communicate with the I / O control circuitry system 112 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0054] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 132. For example, control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received further via control link 132. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 136, and outputs data to memory subsystem controller 115 via I / O bus 136.

[0055] For example, commands can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 136 and then written to command register 124. Addresses can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 136 and then written to address register 114. Data can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 118. The data can then be written to data register 121 for programming memory cell array 104.

[0056] In this embodiment, cache register 118 may be omitted, and data may be written directly to data register 121. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0057] In some implementations, additional circuitry and signals may be provided, and Figure 2 The memory device 130 has been simplified. It should be understood that the reference... Figure 2 The functionality of the various block components described need not be divided into different components or component parts of the integrated circuit device. For example, a single component or component part of the integrated circuit device may be adapted to perform... Figure 2 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 2 The functionality of a single block component. Additionally, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations of I / O pins (or other I / O node structures) or other numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0058] One or more memory devices of the memory subsystem 100 may be represented, for example, by a NAND memory device utilizing an array of transistors built on a semiconductor chip. Figure 3AThe diagram schematically illustrates that the memory cells of a memory device can be transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), having source (S) electrodes and drain (D) electrodes to allow current to flow through them. The source and drain electrodes can be connected to conductive bit lines (BLs), which can be shared by multiple memory cells. The memory device can comprise an array or memory cells connected to multiple word lines (WLs) and multiple bit lines (BLs), as shown by... Figure 4 This is an illustrative illustration. The memory device may further include circuitry for selectively coupling WL and BL to voltage sources that provide control gate and source-drain signals, which, for clarity and simplicity, are shown below. Figure 4 Omit.

[0059] Refer again Figure 3A Memory cells 302 and 304 can be connected to the same bit line N and two different conductive word lines M and M+1, respectively. The memory cells may further have a control gate (CG) electrode to receive a voltage signal V. CG This controls the amount of current flowing between the source and drain electrodes. More specifically, a threshold control gate voltage V can exist. T (Also referred to in this paper as the “threshold voltage” or simply the “threshold”), such that for V CG <V T The source-drain current may be low, but once the control gate voltage exceeds the threshold voltage, i.e., V0... CG >V T This can be roughly increased. The transistors of the same memory device can be characterized by the distribution of their threshold voltages, i.e., P(V... T )=dW / dV T Therefore, dW = P(V) T )dV T This indicates that the threshold voltage of any given transistor is in the range [V]. T V T +dV T The possibilities within. For example, Figure 3B A schematic illustration of the source-drain current I. SD The dependence of the control gate voltage on two memory cells with different threshold control gate voltages, such as memory cell 302 (solid line) and memory cell 304 (dashed line).

[0060] To make the memory cells non-volatile, the cells can be further equipped with conductive islands-charge storage nodes, which can be transmitted through an insulating layer (in... Figure 3A The area depicted as a dashed line in the diagram is electrically isolated from the control gate, source electrode, and drain electrode. It responds to an appropriately selected positive (relative to the source potential) control gate voltage V. CGThe charge storage node can receive a charge Q, which can be permanently stored even after the memory cell is powered on, thus stopping the source-drain current. The charge Q can affect the threshold voltage P (V). T The distribution of Q). Generally speaking, it is similar to the distribution of uncharged charge storage nodes P(V). T In contrast, the presence of charge Q shifts the threshold voltage distribution toward higher voltages. This occurs because a stronger positive gate voltage V may be required. CG To overcome the negative potential of the charge Q at the charge storage node. If the charge sequence Q can be selectively... k (where 1≤k≤2) N If any charge Q is programmed (and later detected during a read operation) into a memory cell, the memory cell can act as an N-bit storage unit. k Preferably, they are chosen to be sufficiently different from each other such that any two adjacent voltage distributions P(V) are such that... T Q k ) and P(V T Q k+1 ) They do not overlap but are separated by valley margins, thus 2 N Distribution P(V) T Q k ) and 2 N -1 valley margin interval.

[0061] Figure 3C The distribution of threshold-controlled gate voltages of a memory cell capable of storing three bits of data by programming the memory cell to at least eight charge states is illustrated, the at least eight charge states being different from the charge storage node of the cell. Figure 3C The exhibition is presented in 2 3 -1 = 7 valley margins (VM) k 2 of the separated three-level cell (TLC) N = Threshold voltage P(V) for 8 different charge states T Q k The distribution of ) is thus programmed as the k-th charge state (i.e., having a charge Q deposited on its charge storage node). k The memory cell can store a specific combination of N bits (e.g., for N = 4, 0110). This charge state Q k Valley margin VM can be detected during readout operations. k Internal control gate voltage V CG Sufficient to open the cell to source-drain current while maintaining the previous valley margin VM k-1 The control gate voltage within is insufficient to open the cell to the source-drain current.

[0062] Memory devices can be classified according to the number of bits stored in each cell of the memory. For example, a single-level cell (SLC) memory has cells that can each store one bit of data (N=1). A multi-level cell (MLC) memory has cells that can each store up to two bits of data (N=2), a three-level cell (TLC) memory has cells that can each store up to three bits of data (N=3), and a four-level cell (QLC) memory has cells that can each store up to four bits of data (N=4). Generally, the operations described herein are applicable to memory devices with N bits (where N>1) of memory cells.

[0063] For example, a TLC can be in at least eight charge states Q. k One of them (where the first state is the uncharged state Q1 = 0), its threshold voltage distribution is determined by the valley margin VM k Separating the data allows for reading data stored in memory cells. For example, if the read threshold voltage is determined to be 2 during a read operation... N If a memory cell is within a specific valley margin of -1 valley margin, then it can be determined that the memory cell is in a 2-valley range. N A specific charge state among the possible charge states. By identifying the right valley margin of the cell, the values ​​of all its N bits can be determined. The identifier of the valley margin (e.g., its coordinates, such as the position of the center and width) can be stored in the read level threshold register of the memory subsystem controller 115.

[0064] As mentioned above, the memory subsystem controller 115 can program the state of the memory cells, and then read the memory cells by setting the read threshold voltage V. T This state is read by comparing it with one or more read level thresholds. The read operation can be performed after the memory cell has been placed into one of its charged states by a previous programming operation, which may consist of one or more programming passes. Each programming pass applies an appropriate programming voltage to a given word line to place the appropriate charge on the charge storage node of the memory cell connected to the word line.

[0065] Programming operations involve a sequence of programming voltage pulses applied to the selected (target) word line (i.e., the word line electrically coupled to the target memory cell). See again... Figure 3A The source (S) and drain (D) electrodes of a memory cell can be connected to a conductive bit line shared by multiple memory cells. Programming operations apply a sequence of programming voltage pulses to the control gate (CG) via the corresponding word line (WL). Each programming voltage pulse induces an electric field that pulls electrons to the charge storage node. After each programming pulse is applied to the selected word line, a verification operation can be performed by reading the memory cell to determine the threshold voltage V of the memory cell.T Has the desired value (voltage verification level) been reached? If the threshold voltage V of the memory cell... T Once the verification voltage associated with the desired state has been reached, the bit line connected to the memory cell can be biased at the programming disable voltage, thereby preventing further programming of the memory cell coupled to the bit line, i.e., to prevent the threshold voltage V of the memory cell from being exceeded. T In response to subsequent programming pulses applied to the selected word line, the bit is shifted further upward.

[0066] Figure 5 A partial block erase operation performed according to aspects of this disclosure is illustrated schematically. The erase operation is typically performed on a block-by-block basis, thereby erasing all memory pages of the block. (As shown by...) Figure 5 To illustrate, the erase operation 500 involves applying a read voltage level 510 to one or more selected word lines of the corresponding page of the addressed block. A preprogramming voltage 520 is then applied to the selected word lines to attempt to equalize the charge held by the memory cells of the block. To avoid memory degradation, the preprogramming voltage 520 remains constant for all blocks, regardless of whether they are fully or partially programmed.

[0067] Following the pre-programming phase 520, one or more erase voltage pulses 530 are applied to the selected word lines to bring the charge of all memory cells in the block to the erase voltage level. The resulting memory cell state is verified by a subsequent erase verification operation 540, which determines whether any memory cell has a threshold voltage distribution that extends at least partially beyond a predefined erase verification voltage threshold.

[0068] If the erase verification operation fails (thus indicating that some memory cells in the block have a threshold voltage distribution that extends at least partially beyond the predefined erase verification voltage threshold), another erase operation 530 may be performed relative to the block, possibly with one or more modified parameters (e.g., higher voltage level and / or longer pulse).

[0069] As mentioned above, the number of programmed pages within a block to be erased can vary across different applications. This could result in a fully programmed block where all pages are programmed, or a partially programmed block where at least some pages are not programmed (i.e., in an erased state), thus producing something similar to... Figure 6 The example threshold voltage distribution of 600. For example, through... Figure 6To illustrate, for a given programming block, some memory cells may exhibit a threshold voltage distribution 610A that is tightly grouped together, while other memory cells may exhibit a threshold voltage distribution 610B that can be shifted by various offsets relative to the threshold voltage distribution 610A. Although the preprogramming voltage 520 applied to the corresponding word line may cause at least some of the memory cells to shift their voltage distribution toward the group of threshold voltage distributions 610A, at least some memory cells may still exhibit threshold voltage distribution 610B because, as mentioned above, the same preprogramming voltage 520 is applied to all word lines, regardless of the programmed / erase state of the page addressable by said word line.

[0070] As mentioned above, this can be achieved by adjusting... Figure 5 The erase verification operation 540 utilizes erase verification voltage thresholds 620A-620B to mitigate differences between threshold voltage distributions. In some embodiments, the erase verification voltage thresholds may be adjusted to reflect the ratio of programmed / erroneous pages (or the ratio of programmed pages to the total number of pages) in the block being erased.

[0071] In some implementations, the memory controller can estimate the number of programmable pages in a block by reading memory pages addressable by a predefined set of word lines, such as by... Figure 7 To illustrate, it shows blocks 710A-710N with different numbers of programmed pages: block 710A has approximately 30% programmed pages, block 710B has approximately 50% programmed pages, block 710D has approximately 90% programmed pages, and block 710M has 100% programmed pages.

[0072] In an illustrative example, the memory controller can sequentially iterate through a predefined set of word lines 720A-720N, reading pages addressable by each word line in the set until the first erased page is found. Assuming word lines 720A-720N are selected in equal intervals, the ratio of programmed pages to total pages in a block can be estimated to be approximately equal to the ratio of the number of sequences of the first word lines (in the set of word lines 720A-720N) that produce erased pages to the total number of word lines in the set of word lines 720A-720N, i.e., R = WL. E / N WL Where R indicates the ratio of programmed pages to total pages, WL E Indicates the sequence number of the first word line that generated the erased page (in the set of word lines 720A-720N), and N WL Indicates the total number of word lines in the selected word line set.

[0073] Therefore, the memory controller can adjust the base value of the erase verification voltage to reflect the estimated ratio of programmed pages to total pages. In some embodiments, an additive adjustment reflecting the estimated number of programmed pages (or the ratio of the number of programmed pages to the total number of pages) can be applied to the base value of the erase verification voltage.

[0074] The additive adjustment can be zero for a fully programmed block and can be expressed as a linear function of the estimated ratio of the programmed pages of the block to the total pages. In the illustrative example, it equals V1. <V2<V3<…<V N The negative additive adjustment can be applied to the corresponding ratio of the programmed pages of the block to the total pages, such that R1>R2>R3>R4>…>R N .

[0075] Figure 8 This is a flowchart illustrating an example method for performing a partial block erasure operation according to an embodiment of the present disclosure. Method 800 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 800 is performed by… Figure 1 The memory subsystem controller 115 and / or local media controller 135 perform the operations. Although shown in a specific sequence or order, the order of operations may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated operations may be performed in different orders, and some operations may be performed in parallel. In addition, one or more operations may be omitted in various embodiments. Therefore, not all operations are required in every embodiment.

[0076] At operation 810, the controller implementing the method identifies the block to be erased in the memory device. In an illustrative example, the block identifier can be supplied via an erase command received by the controller.

[0077] At operation 820, the controller estimates the number of pages with predefined programming states (e.g., erased or programmed states) in the block.

[0078] At operation 830, the controller determines the erase verification voltage to be applied to the block based on the number of pages with predefined programming states. In an illustrative example, the controller may sequentially iterate through a predefined set of word lines, reading pages addressable by each word line in the set until the first erased page is found. The ratio of the number of programmed pages to the total number of pages in the block can then be estimated as approximately equal to the ratio of the sequence number of word lines that produced the first erased page to the total number of word lines in the predefined set of word lines. Therefore, an additive adjustment reflecting the estimated ratio of the number of programmed pages to the total number of pages (or the number of programmed pages or the number of erased pages) can be applied to the base value of the erase verification voltage. The additive adjustment may be zero for a fully programmed block and can be expressed as a linear function of the estimated ratio of the number of programmed pages to the total number of pages, as described in more detail above.

[0079] At operation 840, the controller causes an erase operation to be performed relative to the block. Performing an erase operation may involve applying one or more erase voltage pulses to the word lines of the pages addressing the block, as described in more detail above.

[0080] At operation 850, the controller causes an erase verification operation to be performed relative to the block using an erase verification voltage. The erase verification operation verifies that the memory cell does not have a threshold voltage distribution that extends at least partially beyond the predefined erase verification voltage, as described in more detail above herein.

[0081] Figure 9 This describes an example machine of computer system 900, wherein an executable instruction set is provided to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 900 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of the programming manager 134). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0082] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered to include any collection of machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any or more of the methods discussed herein.

[0083] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 918, which communicate with each other via a bus 930.

[0084] Processing device 902 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 902 is configured to execute instructions 926 for performing the operations and steps discussed herein. Computer system 900 may further include a network interface device 908 for communication via network 920.

[0085] The data storage system 918 may include a machine-readable storage medium 924 (also referred to as a computer-readable medium, such as a non-transitory computer-readable medium) storing one or more instruction sets 926 or software embodying any one or more of the methods or functions described herein. The instructions 926 may also reside wholly or at least partially in main memory 904 and / or processing device 902 during execution by computer system 900, which also constitute machine-readable storage media. The machine-readable storage medium 924, the data storage system 918, and / or main memory 904 may correspond to... Figure 1 The memory subsystem 110.

[0086] In one embodiment, instruction 926 includes instructions for implementing the corresponding Figure 1The programming manager 134 provides functional instructions. Although the machine-readable storage medium 924 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0087] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithms are described and represented as a way for those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. An algorithm here and generally is considered a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0088] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system, or other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0089] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0090] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices for performing the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0091] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0092] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device, comprising: a memory array comprising a plurality of memory cells electrically coupled to a plurality of word lines; and a controller coupled to the memory array, the controller performing operations comprising: identifying, in a memory device, a block comprising a plurality of memory cells; estimating, in the block, a number of pages having a predefined programmed state; determining, based on the number of pages having the predefined programmed state, an erase verify voltage to be applied to the block; applying an additive voltage adjustment to the erase verify voltage, wherein the additive voltage adjustment is a linear function of the number of pages having the predefined programmed state; causing an erase operation to be performed with respect to the block; and causing an erase verify operation to be performed with respect to the block using the erase verify voltage.

2. The memory device of claim 1, wherein the predefined programmed state is at least one of: a programmed state or an erased state.

3. The memory device of claim 1, wherein estimating the number of pages having the predefined programmed state further comprises: identifying, among a plurality of test pages addressable by a plurality of preselected word lines, a first erased page; and estimating the number of pages having the predefined programmed state as a linear function of a number of sequences of word lines addressing first identified erased pages.

4. The memory device of claim 1, wherein estimating the number of pages having the predefined programmed state further comprises: identifying a first programmed page of the block; and estimating the number of pages having the predefined programmed state as a linear function of a number of first identified programmed pages.

5. The memory device of claim 1, wherein the operations further comprise: in response to detecting a failure of the erase verify operation, modifying at least one erase operation parameter; and causing a second erase operation to be performed using the modified erase operation parameter.

6. The memory device of claim 1, wherein causing the erase operation to be performed further comprises: causing a pre-programming voltage to be applied to the plurality of memory cells of the block; and causing an erase pulse to be applied to the plurality of memory cells of the block.

7. A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a controller managing a memory array comprising a plurality of memory cells, cause the controller to perform operations comprising: identifying, in a memory device, a block comprising a plurality of memory cells; estimating, in the block, a number of pages having a predefined programmed state; determining, based on the number of pages having the predefined programmed state, an erase verify voltage to be applied to the block; applying an additive voltage adjustment to a base value of the erase verify voltage, wherein the additive voltage adjustment is a linear function of the number of pages having the predefined programmed state; causing an erase operation to be performed with respect to the block; and causing an erase verify operation to be performed with respect to the block using the erase verify voltage.

8. The computer-readable non-transitory storage medium of claim 7, wherein the predefined programmed state is at least one of: a programmed state or an erased state.

9. The computer-readable non-transitory storage medium of claim 7, wherein estimating the number of pages having the predefined programmed state further comprises: identifying a first erased page among a plurality of test pages addressable by a plurality of pre-selected word lines; and estimating the number of pages having the predefined programmed state as a linear function of a number of sequences of word lines addressing first identified erased pages.

10. The computer-readable non-transitory storage medium of claim 7, wherein estimating the number of pages having the predefined programmed state further comprises: identifying a first programmed page of the block; and estimating the number of pages having the predefined programmed state as a linear function of a number of first identified programmed pages.

11. The computer-readable non-transitory storage medium of claim 7, wherein the operations further comprise: in response to detecting a failure of the erase verify operation, modifying at least one erase operation parameter; and causing a second erase operation to be performed using the modified erase operation parameter.

12. The computer-readable non-transitory storage medium of claim 7, wherein causing the erase operation to be performed further comprises: causing a pre-programming voltage to be applied to the plurality of memory cells of the block; and causing an erase pulse to be applied to the plurality of memory cells of the block.

13. A method comprising: identifying, in a memory device, a block comprising a plurality of memory cells; estimating, in the block, a number of pages having a predefined programmed state; determining, based on the number of pages having the predefined programmed state, an erase verify voltage to be applied to the block; applying an additive voltage adjustment to a base value of the erase verify voltage, wherein the additive voltage adjustment is a linear function of the number of pages having the predefined programmed state; causing, by a processing device of a controller managing the memory device, an erase operation to be performed with respect to the block; and causing an erase verify operation to be performed with respect to the block using the erase verify voltage.

14. The method of claim 13, wherein the predefined programmed state is at least one of: a programmed state or an erased state.

15. The method of claim 13, wherein estimating the number of pages having the predefined programmed state further comprises: identifying a first erased page among a plurality of test pages addressable by a plurality of pre-selected word lines; and estimating the number of pages having the predefined programmed state as a linear function of a number of sequences of word lines addressing first identified erased pages.

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