Method for manufacturing a flash memory device

Abstract

The present invention provides a method for manufacturing a flash memory device. A floating gate layer, an interlayer dielectric layer, a control gate layer, and a hard mask layer with an opening are sequentially formed on a substrate, and a first sidewall is formed on the sidewall of the opening; a recess is formed in the control gate layer exposed by the opening through a first etching process, so that a gap appears between the bottom of the first sidewall near the opening and the control gate layer; the control gate layer exposed by the opening and the interlayer dielectric layer thereunder are removed through a second etching process; a second sidewall filling the gap is formed; the floating gate layer exposed by the opening is removed, and a word line is formed in the opening; the hard mask layer and the control gate layer, the interlayer dielectric layer, and the floating gate layer thereunder are removed to form a control gate and a floating gate. In the present invention, a recess is formed in the control gate layer exposed by the opening, making the top angle of the subsequently formed control gate smooth, improving the thickness uniformity of the second sidewall, thereby avoiding isolation failure between the control gate and the word line and ensuring the normal operation of the flash memory device.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing technology, and particularly to a method for manufacturing a flash memory device. Background Art

[0002] With the development of technology, the application of data storage media has shifted from some traditional non-volatile memories to flash memory type memories. High-capacity solid-state storage devices with flash memory as the main storage medium have become one of the mainstream solutions for data storage today.

[0003] Refer to Figure 1 , a split-gate flash memory device generally includes a word line (WL) 10 and a floating gate (FG) 20 and a control gate (CG) 30 vertically stacked on both sides of the word line 10. Among them, a first spacer 40 is formed on the control gate 30, and a second spacer 41 is formed between the control gate 30 and the word line 10. Refer to Figure 2 and Figure 3 , after forming the first spacer 40, due to the relatively thick control gate layer 31 (for example, ), side etching phenomenon will occur during the process of etching the control gate layer 31 exposed by the first spacer 41, resulting in an inwardly concave bow-shaped profile on the side wall of the etched control gate layer 31, and making the top angle A of the control gate layer 31 relatively sharp. Refer to Figure 4 , wet cleaning and other processes performed after the etching process of the control gate layer 31 will etch back the first spacer 40, exposing the top angle A of the control gate layer 31. Continuing to refer to Figure 1 , since the top angle A of the control gate layer 31 is exposed and relatively sharp, therefore, the thickness of the second spacer 41 finally formed on the surface of the first spacer 40 and the side wall of the control gate 30 is uneven, and the part near the top angle A is the thinnest. In severe cases, the second spacer 41 may even break at the top angle A, thus unable to effectively isolate the subsequently formed control gate and word line, and causing the split-gate flash memory device to fail.

[0004] In view of this, a method is needed to reduce or avoid the uneven thickness or breakage of the second spacer caused by the overly sharp top angle of the control gate, thereby avoiding the isolation failure between the control gate and the word line and ensuring the normal operation of the flash memory device. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for manufacturing a flash memory device, which reduces or avoids the uneven thickness or breakage of the second spacer caused by the overly sharp top angle of the control gate, thereby avoiding the isolation failure between the control gate and the word line and ensuring the normal operation of the flash memory device.

[0006] To achieve the above object, the present invention provides a method for manufacturing a flash memory device, comprising:

[0007] Providing a substrate, on which a floating gate layer, an interlayer dielectric layer, a control gate layer, and a hard mask layer are sequentially formed. An opening exposing the control gate layer is formed on the hard mask layer, and a first sidewall is formed on the sidewall of the opening.

[0008] Performing a first etching process to etch a part of the control gate layer exposed by the opening, and forming a depression in the control gate layer, so that a gap appears between the bottom of the first sidewall close to the opening and the control gate layer.

[0009] Performing a second etching process to remove the control gate layer exposed by the opening and the interlayer dielectric layer under the opening, so that the opening exposes the floating gate layer.

[0010] Forming a second sidewall filling the gap, and the second sidewall covers the surface of the first sidewall and the sidewall of the control gate layer.

[0011] Removing the floating gate layer exposed by the opening, so that the opening exposes the substrate, and forming a word line in the opening; and,

[0012] Removing the hard mask layer and the control gate layer, interlayer dielectric layer, and floating gate layer under the hard mask layer to form a control gate and a floating gate.

[0013] Optionally, after performing the second etching process, the top corner of the control gate layer close to the opening is rounded.

[0014] Optionally, the width of the depression is greater than or equal to the bottom width of the opening, and the width of the depression is less than the sum of the bottom width of the opening and the width of the first sidewall.

[0015] Optionally, the first etching process is an isotropic dry etching process.

[0016] Optionally, in the first etching process, the etching selectivity between the first sidewall and the control gate layer is 1:5 to 1:10.

[0017] Optionally, the second etching process is an anisotropic dry etching process.

[0018] Optionally, after removing the floating gate layer exposed by the opening and before forming a word line in the opening, it further comprises:

[0019] Forming a third sidewall on the sidewall and bottom of the opening.

[0020] Optionally, a gate oxide layer is further formed between the substrate and the floating gate layer.

[0021] Optionally, the interlayer dielectric layer is an ONO stacked structure formed by stacking a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

[0022] Optionally, the manufacturing method of the flash memory device is used to manufacture a split-gate flash memory device.

[0023] In summary, the present invention provides a manufacturing method of a flash memory device, which sequentially forms a floating gate layer, an interlayer dielectric layer, a control gate layer, and a hard mask layer with an opening on a substrate, and forms a first sidewall on the sidewall of the opening; performs a first etching process to form a depression in the control gate layer exposed by the opening, so that a gap appears between the bottom of the first sidewall close to the opening and the control gate layer; performs a second etching process to remove the control gate layer exposed by the opening and the interlayer dielectric layer thereunder; forms a second sidewall to fill the gap; removes the floating gate layer exposed by the opening, and forms a word line in the opening; and removes the hard mask layer and the control gate layer, interlayer dielectric layer, and floating gate layer thereunder to form a control gate and a floating gate. By forming a depression in the control gate layer exposed by the opening through the first etching process, the present invention makes the top angle of the subsequently formed control gate smooth, reduces or avoids uneven thickness or breakage of the second sidewall caused by the too sharp top angle of the control gate, thereby avoiding isolation failure between the control gate and the word line and ensuring the normal operation of the flash memory device. Description of the Drawings

[0024] Figure 1 is a schematic structural diagram of a flash memory device;

[0025] Figures 2 to 4 is a schematic structural diagram corresponding to some steps in the manufacturing process of a flash memory device;

[0026] Figure 5 is a flowchart of the manufacturing method of the flash memory device provided by an embodiment of the present invention;

[0027] Figures 6 to 11 is a schematic structural diagram corresponding to each step in the manufacturing method of the flash memory device provided by an embodiment of the present invention;

[0028] Among them, the reference numerals are as follows:

[0029] 10 - word line; 20 - floating gate; 30 - control gate; 31 - control gate layer; 40 - first sidewall; 41 - second sidewall;

[0030] 100 - substrate; 101 - gate oxide layer; 110 - floating gate layer; 111 - floating gate; 120 - interlayer dielectric layer; 130 - control gate layer; 131 - depression; 132 - control gate; 140 - hard mask layer; 150 - opening; 151 - first sidewall; 152 - second sidewall; 153 - third sidewall; 160 - word line;

[0031] A - apex angle; B - gap. Detailed implementation manners

[0032] The following will describe in more detail the detailed implementation manners of the present invention with reference to the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the attached drawings are all in very simplified forms and use non - precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0033] Figure 5 It is a flowchart of a manufacturing method of a flash memory device provided in an embodiment of the present invention. Refer to Figure 5 The manufacturing method of the flash memory device includes:

[0034] Step S01: Provide a substrate, on which a floating gate layer, an inter - layer dielectric layer, a control gate layer, and a hard mask layer are sequentially formed. An opening exposing the control gate layer is formed on the hard mask layer, and a first sidewall is formed on the sidewall of the opening.

[0035] Step S02: Perform a first etching process to etch a part of the control gate layer exposed by the opening, and form a depression in the control gate layer, so that a gap appears between the bottom of the first sidewall close to the opening and the control gate layer.

[0036] Step S03: Perform a second etching process to remove the control gate layer exposed by the opening and the inter - layer dielectric layer below the opening, so that the opening exposes the floating gate layer.

[0037] Step S04: Form a second sidewall filling the gap, and the second sidewall covers the surface of the first sidewall and the sidewall of the control gate layer.

[0038] Step S05: Remove the floating gate layer exposed by the opening, so that the opening exposes the substrate, and form a word line in the opening; and,

[0039] Step S06: Remove the hard mask layer and the control gate layer, inter - layer dielectric layer, and floating gate layer below the hard mask layer to form a control gate and a floating gate.

[0040] Figures 6 to 11 It is a schematic diagram of the structure corresponding to each step in the manufacturing method of a flash memory device provided in an embodiment of the present invention. The following will describe in detail the manufacturing method of the flash memory device described in this embodiment with reference to Figures 6 to 11 the following.

[0041] First, refer to Figure 6, perform step S01, provide a substrate 100, on which a floating gate layer 110, an interlayer dielectric layer 120, a control gate layer 130, and a hard mask layer 140 are sequentially formed. An opening 150 exposing the control gate layer 130 is formed on the hard mask layer 140, and a first sidewall 151 is formed on the sidewall of the opening 150.

[0042] Exemplarily, the process of forming the first sidewall 151 includes: sequentially depositing and forming a floating gate layer 110, an interlayer dielectric layer 120, a control gate layer 130, and a hard mask layer 140 on the substrate 100; performing photolithography and etching processes on the hard mask layer 140 to pattern the hard mask layer 140, thereby forming the opening 150; depositing a first sidewall material layer (not shown in the figure) in the opening 150, and the first sidewall material layer extends to cover the surfaces of the hard mask layer 140 on both sides of the opening 150; etching the first sidewall material layer to form the first sidewall 151 on the sidewall of the opening 150.

[0043] In this embodiment, a gate oxide layer 101 is further formed between the substrate 100 and the floating gate layer 110. Optionally, the interlayer dielectric layer 120 is an ONO stacked structure formed by stacking a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. In this embodiment, the first sidewall 151 and the gate oxide layer 101 are silicon oxide layers, the floating gate layer 110 and the control gate layer 130 are polysilicon layers, and the hard mask layer 140 is a silicon nitride layer. In other embodiments of the present invention, the specific materials of the above-mentioned each film layer can be adjusted according to actual needs, and the present invention does not limit this.

[0044] Next, refer to Figure 7 , perform step S02, perform a first etching process to etch a part of the control gate layer 130 exposed by the opening 150, and form a recess 131 in the control gate layer 130, so that there is a gap B between the bottom of the first sidewall 151 close to the opening 150 and the control gate layer 130.

[0045] In this embodiment, the first etching process is an isotropic dry etching process, and in the first etching process, the etching selectivity between the first sidewall 151 and the control gate layer 130 is 1:5 to 1:10. It should be noted that the width of the part where the recess 131 extends into the bottom of the first sidewall 151 (i.e., the gap B) is very small and will not affect the normal use of the finally formed flash memory device. Optionally, the width X of the recess 131 is greater than or equal to the bottom width W1 of the opening 150, and the width X of the recess 131 is less than the sum of the bottom width W1 of the opening 151 and the width W2 of the first sidewall 151.

[0046] Subsequently, refer toFigure 8 Step S03 is then performed to carry out a second etching process to remove the control gate layer 130 exposed by the opening 150 and the interlayer dielectric layer 120 under the opening 150, so that the floating gate layer 110 is exposed by the opening 150. Optionally, the second etching process is an anisotropic dry etching process.

[0047] It should be noted that since a depression 131 is formed in the control gate layer 130 in step S02, and there is a gap B between the bottom of the first sidewall 151 near the opening 150 and the control gate layer 130, therefore, after the second etching process, the top corner of the control gate layer 130 near the opening 150 (i.e., the top corner below the gap B) is rounded.

[0048] Next, referring to Figure 9 Step S04 is performed to form a second sidewall 152 filling the gap B, and the second sidewall 152 covers the surface of the first sidewall 151 and the sidewalls of the control gate layer 130. In this embodiment, the forming method of the second sidewall 152 is the same as that of the first sidewall, and will not be elaborated here. Optionally, the second sidewall 152 is a stacked structure formed by stacking a silicon oxide layer and a silicon nitride layer.

[0049] Subsequently, referring to Figure 10 Step S05 is performed to remove the floating gate layer 110 exposed by the opening 150, so that the opening 150 exposes the substrate 110, and a word line 160 is formed in the opening 150.

[0050] Exemplarily, the forming process of the word line 160 includes: etching the floating gate layer 110 exposed by the opening 150 and the gate oxide layer 101 under the opening 150 with the hard mask layer 140, the first sidewall 151 and the second sidewall 152 as a mask k, so that the opening 150 exposes the substrate 110; forming a third sidewall 153 on the sidewalls and bottom of the opening 150 (the forming process of the third sidewall 153 is the same as that of the first sidewall 151 and will not be elaborated here); depositing and forming a word line material layer (not shown in the figure) in the opening 150 and on the hard mask layer 140 on both sides of the opening 150, and performing a planarization process and an etching process on the word line material layer to form a word line 160 in the opening 150. Optionally, a chemical mechanical polishing process is used for the planarization process. Optionally, the third sidewall 153 is a silicon oxide layer. The word line 160 is a polysilicon layer.

[0051] Next, referring to Figure 11, step S06 is executed to remove the hard mask layer 140, the control gate layer 130, the interlayer dielectric layer 120, and the floating gate layer 110 under the hard mask layer 140 to form a control gate 132 and a floating gate 111. Optionally, the hard mask layer 140, the control gate layer 130, the interlayer dielectric layer 120, the floating gate layer 110, and the gate oxide layer 101 under the hard mask layer 140 are removed by a dry etching process.

[0052] In this embodiment, the manufacturing method of the flash memory device is used to manufacture a split-gate flash memory device. In other embodiments of the present invention, the manufacturing method of the flash memory device can also be used to manufacture other types of flash memory devices or other semiconductor devices with the same structure. The present invention does not limit this.

[0053] Comparison Figure 1 and Figure 11 It can be seen that in the existing flash memory device, the top angle A of the control gate 30 is relatively sharp, and the part of the second sidewall 41 near the top angle A is relatively thin, with a risk of breakage, which affects the isolation effect between the control gate 30 and the word line 10; while in the flash memory device formed in this embodiment, the top angle (i.e., the top angle under the gap B) of the control gate 132 is relatively smooth, and the part of the second sidewall 152 near the top angle is relatively thick, and it is not easy to break, thus avoiding the isolation failure between the control gate 132 and the word line 160 and ensuring the normal operation of the flash memory device.

[0054] In summary, the present invention provides a manufacturing method of a flash memory device, which sequentially forms a floating gate layer, an interlayer dielectric layer, a control gate layer, and a hard mask layer with an opening on a substrate, and forms a first sidewall on the sidewall of the opening; performs a first etching process to form a depression in the control gate layer exposed in the opening, so that a gap appears between the bottom of the first sidewall near the opening and the control gate layer; performs a second etching process to remove the control gate layer exposed in the opening and the interlayer dielectric layer below it; forms a second sidewall filling the gap; removes the floating gate layer exposed in the opening, and forms a word line in the opening; and removes the hard mask layer, the control gate layer, the interlayer dielectric layer, and the floating gate layer below it to form a control gate and a floating gate. The present invention forms a depression in the control gate layer exposed in the opening through the first etching process, making the top angle of the subsequently formed control gate smooth, reducing or avoiding the uneven thickness or breakage of the second sidewall caused by the too sharp top angle of the control gate, thereby avoiding the isolation failure between the control gate and the word line and ensuring the normal operation of the flash memory device.

[0055] The above are only the preferred embodiments of the present invention and do not impose any limitation on the present invention. Any person skilled in the art, within the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed by the present invention, which are all within the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A manufacturing method of a flash memory device, characterized in that, Including: Providing a substrate, on which a floating gate layer, an interlayer dielectric layer, a control gate layer, and a hard mask layer are sequentially formed. An opening exposing the control gate layer is formed on the hard mask layer, and a first sidewall is formed on the sidewall of the opening. Performing a first etching process to etch a part of the control gate layer exposed by the opening, and forming a depression in the control gate layer, so that a gap appears between the bottom of the first sidewall close to the opening and the control gate layer. Performing a second etching process to remove the control gate layer exposed by the opening and the interlayer dielectric layer under the opening, so that the opening exposes the floating gate layer. Forming a second sidewall filling the gap, and the second sidewall covers the surface of the first sidewall and the sidewall of the control gate layer. Removing the floating gate layer exposed by the opening, so that the opening exposes the substrate, and forming a word line in the opening. And, Removing the hard mask layer, the control gate layer, the interlayer dielectric layer, and the floating gate layer under the hard mask layer to form a control gate and a floating gate.

2. The manufacturing method of the flash memory device according to claim 1, characterized in that, After performing the second etching process, the top corner of the control gate layer close to the opening is rounded.

3. The manufacturing method of the flash memory device according to claim 1, characterized in that, The width of the depression is greater than or equal to the bottom width of the opening, and the width of the depression is less than the sum of the bottom width of the opening and the width of the first sidewall.

4. The manufacturing method of the flash memory device according to claim 1, characterized in that, The first etching process is an isotropic dry etching process.

5. The manufacturing method of the flash memory device according to claim 1 or 4, characterized in that, In the first etching process, the etching selectivity between the first sidewall and the control gate layer is 1:5 to 1:

10.

6. The manufacturing method of the flash memory device according to claim 1, characterized in that, The second etching process is an anisotropic dry etching process.

7. The manufacturing method of the flash memory device according to claim 1, characterized in that, After removing the floating gate layer exposed by the opening and before forming a word line in the opening, further including: Forming a third sidewall on the sidewall and the bottom of the opening.

8. The manufacturing method of the flash memory device according to claim 1, characterized in that, A gate oxide layer is further formed between the substrate and the floating gate layer.

9. The manufacturing method of the flash memory device according to claim 1, characterized in that, The interlayer dielectric layer is an ONO stacked structure formed by stacking a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

10. The manufacturing method of the flash memory device according to claim 1, characterized in that, The manufacturing method of the flash memory device is used to manufacture a split-gate flash memory device.

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