Array substrate and display panel

Abstract

The application provides an array substrate and a display panel. The array substrate comprises a substrate and a plurality of pixel driving circuits. Each pixel driving circuit comprises a data line, a driving power line, a driving transistor, a switching transistor arranged on one side of the driving transistor close to the data line, a source electrode of the switching transistor connected with a source electrode of the driving transistor, the source electrode of the switching transistor electrically connected with the data line, a compensation transistor, the compensation transistor arranged on one side of the driving power line away from the data line, a drain electrode of the compensation transistor connected with a drain electrode of the driving transistor, a source electrode of the compensation transistor electrically connected with a gate electrode of the driving transistor, and at least one patterned dummy electrode arranged between the source electrode of the switching transistor and the source electrode of the compensation transistor. The array substrate and the display panel optimize the stacked structure of the pixel driving circuit, introduce the dummy electrode, and improve the display abnormality caused by signal crosstalk.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display devices, in particular to an array substrate and a display panel. BACKGROUND

[0002] With the development of display technology, high pixel density display solutions are sought after. The higher the pixel density of a display screen, the smaller the area of the pixel driving circuit. The pixel driving circuit is composed of multiple transistors and capacitors. The more devices, the higher the wiring pattern density, and the more serious the signal crosstalk between the wirings, thereby affecting the quality of the product. SUMMARY

[0003] The technical problem solved by the present application is the signal crosstalk problem between high-density wiring patterns.

[0004] To solve the above technical problem, one technical solution adopted by the present application is: an array substrate, comprising a substrate, and a plurality of pixel driving circuits arranged on the substrate, the pixel driving circuit comprising:

[0005] a data line arranged along a first direction;

[0006] a driving power line arranged along the first direction;

[0007] a driving transistor;

[0008] a switching transistor arranged on one side of the driving transistor close to the data line, and the drain part of the switching transistor is connected with the source part of the driving transistor; the source part of the switching transistor is electrically connected with the data line;

[0009] a compensation transistor arranged on one side of the driving power line away from the data line; the drain part of the compensation transistor is connected with the drain part of the driving transistor; the source part of the compensation transistor is electrically connected with the gate of the driving transistor; wherein at least one patterned virtual electrode is arranged between the source part of the switching transistor and the source part of the compensation transistor.

[0010] Preferably, the driving transistor and the compensation transistor are located on one side of the driving power line away from the data line; the switching transistor is located on one side of the driving power line close to the data line; along the first direction, the switching transistor and the compensation transistor are located on the same side of the driving transistor; so that the driving transistor, the compensation transistor and the switching transistor are reasonably arranged on the substrate, which is beneficial to the miniaturization of the pixel driving circuit.

[0011] Preferably, the gate of the switch transistor and the gate of the compensation transistor are electrically connected with a second scan line respectively, so that the second scan line is multiplexed as the gate of the switch transistor and the compensation transistor, the gate wiring is simplified, and the miniaturization of the pixel driving circuit is improved; the second scan line is arranged between the compensation transistor and the driving transistor, so as to reduce the wiring distance of the compensation transistor and the driving transistor from the second scan line.

[0012] Preferably, the compensation transistor is a double-gate transistor, so as to improve the convenience and independence of the control of the compensation transistor.

[0013] More preferably, the dummy electrode is electrically connected with the driving power supply line, so as to shield the crosstalk of the voltage jump of the data line to the gate potential of the driving transistor;

[0014] Preferably, the dummy electrode and the driving power supply line at least partially overlap on the substrate, so as to reduce the wiring distance between the driving power supply line and the dummy electrode; the dummy electrode is electrically connected with the driving power supply line through a first via, so as to reduce the connection distance of the dummy electrode and the driving power supply line.

[0015] More preferably, the material of the dummy electrode is the same as the material of the semiconductor layer of the driving transistor, without increasing the complexity of the mask process.

[0016] Preferably, the dummy electrode is a heavily doped semiconductor, so as to improve the shielding property of the dummy electrode to signal crosstalk.

[0017] More preferably, the source part of the switch transistor is electrically connected with the data line through a second via, so as to reduce the connection distance of the source part of the switch transistor and the data line; the source part of the compensation transistor is connected with a connection line through a third via, and the connection line is electrically connected with the gate of the driving transistor, so as to realize the electrical connection of the source part of the compensation transistor and the gate of the driving transistor, and reduce the connection distance of the two;

[0018] The dummy electrode has a first end part and a second end part along a first direction; the first end part is located on the side of the second via and the third via away from the driving transistor along the first direction, and the second end part is located on the side of the second via and the third via close to the driving transistor along the first direction; so as to further reduce the parasitic capacitance between the source part of the switch transistor and the source part of the compensation transistor, and shield the crosstalk of the voltage jump of the data line to the gate potential of the driving transistor;

[0019] Preferably, along the first direction, the first end part is located at the side of the source part of the switch transistor and the source part of the compensation transistor away from the driving transistor, and the second end part is located at the side of the source part of the switch transistor and the source part of the compensation transistor close to the driving transistor, so as to further reduce the parasitic capacitance between the source part of the switch transistor and the source part of the compensation transistor.

[0020] More preferably, the pixel driving circuit further comprises a conductive layer electrically connected with the driving power supply line; the conductive layer covers at least part of the dummy electrode, part of the source part of the compensation transistor and part of the drain part of the compensation transistor; the conductive layer is electrically connected with the driving power supply line, so as to stabilize the potential of the compensation transistor.

[0021] Preferably, the pixel driving circuit further comprises a storage capacitor comprising a first capacitor electrode and a second capacitor electrode arranged oppositely; the storage capacitor and the driving transistor at least partially overlap in the orthographic projection on the substrate; the gate of the driving transistor serves as the second capacitor electrode; the first capacitor electrode partially overlaps with the driving power supply line in the orthographic projection on the substrate, and the first capacitor electrode is electrically connected with the driving power supply line; so as to improve the miniaturization of the pixel driving circuit.

[0022] Preferably, an opening is formed in the first capacitor electrode, and the gate of the driving transistor is electrically connected with the source part of the compensation transistor through the opening; so as to reduce the wiring distance between the gate of the driving transistor and the source part of the compensation transistor, and reduce the area of the pixel driving circuit.

[0023] Preferably, the pixel driving circuit further comprises an initialization transistor; the source part of the initialization transistor is electrically connected with a reference voltage signal line; the drain part of the initialization transistor is connected with the gate of the driving transistor and the source part of the compensation transistor; and the gate of the initialization transistor is electrically connected with a first scan line, so as to multiplex the first scan line as the gate of the initialization transistor, simplify the gate wiring and improve the miniaturization of the pixel driving circuit.

[0024] Preferably, the initialization transistor is a double-gate transistor, so as to improve the convenience and independence of the control of the initialization transistor.

[0025] Preferably, the pixel driving circuit further comprises a first light-emitting control transistor and a second light-emitting control transistor; the first light-emitting control transistor and the second light-emitting control transistor are arranged on the side of the driving transistor away from the compensation transistor in the first direction, and the first light-emitting control transistor and the second light-emitting control transistor are arranged on both sides of the active part of the driving transistor in the extension direction of the active part of the driving transistor; so that the first light-emitting control transistor and the second light-emitting control transistor are reasonably arranged on the substrate, which is conducive to the miniaturization of the pixel driving circuit.

[0026] The source part of the first light-emitting control transistor is electrically connected with the driving power supply line; and the drain part of the first light-emitting control transistor is connected with the source part of the driving transistor.

[0027] The source part of the second light-emitting control transistor is connected with the drain part of the driving transistor; and the drain part of the second light-emitting control transistor is used for being electrically connected with the light-emitting element.

[0028] The gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are electrically connected with a light-emitting control signal line; and the light-emitting control signal line is arranged in extension along the second direction.

[0029] Preferably, the pixel driving circuit further comprises an anode initialization transistor; the drain part of the anode initialization transistor is connected with the drain part of the second light-emitting control transistor; the source part of the anode initialization transistor is electrically connected with a reference voltage signal line; and the gate of the anode initialization transistor is electrically connected with a third scanning line, so that the third scanning line is multiplexed as the gate of the anode initialization transistor, which simplifies the gate wiring and improves the miniaturization of the pixel driving circuit.

[0030] To solve the above technical problems, another technical solution adopted by the present application is: a display panel comprising the array substrate.

[0031] The present application provides an array substrate and a display panel, wherein in the array substrate, the pixel driving circuit is improved by optimizing the stack structure of the pixel driving circuit and introducing a virtual electrode, so as to improve the display abnormality caused by signal crosstalk. The improved pixel driving circuit is stable, reliable and simple in structure, and can be applied in full-screen technology. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0033] Figure 1 is a circuit schematic diagram of the pixel driving circuit provided by the present application;

[0034] Figure 2 is Figure 1 the layout of the pixel driving circuit provided by the present application;

[0035] Figure 3 is Figure 2 an enlarged view of the A area in the layout of the pixel driving circuit provided by the present application;

[0036] Figure 4 is Figure 2 a structural schematic diagram of the semiconductor layer in the layout of the pixel driving circuit provided by the present application;

[0037] Figure 5 is Figure 2 a sectional view at the driving transistor in the array substrate of the pixel driving circuit provided by the present application;

[0038] Figure 6 is a structural schematic diagram of the display panel provided by the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0040] The terms “first”, “second”, “third” in the present application are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first”, “second”, “third” can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of “a plurality of” is at least two, such as two, three, etc., unless otherwise explicitly and specifically limited. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative positional relationship, movement condition, etc. between the components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly. In addition, the terms “include” and “have” and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0041] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to those of ordinary skill in the art, embodiments described herein can be combined with other embodiments.

[0042] The application will be described in detail below with reference to the attached drawings and embodiments.

[0043] Reference will now be made to Figure 1 , Figure 1 is a circuit schematic diagram of a pixel driving circuit provided by the application.

[0044] Reference will now be made to Figure 1 , the application provides a pixel driving circuit, comprising a driving transistor T1, a switching transistor T2, a compensation transistor T3, an initialization transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, an anode initialization transistor T7, and a storage capacitor Cst.

[0045] The source part of the first light-emitting control transistor T5 writes an electrical signal of a driving power supply line ELVDD. The gate of the first light-emitting control transistor T5 writes an electrical signal of a light-emitting control signal line EM, which is used to control the conduction or turn-off of the first light-emitting control transistor T5.

[0046] The source part of the switching transistor T2 writes an electrical signal of a data line Data. The gate of the switching transistor T2 writes an electrical signal of a second scan line SCAN2, which is used to control the conduction or turn-off of the switching transistor T2.

[0047] The drain part of the first light-emitting control transistor T5 and the drain part of the switching transistor T2 are electrically connected to the source part of the driving transistor T1.

[0048] The electrical signal of the driving power supply line ELVDD is electrically connected to the first capacitor electrode C1 of the storage capacitor Cst, and the second capacitor electrode C2 of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1.

[0049] The source part of the initialization transistor T4 writes a reference voltage signal line Vref. The gate of the initialization transistor T4 writes an electrical signal of a first scan line SCAN1, which is used to control the conduction or turn-off of the initialization transistor T4. The drain part of the initialization transistor T4 is electrically connected to the source part of the compensation transistor T3.

[0050] The source of the compensation transistor T3 is electrically connected with the gate of the driving transistor T1. The second scan line SCAN2 is electrically connected with the gate of the compensation transistor T3, for controlling the on or off of the compensation transistor T3. The drain of the compensation transistor T3 is electrically connected with the drain of the driving transistor T1 and the source of the second light emitting control transistor T6.

[0051] The source of the anode initialization transistor T7 is electrically connected with the reference voltage signal line Vref. The gate of the anode initialization transistor T7 is electrically connected with the third scan line SCAN3, for controlling the on or off of the anode initialization transistor T7. The drain of the anode initialization transistor T7 is electrically connected with the drain of the second light emitting control transistor T6 and the light emitting element.

[0052] Referring to Figures 2-4 , Figure 2 is Figure 1 the layout of the pixel driving circuit provided by the present application, Figure 3 is Figure 2 the layout of the pixel driving circuit provided by the present application, Figure 4 is Figure 2 the structure of the semiconductor layer in the layout of the pixel driving circuit provided by the present application.

[0053] Referring to Figures 2-4 , the data line Data and the driving power line ELVDD are arranged along the first direction Y in the layout of the pixel driving circuit 20 provided by the present application. The plurality of scan lines are arranged along the second direction X. The first direction Y and the second direction X can be crossed. In the present embodiment, the first direction Y and the second direction X are arranged perpendicularly.

[0054] Specifically, in the present embodiment, the reference voltage signal line Vref, the first scan line SCAN1, the second scan line SCAN2, the light emitting control signal line EM and the third scan line SCAN3 are arranged along the second direction X and are arranged in sequence and spaced apart along the first direction Y. The data line Data and the driving power line ELVDD are arranged along the first direction Y and are arranged in sequence and spaced apart along the second direction X. The projection of the reference voltage signal line Vref, the first scan line SCAN1, the second scan line SCAN2, the light emitting control signal line EM and the third scan line SCAN3 on the substrate 10 crosses the projection of the data line Data and the driving power line ELVDD on the substrate 10.

[0055] In the embodiments of the present application, the driving transistor T1 and the compensation transistor T3 are located on the side of the driving power line ELVDD away from the data line Data. The switching transistor T2 is located on the side of the driving power line ELVDD close to the data line Data. Along the first direction Y, the switching transistor T2 and the compensation transistor T3 are located on the same side of the driving transistor T1. The gate of the switching transistor T2 and the gate of the compensation transistor T3 are electrically connected with the second scan line SCAN2 respectively. The second scan line SCAN2 is arranged between the compensation transistor T3 and the driving transistor T1.

[0056] The drain of the switching transistor T2 is connected with the source of the driving transistor T1. The source of the switching transistor T2 is electrically connected with the data line Data. The gate of the switching transistor T2 is electrically connected with the second scan line SCAN2 and arranged in the same layer. In the embodiments, the source of the switching transistor T2 is electrically connected with the data line Data through the second via hole H2.

[0057] The drain of the compensation transistor T3 is connected with the drain of the driving transistor T1. The source of the compensation transistor T3 is electrically connected with the gate of the driving transistor T1. The gate of the compensation transistor T3 is electrically connected with the second scan line SCAN2 and arranged in the same layer. The second scan line SCAN2 of the embodiments of the present application is arranged between the driving transistor T1 and the compensation transistor T3. The compensation transistor T3 of the embodiments of the present application can be a single-gate transistor or a double-gate transistor. The compensation transistor T3 of the embodiments is a double-gate transistor. In the embodiments, the source of the compensation transistor T3 is electrically connected with the gate of the driving transistor T1 through the third via hole H3.

[0058] In the pixel driving circuit 20 provided by the present application, the driving transistor T1, the switching transistor T2 and the compensation transistor T3 are arranged compactly on the substrate 10, which is beneficial to the miniaturization of the pixel driving circuit 20, improves the density of the light emitting element 201 (as shown in the figure) controlled by the pixel driving circuit 20, and further improves the display quality of the display panel 300 (as shown in the figure) of the present application. Figure 6 Figure 6

[0059] The inventors found in the research that, with the miniaturization of the pixel driving circuit 20, the signal crosstalk phenomenon (crosstalk) between the various wirings (such as the data line Data, the scan line SCAN1 / SCAN2 / SCAN3 and the driving power line ELVDD in the present application) inside the pixel driving circuit 20 is exacerbated, thereby affecting the display panel 300 (as shown in the figure). Figure 6 ​​The display quality of the display panel. Specifically, in the pixel driving circuit 20 provided by the present application, the source of the switch transistor T2 and the source of the compensation transistor T3 are close to each other and have a parasitic capacitance. The potential change of the data line Data will affect the potential of the gate of the driving transistor T1 electrically connected to the source of the compensation transistor T3 through the parasitic capacitance, so that the potential of the gate of the driving transistor T1 changes, causing signal crosstalk.

[0060] In the prior art, the parasitic capacitance is reduced by increasing the distance between the wirings, for example, by increasing the distance between the source of the switch transistor T2 and the source of the compensation transistor T3. However, this method of reducing the parasitic capacitance is contrary to the original intention of miniaturizing the pixel circuit.

[0061] Therefore, the pixel driving circuit 20 provided by the present application solves the problem of signal crosstalk while achieving miniaturization. Specifically, the pixel driving circuit 20 provided by the present application is provided with at least one dummy electrode (Dummy-PSi) DP patterned between the source of the switch transistor T2 and the source of the compensation transistor T3 to reduce the parasitic capacitance between the source of the switch transistor T2 and the source of the compensation transistor T3, thereby avoiding signal crosstalk between the potential of the data line Data and the potential of the gate of the driving transistor T1. In the specific embodiments of the present application, the dummy electrode DP is disposed in the same layer as the active part of each transistor, and the material of the dummy electrode DP is the same as the material of the semiconductor layer of the driving transistor T1, without increasing the complexity of the photomask process. It can be understood that the dummy electrode DP of the present application can also be provided at other places in the pixel driving circuit 20 where signal crosstalk occurs, which is not limited specifically herein.

[0062] Further, in the specific embodiments of the present application, the dummy electrode DP is electrically connected to the driving power supply line ELVDD to shield the crosstalk of the voltage jump of the data line Data to the potential of the gate of the driving transistor T1. The dummy electrode DP is an independent patterned semiconductor, which is not connected to other structures in the pixel driving circuit 20 except for being electrically connected to the driving power supply line ELVDD. In some specific embodiments, the dummy electrode DP and the driving power supply line ELVDD at least partially overlap on the projection of the substrate 10 (the structure of the substrate 10 is shown in FIG. 1) to reduce the wiring distance between the driving power supply line ELVDD and the dummy electrode DP. Specifically, in the present embodiment, the dummy electrode DP is electrically connected to the driving power supply line ELVDD through the first via hole H1, which can effectively simplify the preparation process. Further, the dummy electrode DP in the specific embodiments of the present application can be a heavily doped semiconductor to improve the shielding property of the dummy electrode DP to signal crosstalk. Figure 5 、 Figure 6

[0063] ​To further reduce the parasitic capacitance between the source of the switch transistor T2 and the source of the compensation transistor T3, the voltage jump of the data line Data is shielded from the crosstalk of the gate potential of the driving transistor T1. The specific embodiment of the present application improves the structure of the dummy electrode DP. Specifically, the source of the switch transistor T2 is electrically connected to the data line Data through the second via hole H2. The source of the compensation transistor T3 is connected to the connection line J1 through the third via hole H3, and the connection line J1 is electrically connected to the gate of the driving transistor T1 through the fourth via hole H4.

[0064] The dummy electrode DP has a first end DP1 and a second end DP2. Along the first direction Y, the first end DP1 is located on the side of the second via hole H2 and the third via hole H3 away from the driving transistor T1, and the second end DP2 is located on the side of the second via hole H2 and the third via hole H3 close to the driving transistor T1. Specifically, in the embodiment, the dummy electrode DP is a strip-shaped semiconductor having a first end DP1 and a second end DP2 along the first direction Y; the dummy electrode DP is located between the source of the switch transistor T2 and the source of the compensation transistor T3, and separates the source of the switch transistor T2 and the source of the compensation transistor T3. In some specific embodiments, along the first direction Y, the first end DP1 is located on the side of the source of the switch transistor T2 and the source of the compensation transistor T3 away from the driving transistor T1, and the second end DP2 is located on the side of the source of the switch transistor T2 and the source of the compensation transistor T3 close to the driving transistor T1. That is, along the second direction X, the projection of the dummy electrode DP on the source of the switch transistor T2 covers the source of the switch transistor T2, and the projection of the dummy electrode DP on the source of the compensation transistor T3 covers the source of the compensation transistor T3. In the embodiment, the first end DP1 is located on the side of the source of the switch transistor T2 away from the driving transistor T1, and the second end DP2 is located on the side of the source of the compensation transistor T3 close to the driving transistor T1.

[0065] Further, in order to stabilize the potential of the compensation transistor T3, the pixel driving circuit 20 further comprises a conductive layer CL, which is electrically connected to the driving power supply line ELVDD; the conductive layer CL covers at least part of the dummy electrode DP, part of the source of the compensation transistor T3 and part of the drain of the compensation transistor T3. In the embodiment, the compensation transistor T3 is a double-gate transistor, and the conductive layer CL covers the source and drain of one of the double-gate transistors and the dummy electrode DP.

[0066] In some specific embodiments, the gate of the switch transistor T2 and the gate of the compensation transistor T3 are respectively electrically connected to the second scan line SCAN2, and the second scan line SCAN2 is arranged between the compensation transistor T3 and the driving transistor T1, thereby reducing the area of the pixel driving circuit 20.

[0067] In some embodiments, the storage capacitor Cst includes a first capacitor electrode C1 and a second capacitor electrode C2 arranged oppositely. In some embodiments, the storage capacitor Cst and the driving transistor T1 at least partially overlap in the orthographic projection of the substrate 10. The gate of the driving transistor T1 serves as the second capacitor electrode C2. The first capacitor electrode C1 partially overlaps the driving power line ELVDD in the orthographic projection of the substrate 10, and the first capacitor electrode C1 is electrically connected to the driving power line ELVDD. In some embodiments, the storage capacitor Cst is arranged on the side of the driving transistor T1 away from the substrate 10, thereby reducing the area of the pixel driving circuit 20. Specifically, the first capacitor electrode C1 is provided with an opening C11, and the gate of the driving transistor T1 is electrically connected to the source of the compensation transistor T3 through the opening C11, so that the storage capacitor Cst is arranged on the side of the driving transistor T1 away from the substrate 10 without affecting the data writing of the gate of the driving transistor T1.

[0068] In some embodiments, the source of the initialization transistor T4 is electrically connected to the reference voltage signal line Vref for writing a reference voltage signal; the drain of the initialization transistor T4 is connected to the gate of the driving transistor T1 and the source of the compensation transistor T3; the initialization transistor T4 writes the reference voltage signal to the gate of the driving transistor T1; and the gate of the initialization transistor T4 is electrically connected to the first scan line SCAN1. In some embodiments, the initialization transistor T4 can be a single-gate transistor or a double-gate transistor. In some embodiments, the initialization transistor T4 is a double-gate transistor.

[0069] In some embodiments, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are arranged on the side of the driving transistor T1 away from the compensation transistor T3 in the first direction Y, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are arranged on both sides of the active region of the driving transistor T1 in the extension direction of the active region of the driving transistor T1. The source of the first light-emitting control transistor T5 is electrically connected to the driving power line ELVDD. The drain of the first light-emitting control transistor T5 is connected to the source of the driving transistor T1. The source of the second light-emitting control transistor T6 is connected to the drain of the driving transistor T1. The drain of the second light-emitting control transistor T6 is electrically connected to the light-emitting element 201. The gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6 are electrically connected to the light-emitting control signal line EM. In some embodiments, the light-emitting control signal line EM extends in the second direction X.

[0070] In some specific embodiments, the drain of the anode initialization transistor T7 is connected with the drain of the second light emitting control transistor T6. The source of the anode initialization transistor T7 is electrically connected with the reference voltage signal line Vref. The gate of the anode initialization transistor T7 is electrically connected with the third scan line SCAN3.

[0071] Referring to Figure 5 , Figure 5 is Figure 2 a cross-sectional view of a driving transistor at an array substrate of

[0072] Referring to Figure 5 , the array substrate 100 provided by the present application comprises, from bottom to top, a substrate 10, a semiconductor layer 21, a first insulating layer 22, a first conductive layer 23, a second insulating layer 24, a second conductive layer 25, a third insulating layer 26, a third conductive layer 27, a planarization layer 28, an anode layer 29, and a pixel definition layer 30.

[0073] The substrate 10 of the embodiment of the present application can be a rigid substrate or a flexible substrate, which can be reasonably arranged as required. The substrate 10 can be a single-layer substrate or a multi-layer substrate. When the substrate 10 is a multi-layer substrate, inorganic barrier layers are filled between adjacent two layers, which can be made of inorganic insulating materials such as silicon oxide or silicon nitride, which can be reasonably arranged as required. The semiconductor layer 21 is arranged on one side of the substrate 10, which can be made of an amorphous silicon layer, a single crystal silicon layer, a polycrystalline silicon layer or a metal oxide layer, which can be reasonably arranged as required. In the embodiment, the semiconductor layer 21 can be made of a polycrystalline silicon layer (PSI). The active part of the driving transistor T1 in the embodiment of the present application can be part of the semiconductor layer 21, which includes a source part 211, a channel part 212 and a drain part 213. A buffer layer can be arranged on a layer of the substrate 10 in contact with the semiconductor layer 21, which can be made of materials such as silicon oxide or silicon nitride, which can be reasonably arranged as required. The first insulating layer 22 is arranged on the side of the semiconductor layer 21 away from the substrate 10 and covers the patterned semiconductor layer 21. The first insulating layer 22 can be made of inorganic insulating materials such as silicon oxide or silicon nitride, which can be reasonably arranged as required. The first conductive layer 23 is arranged on the side of the first insulating layer 22 away from the substrate 10, and the gate of the driving transistor T1 in the embodiment of the present application is part of the first conductive layer 23. The second insulating layer 24 is arranged on the side of the first conductive layer 23 away from the substrate 10 and covers the patterned first conductive layer 23. The second insulating layer 24 can be made of inorganic insulating materials such as silicon oxide or silicon nitride, which can be reasonably arranged as required. The second conductive layer 25 is arranged on the side of the second insulating layer 24 away from the substrate 10. The first capacitor electrode C1 of the storage capacitor CST in the embodiment of the present application is part of the second conductive layer 25. The gate of the driving transistor T1 in the embodiment of the present application serves as the second capacitor electrode C2 of the storage capacitor CST. The third insulating layer 26 covers the patterned second conductive layer 25. The third conductive layer 27 is arranged on the side of the third insulating layer 26 away from the substrate 10. The source 271 and the drain 272 of the driving transistor T1 in the embodiment of the present application are part of the third conductive layer 27. The driving power line ELVDD in the embodiment of the present application is part of the third conductive layer 27. The driving power line ELVDD is electrically connected with the first capacitor electrode C1 of the storage capacitor CST. The planar layer 28 is arranged on the side of the third conductive layer 27 away from the substrate 10. The anode layer 29 is arranged on the side of the planar layer 28 away from the substrate 10. The pixel definition layer 30 is arranged on the side of the anode layer 29 away from the substrate 10.

[0074] Please refer to Figure 6 , Figure 6 which is a structural schematic diagram of a display panel provided by the present application.

[0075] Please refer to Figure 6The display panel 300 provided in the present application comprises an array substrate 100 and a light emitting element layer 200. The array substrate 100 comprises a substrate 10 and a plurality of pixel driving circuits 20 arranged on the substrate 10. The light emitting element layer 200 comprises a plurality of light emitting elements 201. The pixel driving circuit 20 is electrically connected with the light emitting element 201, and is used for controlling pixel display of the light emitting element 201. The light emitting element 201 in the embodiment can be an organic light emitting diode.

[0076] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the division of the above-described device embodiments is only a logical function division, and there can be another division manner for actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different units, or the mutual couplings or direct couplings or communication connections displayed or discussed as being separated, can be indirect couplings or communication connections through some interface, device or unit, and can be in electrical, mechanical or other forms.

[0077] In addition, each function unit in the embodiments of the present application can be integrated in a processing unit, or each unit can exist alone physically, or two or more units can be integrated in one unit. The integrated unit can be implemented in the form of hardware, or in the form of a software function unit.

[0078] The above descriptions are only some embodiments of the present application, and do not limit the patent scope of the present application, and any equivalent structure or equivalent flow transformation using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An array substrate, comprising a substrate and a plurality of pixel driving circuits disposed on the substrate, characterized in that, The pixel driving circuit includes: The data cable is set to extend along the first direction; The drive power line extends along the first direction; Drive transistors; A switching transistor is disposed on the side of the driving transistor close to the data line, and the drain of the switching transistor is connected to the source of the driving transistor; the source of the switching transistor is electrically connected to the data line. A compensation transistor is disposed on the side of the driving power line away from the data line; the drain of the compensation transistor is connected to the drain of the driving transistor; the source of the compensation transistor is electrically connected to the gate of the driving transistor. In this embodiment, at least one patterned virtual electrode is provided between the source portion of the switching transistor and the source portion of the compensation transistor; the virtual electrode is electrically connected to the driving power supply line.

2. The array substrate according to claim 1, characterized in that, The driving transistor and the compensation transistor are located on the side of the driving power line away from the data line; the switching transistor is located on the side of the driving power line close to the data line; along the first direction, the switching transistor and the compensation transistor are located on the same side of the driving transistor; preferably, the gate of the switching transistor and the gate of the compensation transistor are electrically connected to the second scan line respectively; the second scan line is disposed between the compensation transistor and the driving transistor.

3. The array substrate according to claim 2, characterized in that, The compensation transistor is a dual-gate transistor.

4. The array substrate according to claim 2, characterized in that, The virtual electrode at least partially overlaps with the projection of the driving power line on the substrate; the virtual electrode is electrically connected to the driving power line through a first via.

5. The array substrate according to claim 1, characterized in that, The material of the virtual electrode is the same as the material of the semiconductor layer of the driving transistor.

6. The array substrate according to claim 5, characterized in that, The virtual electrode is a heavily doped semiconductor.

7. The array substrate according to claim 1, characterized in that, The source of the switching transistor is electrically connected to the data line through a second via; the source of the compensation transistor is connected to the connecting line through a third via, and the connecting line is electrically connected to the gate of the driving transistor. The virtual electrode has a first end and a second end along a first direction; the first end is located on the side of the second via and the third via away from the driving transistor along the first direction, and the second end is located on the side of the second via and the third via close to the driving transistor.

8. The array substrate according to claim 7, characterized in that, Along a first direction, the first end is located on the side of the source portion of the switching transistor and the source portion of the compensation transistor away from the driving transistor, and the second end is located on the side of the source portion of the switching transistor and the source portion of the compensation transistor close to the driving transistor.

9. The array substrate according to claim 1, characterized in that, The pixel driving circuit further includes a conductive layer electrically connected to the driving power line; the conductive layer at least covers a portion of the virtual electrode, a portion of the source portion of the compensation transistor, and a portion of the drain portion of the compensation transistor.

10. The array substrate according to claim 1, characterized in that, The pixel driving circuit further includes a storage capacitor, which includes a first capacitor electrode and a second capacitor electrode disposed opposite to each other; the storage capacitor at least partially overlaps with the orthographic projection of the driving transistor on the substrate; the gate of the driving transistor serves as the second capacitor electrode; The first capacitor electrode overlaps with the driving power line in the orthographic projection portion of the substrate, and the first capacitor electrode is electrically connected to the driving power line.

11. The array substrate according to claim 10, characterized in that, An opening is provided on the first capacitor electrode, and the gate of the driving transistor is electrically connected to the source of the compensation transistor through the opening.

12. The array substrate according to claim 1, characterized in that, The pixel driving circuit further includes an initialization transistor; the source of the initialization transistor is electrically connected to a reference voltage signal line; the drain of the initialization transistor is connected to the gate of the driving transistor and the source of the compensation transistor; the gate of the initialization transistor is electrically connected to a first scan line.

13. The array substrate according to claim 12, characterized in that, The initialization transistor is a dual-gate transistor.

14. The array substrate according to claim 1, characterized in that, The pixel driving circuit further includes a first light-emitting control transistor and a second light-emitting control transistor; the first light-emitting control transistor and the second light-emitting control transistor are both disposed on the side of the driving transistor away from the compensation transistor in the first direction, and the first light-emitting control transistor and the second light-emitting control transistor are disposed on both sides of the active portion of the driving transistor in the extension direction of the active portion of the driving transistor. The source of the first light-emitting control transistor is electrically connected to the driving power line; the drain of the first light-emitting control transistor is connected to the source of the driving transistor. The source of the second light-emitting control transistor is connected to the drain of the driving transistor; the drain of the second light-emitting control transistor is used for electrical connection with the light-emitting element. The gates of the first light-emitting control transistor and the second light-emitting control transistor are both electrically connected to the light-emitting control signal line; the light-emitting control signal line extends along the second direction.

15. The array substrate according to claim 14, characterized in that, The pixel driving circuit further includes an anode initialization transistor; the drain of the anode initialization transistor is connected to the drain of the second light-emitting control transistor; the source of the anode initialization transistor is electrically connected to the reference voltage signal line; and the gate of the anode initialization transistor is electrically connected to the third scan line.

16. A display panel, characterized in that, The array substrate includes any one of claims 1 to 15.

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