Clock offset error calibration circuit and integrated circuit

Abstract

The application discloses a clock offset error calibration circuit and an integrated circuit, and is applied to the technical field of integrated circuits, wherein a common-mode signal channel is connected with a first differential input end and a second differential input end simultaneously; a differential signal input end is connected with an ADC module; a service signal end and a correction signal end are connected with the ADC module; the common-mode signal channel is used for inputting a test signal to the first differential input end and the second differential input end; and the ADC module is used for obtaining a voltage signal; the service signal end generates a service signal; the correction signal end generates a correction signal; the correction signal is associated with the service signal; and a clock offset error is obtained. The test signal is injected into the differential signal through the common-mode signal channel, so that the test signal and the service signal existing in the differential signal channel are completely separated, the clock offset error information is conveniently extracted, and finally, the clock offset error is compensated in a clock circuit, so that the accurate calibration of the clock offset error is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, in particular to a clock offset error calibration circuit and an integrated circuit. BACKGROUND

[0002] Limited by power consumption and process, the sampling rate of single-path ADC (analog-to-digital conversion circuit) is usually below 1GSPS. In order to realize the wireless receiver architecture of radio frequency direct sampling and microwave direct sampling, the sampling rate of ADC needs to be improved to several to tens of GSPS, and the multi-path time-interleaved ADC architecture is the key technology to realize such performance and is an important research direction in the field of analog-to-digital converters in recent years.

[0003] The performance of the multi-path time-interleaved ADC is limited by the interleaving mismatch error, including: offset, gain, clock skew, and bandwidth mismatch in each interleaving path. Among them:

[0004] The offset mismatch error is manifested in the spectrum as a fixed frequency and fixed energy spurious signal, which is independent of the characteristics of the input signal. The offset can be easily obtained by statistically averaging the signal of each interleaving path, and can be subtracted in the digital domain.

[0005] The gain mismatch error is manifested in the spectrum as a spurious signal at the signal image position, and its amplitude changes proportionally with the input signal amplitude. The gain can be relatively easily obtained by statistically averaging the root mean square value of the signal of each interleaving path, and can be multiplied by the corresponding coefficient in the digital domain to make the gain of each path consistent.

[0006] The bandwidth mismatch is caused by the limited bandwidth of the sampling network of each interleaving channel, which is difficult to model and compensate. Generally, the analog design is used to ensure that the sampling network bandwidth is much larger than the signal bandwidth to ensure that this error does not have a significant impact on the performance.

[0007] The common feature of the above three types of mismatch is that they are caused by the characteristic mismatch between each path of the interleaved ADC channel. There is a random channel selection method that can scatter the spurious signals caused by them in the spectrum into random noise, thereby alleviating the deterioration of linearity.

[0008] Skew refers to the non-equidistant sampling phenomenon caused by the sampling time deviation of each interleaving channel from the ideal value, which is mainly caused by the phase delay mismatch of the multi-phase clock generation circuit, and is manifested as mirror spurious signals in the frequency spectrum, which changes proportionally with the power and frequency of the input signal and cannot be dispersed by random channel selection; when the input signal is in the radio frequency band or even the microwave frequency band, the performance deterioration caused by skew is particularly serious, therefore, skew calibration is one of the main difficulties in the design of multi-channel time-interleaved ADC. Therefore, how to provide a clock offset error calibration circuit that can accurately calibrate the clock offset is a problem that those skilled in the art urgently need to solve. SUMMARY

[0009] The purpose of the present application is to provide a clock offset error calibration circuit that can accurately calibrate the clock offset; another purpose of the present application is to provide an integrated circuit that can accurately calibrate the clock offset.

[0010] To solve the above technical problems, the present application provides a clock offset error calibration circuit, comprising a differential signal input end, a common mode signal channel, an ADC module, a service signal end and a correction signal end.

[0011] The differential signal input end comprises a first differential input end and a second differential input end, and the common mode signal channel is connected to the first differential input end and the second differential input end at the same time; the differential signal input end is connected to the ADC module, and the service signal end and the correction signal end are both connected to the ADC module.

[0012] The common mode signal channel is used to input a test signal to the first differential input end and the second differential input end, the ADC module is used to convert the differential signal with the test signal from time domain to digital domain to obtain a voltage signal; the service signal end generates a service signal based on the voltage signal, and the correction signal end generates a correction signal based on the voltage signal, so as to associate the correction signal with the service signal to obtain a clock offset error, and correct the clock.

[0013] Optionally, the ADC module comprises a first ADC unit and a second ADC unit, the first differential input end is connected to the first ADC unit through a first signal channel, and the second differential input end is connected to the second ADC unit through a second signal channel; the service signal end is connected to the first ADC unit and the second ADC unit at the same time, and the correction signal end is connected to the first ADC unit and the second ADC unit at the same time.

[0014] Optionally, the first ADC unit is configured to convert a signal in the first signal channel from a time domain to a digital domain to obtain a first voltage signal; the second ADC unit is configured to convert a signal in the second signal channel from the time domain to the digital domain to obtain a second voltage signal; the service signal terminal is configured to subtract the first voltage signal from the second voltage signal to obtain a service signal; and the correction signal terminal is configured to add the first voltage signal and the second voltage signal to obtain a correction signal, associate the correction signal with the service signal, and obtain a clock offset error to correct the clock.

[0015] Optionally, the differential signal input terminal is connected to the ADC module through a buffer module.

[0016] Optionally, the buffer module comprises a first transistor and a second transistor, the first differential input terminal is connected to a gate of the first transistor, a source of the first transistor is connected to the first ADC unit through the first signal channel; the second differential input terminal is connected to a gate of the second transistor, a source of the second transistor is connected to the second ADC unit through the second signal channel.

[0017] Optionally, the first ADC unit comprises a first DAC switch, a first SAR logic circuit and a first comparator, the first signal channel is connected to an input terminal of the first DAC switch and the first comparator, an output terminal of the first comparator is connected to the first SAR logic circuit, and the first SAR logic circuit is connected to the first DAC switch; the second ADC unit comprises a second DAC switch, a second SAR logic circuit and a second comparator, the second signal channel is connected to an input terminal of the second DAC switch and the second comparator, an output terminal of the second comparator is connected to the second SAR logic circuit, and the second SAR logic circuit is connected to the second DAC switch.

[0018] The service signal terminal is connected to the first SAR logic circuit and the second SAR logic circuit simultaneously, and the correction signal terminal is connected to the first SAR logic circuit and the second SAR logic circuit simultaneously.

[0019] Optionally, the first comparator and the second comparator are connected to the same reference voltage.

[0020] Optionally, the differential signal input terminal is connected to the ADC module through a switch, the switch is connected to a clock circuit, and the clock circuit is corrected by the clock offset error.

[0021] Optionally, the test signal is a single tone signal.

[0022] The present invention also provides an integrated circuit including a clock offset error calibration circuit as described in any of the preceding claims.

[0023] The present invention provides a clock offset error calibration circuit, comprising a differential signal input terminal, a common-mode signal channel, an ADC module, a service signal terminal, and a correction signal terminal. The differential signal input terminal includes a first differential input terminal and a second differential input terminal, and the common-mode signal channel is connected to both the first and second differential input terminals. The differential signal input terminal is connected to the ADC module, and both the service signal terminal and the correction signal terminal are connected to the ADC module. The common-mode signal channel is used to input test signals to the first and second differential input terminals. The ADC module is used to convert the differential signal with the input test signal from the time domain to the digital domain to obtain a voltage signal. The service signal terminal generates a service signal based on the voltage signal, and the correction signal terminal generates a correction signal based on the voltage signal. The correction signal is correlated with the service signal to obtain the clock offset error and correct the clock.

[0024] Injecting a test signal into the differential signal via the common-mode signal channel completely separates the test signal from the service signal present in the differential-mode signal channel, preventing mutual interference and maintaining the ADC's range. In the clock offset error calibration circuit, the common-mode value is sampled simultaneously with the differential signal. Therefore, the clock offset error is the same for both the differential and common-mode signals. The ADC module then quantizes the separated differential and common-mode signals, allowing the clock offset error information to be extracted in the digital domain through autocorrelation calculation of the test signal. Finally, this error is compensated for in the clock circuit, achieving accurate clock offset error calibration.

[0025] The present invention also provides an integrated circuit that has the same beneficial effects as described above, which will not be described in detail here. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of a clock offset error calibration circuit provided in an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of a specific clock offset error calibration circuit provided in an embodiment of the present invention.

[0029] In the figure: 1. differential signal input end, 2. common mode signal channel, 3. ADC module, 31. first ADC unit, 32. second ADC unit, 4. service signal end, 5. correction signal end, 6. buffer module, 61. first transistor, 62. second transistor, 7. switch. DETAILED DESCRIPTION

[0030] In order to make the person in the technical field better understand the present application scheme, the present application is further described in detail below in combination with the drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without making creative labor belong to the scope of protection of the present application.

[0031] The core of the present application is to provide a clock offset error calibration circuit. In the prior art, there are several existing methods for detecting and calibrating the clock offset error of time-interleaved ADC:

[0032] First, autocorrelation statistics method

[0033] Detect whether the autocorrelation value of the adjacent two sampling points of the input signal changes with the sampling time. If it is independent of the sampling time, it is considered to be equal interval sampling, that is, there is no skew error, otherwise it is considered to exist skew error.

[0034] For example, in equal interval sampling, the autocorrelation value of the adjacent two sample points can be calculated as: E[Vin(t)Vin(t+Ts)]=R(Ts), where Ts is the equal interval sampling period, and R() is the autocorrelation function; In non-equal interval sampling, suppose the sampling time of two-channel time-interleaved is k*Ts, (k+1)*Ts+Δ, then E[Vin(k*Ts)Vin((k+1)*Ts+Δ)=R(Ts+Δ)≠R(Ts-Δ)=E[Vin((k+1)*Ts+Δ)Vin((k+2)*Ts)], the error e=R(Ts+Δ)-R(Ts-Δ) can represent the skew information: Δ.

[0035] The advantage of this method is that it can run in the background without interrupting the normal work of the ADC, and the calculation method is simple. The disadvantage is that it depends on the generalized stationary characteristics of the input signal after sampling, and it will fail under many input conditions and also fail when there is no input signal.

[0036] Second, mirror energy detection method

[0037] By oversampling, the input signal only occupies the low frequency part of the Nyquist bandwidth, and the mirror occupies the empty high frequency part of the spectrum. In the digital domain, the energy of the high frequency band can be detected to extract the skew information.

[0038] This method is running in the background, and does not interrupt the normal work of ADC. The disadvantage is that it depends on oversampling, and has requirements for the frequency range of the input signal.

[0039] Third, slope signal injection method

[0040] At each interleaved channel sampling, an artificially generated identical slope signal is injected. The difference between the results of the slope signal sampling of different channels is K*Δ, where K is the slope, and Δ is the skew value.

[0041] The advantage of this method is that the test signal is artificially generated, and the effect does not depend on the input signal. The disadvantage is that the precision is low, and the additional analog circuit needs to be carefully designed, which may affect the normal work of the ADC.

[0042] Fourth, reference channel

[0043] An additional low-precision reference channel is designed outside all interleaved ADC channels, which works at full speed or samples at the same time as a certain interleaved channel at a certain period. By comparing the difference between the quantization results of the reference channel, the skew information is extracted.

[0044] The advantage of this method is that it runs in the background and does not interrupt the normal work of the ADC, and has low requirements for the characteristics of the input signal. The disadvantage is that multiple ADCs sampling at the same time will interfere with each other, affecting the signal quality.

[0045] Fifth, sampling value range detection

[0046] Multiple interleaved ADCs share a full-speed MSB (most significant bit) quantizer, or an additional full-speed voltage range detection circuit. When the input signal appears in the voltage range of the detection circuit, the range of the quantization results of each channel ADC is counted, and the larger range is used as the skew of the channel relative to the detection channel. This is essentially a variation of the reference channel method.

[0047] The advantage of this method is that it runs in the background and does not interrupt the normal work of the ADC. The disadvantage is that the full-speed MSB quantizer or voltage range detection circuit can be considered as a reference channel, which will interfere when sampling at the same time as a certain interleaved ADC. In addition, if the input signal does not appear in the voltage detection range, the method cannot work.

[0048] Among the above methods, the first method is the most traditional and mature, and is widely used in practice. However, in large-scale interleaved ADC architecture, its failure scenarios become more frequent, which makes it necessary to develop a more robust skew calibration method.

[0049] The inevitable way to overcome the dependence of skew calibration effect on input signal to improve calibration robustness is to inject a calibration test signal, detect the signal feature change caused by non-equidistant sampling of the test signal in the digital domain as the indication information of skew error. In order to realize the background calibration following the temperature and voltage change, the test signal and the service signal must be input into the time-interleaved ADC at the same time for sampling and quantization, and cannot interfere with each other.

[0050] For several common test signal injection methods, it specifically includes test signal and service signal time-sharing injection, and test signal and service signal frequency band injection.

[0051] For test signal and service signal time-sharing injection, the mutual interference of the two types of signals can be avoided to the greatest extent, but it can only be applied in some specific scenarios, such as TDD (test library) scenario, which is not applicable when the ADC needs to work continuously.

[0052] For test signal and service signal frequency band injection, it is similar to the mirror energy detection method in the above, even if the frequency planning can be realized, the test signal is superimposed on the service signal, which will reduce the range of the ADC, in addition, when in order to try not to affect the ADC range, the test signal energy is very small, a digital filter with very large hardware overhead or very long calculation time is needed to extract the test signal energy in the digital domain. Obviously, the above two methods have certain limitations and defects.

[0053] And a clock skew error calibration circuit provided by the application, comprising a differential signal input end, a common mode signal channel, an ADC module, a service signal end and a correction signal end; the differential signal input end comprises a first differential input end and a second differential input end, and the common mode signal channel is connected with the first differential input end and the second differential input end at the same time; the differential signal input end is connected with the ADC module, and the service signal end and the correction signal end are both connected with the ADC module; the common mode signal channel is used for inputting a test signal to the first differential input end and the second differential input end, and the ADC module is used for converting the differential signal with the test signal from time domain to digital domain to obtain a voltage signal; the service signal end generates a service signal based on the voltage signal, and the correction signal end generates a correction signal based on the voltage signal, so as to associate the correction signal with the service signal to obtain a clock skew error, and correct the clock.

[0054] The test signal is injected into the differential signal through the common mode signal channel, so that the test signal can be completely separated from the service signal existing in the differential mode signal channel, without mutual interference and without reducing the range of the ADC. In the clock offset error calibration circuit, the common mode value of the signal is also sampled at the time of sampling the differential signal, so that the clock offset error of each channel is the same for the differential signal and the common mode signal. Then, the separated differential signal and the common mode signal are quantized based on the ADC module, so that the clock offset error information can be extracted through the autocorrelation calculation of the test signal in the digital domain, and finally, the clock offset error is compensated in the clock circuit, so that the clock offset error is accurately calibrated.

[0055] Please refer to Figure 1 , Figure 1 The structure diagram of the clock offset error calibration circuit provided by the embodiment of the application is shown.

[0056] Please refer to Figure 1 In the embodiment of the application, the clock offset error calibration circuit comprises a differential signal input end 1, a common mode signal channel 2, an ADC module 3, a service signal end 4 and a correction signal end 5. The differential signal input end 1 comprises a first differential input end and a second differential input end, and the common mode signal channel 2 is connected with the first differential input end and the second differential input end. The differential signal input end 1 is connected with the ADC module 3, and the service signal end 4 and the correction signal end 5 are connected with the ADC module 3. The common mode signal channel 2 is used for inputting a test signal Vic into the first differential input end and the second differential input end, and the ADC module 3 is used for converting the differential signal input with the test signal Vic from the time domain into the digital domain to obtain a voltage signal. The service signal end 4 generates a service signal Dsig based on the voltage signal, and the correction signal end 5 generates a correction signal Dcom based on the voltage signal, so as to associate the correction signal Dcom with the service signal Dsig to obtain the clock offset error and correct the clock.

[0057] The differential signal input end 1 is used for inputting the differential signal, and the service signal Dsig actually transmitted by the circuit during operation can be extracted from the differential signal. The differential signal input end 1 comprises a first differential input end and a second differential input end, which are respectively used for transmitting two signals Vip and Vin of the differential signal. The signals input by the two differential input ends have the same amplitude and opposite phases.

[0058] The test signal Vic transmitted in the common mode signal channel 2 is a common mode signal, and the common mode signal channel 2 needs to be connected to the first differential input end and the second differential input end at the same time, so as to input the common mode test signal Vic to the first differential input end and the second differential input end at the same time. At this time, the test signal Vic output to the first differential input end and the second differential input end has the same amplitude and the same phase.

[0059] The differential signal input end 1 includes the first differential input end and the second differential input end, which needs to be connected to the ADC module 3, that is, the differential signal injected with the test signal Vic is quantized through the ADC module 3. Specifically, the ADC module 3 converts the differential signal injected with the test signal Vic from the time domain to the digital domain to obtain a voltage signal. The service signal end 4 and the correction signal end 5 are connected to the ADC module 3. Specifically, the service signal end 4 is mainly based on the voltage signal and is used to analyze the differential signal to generate a service signal Dsig; and the correction signal end 5 is mainly based on the voltage signal and is used to analyze the test signal Vic to generate a correction signal Dcom. Then the correction signal Dcom is associated with the service signal Dsig to obtain a clock offset error, and finally the clock is corrected based on the clock offset error.

[0060] The clock offset error calibration circuit provided by the embodiment of the application injects the test signal Vic into the differential signal through the common mode signal channel 2, so that the test signal Vic and the service signal Dsig existing in the differential mode signal channel are completely separated, without interfering with each other and without reducing the range of the ADC. In the clock offset error calibration circuit, the common mode value of the signal is also sampled at the time of sampling the differential signal, so that the clock offset error of each channel is the same for the differential signal and the common mode signal. Then, based on the ADC module 3, the separated differential signal and the common mode signal are quantized, the clock offset error information is extracted through the autocorrelation calculation of the test signal Vic in the digital domain, and finally the clock offset error is compensated in the clock circuit, so that the clock offset error is accurately calibrated.

[0061] The specific content of the clock offset error calibration circuit provided by the application will be described in detail in the following embodiment.

[0062] Please refer to Figure 2 , Figure 2 The structure diagram of a specific clock offset error calibration circuit provided by the embodiment of the application.

[0063] Differing from the above-mentioned embodiments, the embodiments of the present application further limit the structure of the clock offset error calibration circuit on the basis of the above-mentioned embodiments. The remaining contents have been described in detail in the above-mentioned embodiments, and will not be described here again.

[0064] Referring to Figure 2 In the embodiments of the present application, the ADC module 3 in the clock offset error calibration circuit comprises a first ADC unit 31 and a second ADC unit 32, the first differential input end is connected to the first ADC unit 31 through a first signal channel, and the second differential input end is connected to the second ADC unit 32 through a second signal channel; the service signal end 4 is connected to the first ADC unit 31 and the second ADC unit 32 at the same time, and the correction signal end 5 is connected to the first ADC unit 31 and the second ADC unit 32 at the same time.

[0065] That is, the above-mentioned clock offset error calibration circuit has two similar structures, the ADC module 3 comprises a first ADC unit 31 and a second ADC unit 32, wherein the first differential input end is connected to the first ADC unit 31 through a first signal channel, so that the first ADC unit 31 can quantize the signal in the first signal channel; and the second differential input end is connected to the second ADC unit 32 through a second signal channel, so that the second ADC unit 32 can quantize the signal in the second signal channel. The signals transmitted in the first signal channel and the second signal channel are two differential signals after the common-mode test signal Vic is injected.

[0066] The above-mentioned service signal end 4 needs to be connected to the first ADC unit 31 and the second ADC unit 32 at the same time, so as to obtain the service signal Dsig based on the two quantized signals; and correspondingly, the correction signal end 5 needs to be connected to the first ADC unit 31 and the second ADC unit 32 at the same time, so as to obtain the correction signal Dcom based on the two quantized signals.

[0067] Specifically, in the embodiments of the present application, the first ADC unit 31 is used to convert the signal in the first signal channel from the time domain to the digital domain to obtain a first voltage signal; the second ADC unit 32 is used to convert the signal in the second signal channel from the time domain to the digital domain to obtain a second voltage signal; the service signal end 4 is used to subtract the first voltage signal from the second voltage signal to obtain a service signal Dsig, and the correction signal end 5 is used to add the first voltage signal to the second voltage signal to obtain a correction signal Dcom, so as to associate the correction signal Dcom with the service signal Dsig to obtain the clock offset error and correct the clock.

[0068] The first ADC unit 31 quantizes the differential signal Vip input from the first differential input terminal in the first signal channel and the test signal Vic injected, converts them from time domain to digital domain, and obtains a first voltage signal. The second ADC unit 32 quantizes the differential signal Vin input from the second differential input terminal in the second signal channel and the test signal Vic injected, converts them from time domain to digital domain, and obtains a second voltage signal. The service signal terminal 4 is used to subtract the first voltage signal from the second voltage signal, remove the common test signal Vic, and subtract the two differential signals to obtain a service signal Dsig including service information. The correction signal terminal 5 is used to add the first voltage signal and the second voltage signal, remove the differential signal, and obtain a correction signal Dcom based on the test signal Vic.

[0069] When there is no clock offset error in the circuit, the correction signal Dcom is not associated with the service signal Dsig. When the correction signal Dcom is associated with the service signal Dsig, it means that there is a clock offset error in the circuit, and because the sampling time of the differential signal and the common mode signal is the same, the clock offset error included is also the same. In the embodiment of the application, the clock offset error can be determined based on the correlation of the correction signal Dcom and the service signal Dsig, and then compensated in the clock circuit to achieve accurate calibration of the clock offset error. For details of extracting the clock offset error information based on the correlation of the signals and compensating the clock offset error in the clock circuit, reference can be made to the prior art, which will not be described here.

[0070] Specifically, in the embodiment of the application, the first ADC unit 31 includes first DAC (digital-to-analog converter) switches, a first SAR (successive approximation) logic circuit, and a first comparator. The first signal channel is connected to the input terminals of the first DAC switches and the first comparator. The output terminal of the first comparator is connected to the first SAR logic circuit, and the first SAR logic circuit is connected to the first DAC switches. The second ADC unit 32 includes second DAC switches, a second SAR logic circuit, and a second comparator. The second signal channel is connected to the input terminals of the second DAC switches and the second comparator. The output terminal of the second comparator is connected to the second SAR logic circuit, and the second SAR logic circuit is connected to the second DAC switches. The service signal terminal 4 is connected to the first SAR logic circuit and the second SAR logic circuit, and the correction signal terminal 5 is connected to the first SAR logic circuit and the second SAR logic circuit.

[0071] The first ADC unit 31 includes a first DAC switch, a first SAR logic circuit and a first comparator connected with each other. Specifically, a first signal channel connects the first DAC switch with the input end of the first comparator, the output end of the first comparator is connected with the first SAR logic circuit, and the first SAR logic circuit is connected with the first DAC switch to realize quantization of the signal in the first signal channel. Correspondingly, a second signal channel connects the second DAC switch with the input end of the second comparator, and the output end of the second comparator is connected with the second SAR logic circuit, and the second SAR logic circuit is connected with the second DAC switch to realize quantization of the signal in the second signal channel. In general, the first comparator and the second comparator are connected with the same reference voltage Vcm to reduce the contact points in the clock offset error calibration circuit.

[0072] In the embodiment of the present application, the clock offset error calibration circuit generally further includes a buffer module 6, and the differential signal input end 1 is connected with the ADC module 3 through the buffer module 6. The buffer module 6 is used to improve the load capacity of the circuit and ensure the correct signal timing. The differential signal input end 1 is connected with the ADC module 3 through the buffer module 6.

[0073] Specifically, the buffer module 6 includes a first transistor 61 and a second transistor 62. The first differential input end is connected with the gate of the first transistor 61, and the source of the first transistor 61 is connected with the first ADC unit 31 through the first signal channel. The second differential input end is connected with the gate of the second transistor 62, and the source of the second transistor 62 is connected with the second ADC unit 32 through the second signal channel.

[0074] The gate of the first transistor 61 needs to be connected with the first differential input end, and the test signal Vic needs to be injected from the gate of the first transistor 61, and the source of the first transistor 61 needs to be grounded. The gate of the second transistor 62 needs to be connected with the second differential input end, and the test signal Vic needs to be injected from the gate of the second transistor 62, and the source of the second transistor 62 needs to be grounded. The source of the first transistor 61 is connected with the first ADC unit 31 through the first signal channel, so that the first ADC unit 31 quantizes the signal passing through the buffer module 6. The source of the second transistor 62 is connected with the second ADC unit 32 through the second signal channel, so that the second ADC unit 32 quantizes the signal passing through the buffer module 6.

[0075] The buffer module of the high-speed ADC, i.e. the above-mentioned buffer module 6, is usually a pair of pseudo-differential source followers, each of which is connected to two ends of a differential signal, and a common-mode test signal Vic can be injected by capacitive coupling to the gate end of the buffer module 6.

[0076] In the embodiment of the present application, the comparator in the ADC module 3 is split into two parts, i.e. a positive part and a negative part, and each of them quantizes a differential end signal. In the digital domain, the differential input service signal Dsig is obtained by subtraction, and the calibration signal Dcom of the injected test signal Vic is obtained by addition, which can be used for autocorrelation calculation to extract skew information.

[0077] In the embodiment of the present application, the test signal Vic can be a single-tone signal. Since the autocorrelation statistical method has low requirements for the test signal Vic, the test signal Vic can be a single-tone signal with poor linearity, which can be generated by clock source frequency division, and the amplitude can be small, for example, -40 dBFS. Even if a part of the test signal Vic leaks into the differential path due to matching error, it will not significantly deteriorate the performance of the ADC. At the same time, the test signal Vic will not be disturbed by the service signal Dsig, and the algorithm converges quickly.

[0078] In the embodiment of the present application, the common-mode voltage is quantized at the same time, i.e. the test signal Vic is quantized at the same time. Another advantage is that the comparator input common-mode bias can be ensured to be stable when quantizing to the LSB (Least Significant Bit) each time. In some low-voltage and low-power comparator designs, the noise can be optimized.

[0079] In the embodiment of the present application, the differential two ends of the input signal are quantized respectively, which can improve the tolerance to the common-mode voltage of the input signal. Common differential ADCs require that the common-mode voltage of the input differential signal be within a small range to achieve high conversion performance. When the differential two ends are quantized respectively, there is almost no requirement for the common-mode of the input signal. In some specific applications, the design of the previous stage driving circuit can be simplified.

[0080] In the embodiment of the present application, the differential signal input end 1 is connected to the ADC module 3 through the switch 7, and the clock circuit is connected to the switch 7. The transmission of the signal in the first signal channel and the transmission of the signal in the second signal channel in the clock skew error calibration circuit are controlled by the switch 7 controlled by the clock circuit. The above-mentioned clock skew error based on the calibration signal Dcom and the service signal Dsig is generally used to correct the clock circuit, thereby realizing clock skew error calibration.

[0081] The clock offset error calibration circuit provided by the embodiment of the application injects a test signal Vic into the differential signal through a common mode signal channel 2, so that the test signal Vic and the service signal Dsig existing in the differential mode signal channel are completely separated, without interfering with each other and without reducing the range of the ADC. Since the autocorrelation statistics method of the clock offset error has low requirements on the signal amplitude, quantization accuracy and linearity, the test signal Vic injected in the common mode does not need high energy, and the test signal Vic generation circuit can be very simple.

[0082] In the clock offset error calibration circuit, the common mode value of the signal is also sampled at the moment when the differential signal is sampled, so the clock offset error of each channel is the same for the differential signal and the common mode signal, and then the separated differential signal and the common mode signal are quantized based on the ADC module 3, so that the clock offset error information can be extracted by autocorrelation calculation of the test signal Vic in the digital domain, and finally compensated in the clock circuit, to realize accurate calibration of the clock offset error.

[0083] The application further provides an integrated circuit comprising the clock offset error calibration circuit provided by any of the above embodiments. The remaining structure of the integrated circuit can refer to the prior art, and will not be described here.

[0084] Since the clock offset error calibration circuit provided by the above embodiment can accurately and quickly calibrate the clock offset error, the above integrated circuit can have a lower clock offset error or avoid the existence of the clock offset error.

[0085] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts of each embodiment can be referred to each other.

[0086] The skilled person can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in the present text can be realized by electronic hardware, computer software or a combination of both. In order to clearly show the interchangeability of hardware and software, the components and steps of each example have been described in the above description. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0087] The steps of a method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. The

[0088] Finally, it is to be noted that, in the present document, terms such as first and second, etc., are used merely to distinguish one entity or action from another, without necessarily requiring or implying any such actual relationship or order between such entities or actions. Also, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0089] The above provides a clock offset error calibration circuit and integrated circuit. The principles and implementation manners of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A clock offset error calibration circuit, characterized by, The differential signal input end, the common-mode signal channel, the ADC module, the service signal end and the correction signal end are included. The differential signal input end includes a first differential input end and a second differential input end, and the common-mode signal channel is connected with the first differential input end and the second differential input end simultaneously; the differential signal input end is connected with the ADC module, and the service signal end and the correction signal end are connected with the ADC module. The common-mode signal channel is used for inputting test signals to the first differential input end and the second differential input end, the ADC module is used for converting differential signals with the test signals from time domain to digital domain to obtain voltage signals; the service signal end generates service signals based on the voltage signals, and the correction signal end generates correction signals based on the voltage signals to associate the correction signals with the service signals to obtain clock offset errors and correct the clock. The ADC module includes a first ADC unit and a second ADC unit, the first differential input end is connected with the first ADC unit through a first signal channel, and the second differential input end is connected with the second ADC unit through a second signal channel; the service signal end is connected with the first ADC unit and the second ADC unit simultaneously, and the correction signal end is connected with the first ADC unit and the second ADC unit simultaneously. The first ADC unit is used for converting signals in the first signal channel from time domain to digital domain to obtain first voltage signals; the second ADC unit is used for converting signals in the second signal channel from time domain to digital domain to obtain second voltage signals; the service signal end is used for subtracting the first voltage signals from the second voltage signals to obtain service signals, and the correction signal end is used for adding the first voltage signals to the second voltage signals to obtain correction signals to associate the correction signals with the service signals to obtain clock offset errors and correct the clock.

2. The clock offset error calibration circuit of claim 1, wherein, A buffer module is further included, and the differential signal input end is connected with the ADC module through the buffer module.

3. The clock offset error calibration circuit of claim 2, wherein, The buffer module includes a first transistor and a second transistor, the first differential input end is connected with a gate of the first transistor, and a source of the first transistor is connected with the first ADC unit through the first signal channel; The second differential input end is connected with a gate of the second transistor, and a source of the second transistor is connected with the second ADC unit through the second signal channel.

4. The clock offset error calibration circuit of claim 1, wherein, The first ADC unit comprises a first DAC switch, a first SAR logic circuit and a first comparator, the first signal channel connects the first DAC switch with an input end of the first comparator, an output end of the first comparator is connected with the first SAR logic circuit, and the first SAR logic circuit is connected with the first DAC switch; the second ADC unit comprises a second DAC switch, a second SAR logic circuit and a second comparator, the second signal channel connects the second DAC switch with an input end of the second comparator, an output end of the second comparator is connected with the second SAR logic circuit, and the second SAR logic circuit is connected with the second DAC switch. The service signal end is connected with the first SAR logic circuit and the second SAR logic circuit simultaneously, and the correction signal end is connected with the first SAR logic circuit and the second SAR logic circuit simultaneously.

5. The clock offset error calibration circuit of claim 4, wherein, The first comparator and the second comparator are connected with the same reference voltage.

6. The clock offset error calibration circuit of claim 1, wherein, The differential signal input end is connected with the ADC module through a switch, and the switch is connected with a clock circuit, and the clock circuit is subjected to the clock offset error correction.

7. The clock offset error calibration circuit of claim 1, wherein, The test signal is a single tone signal.

8. An integrated circuit, characterized by The clock offset error correction circuit comprises the ADC module. The clock offset error correction circuit comprises the ADC module.

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