An anti-fuse FPGA internal logic on-chip test circuit

Abstract

The present invention discloses an on-chip test circuit for internal logic of an anti-fuse FPGA, belonging to the field of semiconductor integrated circuits. During chip design, the internal sequential logic units and combinational logic units of the chip are integrated and laid out. The main body of the on-chip test circuit for internal logic is "sequential logic unit 1" + "n-2 levels of cascaded combinational logic units" + "sequential logic unit 2". The speed performance of the circuit and internal logic units can be evaluated both in the chip design stage and the test stage. The above-mentioned "n" can be flexibly configured according to the actual circuit scale, so as to meet the evaluation requirements for the speed performance of the internal logic of anti-fuse FPGA chips of different scales. The on-chip test circuit for internal logic of the anti-fuse FPGA provided by the present invention can accurately measure the speed performance of the internal logic units of the circuit in the design stage. After the anti-fuse FPGA is programmed by the user, it can measure the speed performance of the internal sequential logic units and combinational logic units, as well as the impact of the resistance difference after anti-fuse programming on the circuit speed.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and particularly to an on-chip test circuit for internal logic of an antifuse FPGA. Background Art

[0002] In the technical field of semiconductor integrated circuits, FPGAs are widely used because of their high configurability and can be flexibly applied in various complex electronic systems. According to the different structures of programming units, FPGAs are mainly divided into SRAM-based FPGAs, FLASH-based FPGAs, and antifuse FPGAs. Compared with the first two types of FPGAs, the programming units of antifuse FPGAs occupy less area, and the wiring resources are richer under the same area. At the same time, after the antifuse FPGA is programmed, the chip function does not lose power and can continue to work after power-on. Antifuse units are widely used in high-reliability systems because of their high security and extremely high stability after programming.

[0003] The internal part of the antifuse FPGA mainly includes an I / O module, a charge pump module, a power-on module, a combinational logic module, a sequential logic module, etc.; among them, modules such as I / O, charge pump, and power-on can be directly tested during chip detection. However, the combinational logic module and the sequential logic module are inside the circuit and cannot pass the chip-level test speed performance, and only the module-level simulation parameters can be obtained through simulation tools. When designing an antifuse FPGA chip, it is also impossible to intuitively and accurately measure the speed performance of the entire internal logic of the circuit, which will inevitably bring challenges to circuit design and testing.

[0004] Antifuses can be formed into different types of antifuse units according to different process means. Even for the same type of antifuse unit, the resistance of the programmed antifuse unit will be different under different programming currents, programming voltages, and programming times. And even on different antifuse FPGA chips on the same wafer in the same lot, the resistance of the antifuse unit after programming will also be different. When the resistance value of the programmed antifuse unit is large, it will reduce the signal transmission speed, thereby reducing the speed performance of the antifuse FPGA, and seriously, the entire chip function does not meet the user requirements.

[0005] In order to evaluate and detect the speed performance of the internal logic of the antifuse FPGA during the design stage and the chip testing stage, the traditional method is to perform circuit module-level simulation or to additionally design the PCM circuit of the corresponding module for tape-out and then conduct testing. However, this method cannot accurately measure the potential risks existing during chip design. If there are large errors, it will inevitably result in serious economic losses and a longer design cycle. Therefore, a method is needed to accurately measure the speed performance of the internal logic units of the circuit in the antifuse FPGA during the design stage, and during the chip testing stage, to evaluate the speed performance of the internal logic units and test the impact of the resistance value of the antifuse units after programming on the circuit speed performance. Summary of the Invention

[0006] The purpose of the present invention is to provide an on-chip test circuit for the internal logic of an antifuse FPGA to solve the problems in the background technology.

[0007] To solve the above technical problems, the present invention provides an on-chip test circuit for the internal logic of an antifuse FPGA, including a TDI port, a TDO port, two-level timing logic units, n - 2-level combinational logic units, and 3n antifuse units. Among them, the two-level timing logic units are the first-level timing logic unit and the second-level timing logic unit;

[0008] The TDI port is connected to the input end of the first-level timing logic unit, the output end of the first-level timing logic unit is connected to the input end of the first-level combinational logic unit, after the n - 2-level combinational logic units are connected in series, the output end of the last-level combinational logic unit is connected to the input end of the second-level timing logic unit; the output end of the second-level timing logic unit is connected to the TDO port;

[0009] There are 3 different types of antifuse units after any logic unit.

[0010] In an embodiment, the timing logic unit includes NAND gates NAND1 and NAND2, NOR gates NOR1 and NOR2, transmission gates T1 and T2, and inverters INV1 to INV3; among them,

[0011] The input ends of the NAND gate NAND1 are respectively connected to the TDI port and the enable signal OE, and the output is connected to node A1; the input ends of the NOR gate NOR1 are respectively connected to the reset signal RST of the on-chip test circuit of the internal logic and node A1, and the output is connected to node A3;

[0012] The input terminals of the NOR gate NOR2 are respectively connected to node A3 and node A4, and the output is connected to node A5; the input terminal of the inverter INV2 is connected to node A5, and the output is connected to node A2; the input terminal of the transmission gate T1 is node A2, and the output terminal is connected to node A1; the input terminals of the NAND gate NAND2 are connected to node A2 and the reset signal RST of the on-chip test circuit of the internal logic, and the output terminal is connected to node A4;

[0013] The input terminal of the transmission gate T2 is connected to node A5, and the output terminal is connected to node A6; the input terminal of the inverter INV1 is connected to node A6, and the output terminal is connected to the output terminal OUT; the input terminal of the inverter INV3 is connected to the output terminal OUT of the sequential logic unit, and the output terminal is connected to node A6.

[0014] In one embodiment, the inverter INV2, the inverter INV3, the transmission gate T1 and the transmission gate T2 are all controlled by the clock signal CP;

[0015] When the clock signal CP is high, the inverter INV2 and the transmission gate T2 work normally; when the clock signal CP is low, the inverter INV2 and the transmission gate T2 do not work;

[0016] When the clock signal CP is low, the inverter INV3 and the transmission gate T1 work normally; when the clock signal CP is high, the inverter INV3 and the transmission gate T1 do not work.

[0017] In one embodiment, the combinational logic unit includes a NAND gate NAND3, selectors MUX1 and MUX2, and inverters INV4 and INV5; where,

[0018] The input terminals of the NAND gate NAND3 are respectively connected to the output signal of the upper-level logic unit and the enable signal OE of the on-chip test circuit of the internal logic, and the output terminal is connected to node A7;

[0019] The input terminals of the selector MUX1 are connected to the power supply VS, the ground GS and the enable signal OE. When the enable signal OE is high, the combinational logic unit starts to work, and the selector MUX1 inverts and outputs the data of node A7; the output terminal of the selector MUX1 is connected to node A8;

[0020] The input terminals of the selector MUX2 are connected to node A8, the power supply VS and the ground GS, and the output is connected to node A9; the selector MUX2 outputs the data of node A8 in-phase;

[0021] The input terminal of the inverter INV4 is connected to node A9, and the output terminal is connected to node A10;

[0022] The input terminal of the inverter INV5 is connected to node A10, and the output terminal is connected to the output terminal OUT1.

[0023] In one embodiment, the TDI port is the data input port of the on-chip test circuit of the anti-fuse FPGA internal logic chip; the TDO port is the data output port of the on-chip test circuit of the anti-fuse FPGA internal logic chip;

[0024] The enable signal OE controls whether the on-chip test circuit of the anti-fuse FPGA internal logic chip works or not. When the enable signal OE is high, the on-chip test circuit of the anti-fuse FPGA internal logic chip is effectively enabled and the circuit starts to work; when the enable signal OE is low, the on-chip test circuit of the anti-fuse FPGA internal logic chip is disabled and the circuit does not work;

[0025] The reset signal RST controls whether the timing logic unit is reset or not. When the reset signal RST is high and the rising edge of the clock signal CP arrives, the timing logic unit works normally; when the reset signal RST is low and the rising edge of the clock signal CP arrives, the output terminal OUT of the timing logic unit is reset and the on-chip test circuit of the anti-fuse FPGA internal logic chip outputs a high level;

[0026] The clock signal CP is the clock signal of the on-chip test circuit of the anti-fuse FPGA internal logic chip. When the enable signal OE is high, the reset signal RST is high, and the falling edge of the clock signal CP arrives, the timing logic unit acquires data; when the rising edge of the clock signal CP arrives, the timing logic unit outputs data.

[0027] In one embodiment, the physical positions of the 3 different types of anti-fuse units in the circuit layout are non-continuous, and the layout satisfies the wiring transmission delay of the entire circuit.

[0028] In a test circuit on the internal logic chip of an anti-fuse FPGA provided by the present invention, it includes a TDI port, a TDO port, two-level timing logic units, n - 2 - level combinational logic units, and 3n anti-fuse units. Among them, the two-level timing logic units are the first-level timing logic unit and the second-level timing logic unit; the TDI port is connected to the input end of the first-level timing logic unit, the output end of the first-level timing logic unit is connected to the input end of the first-level combinational logic unit, after the n - 2 - level combinational logic units are connected in series, the output end of the last-level combinational logic unit is connected to the input end of the second-level timing logic unit; the output end of the second-level timing logic unit is connected to the TDO port; there are 3 anti-fuse units of different types after any logic unit. The speed performance of the circuit and internal logic units can be evaluated both in the chip design stage and the test stage. The above "n" can be flexibly configured according to the actual circuit scale, so as to meet the evaluation requirements of the internal logic speed performance of anti-fuse FPGA chips of different scales. The test circuit on the internal logic chip of the anti-fuse FPGA provided by the present invention can accurately measure the speed performance of the internal logic units of the circuit in the design stage. After the anti-fuse FPGA is programmed by users, it can measure the speed performance of the internal timing logic units and combinational logic units, as well as the impact of the resistance difference after anti-fuse programming on the circuit speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 FIG. is a schematic structural diagram of a test circuit on the internal logic chip of an anti-fuse FPGA provided by the present invention.

[0030] Figure 2 FIG. is a schematic structural diagram of a timing logic unit.

[0031] Figure 3 FIG. is a schematic structural diagram of a combinational logic unit.

[0032] Figure 4 FIG. is a schematic diagram of the internal layout of the chip where the test circuit on the internal logic chip of the anti-fuse FPGA is located. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] The following further details a test circuit on the internal logic chip of an anti-fuse FPGA proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention.

[0034] The present invention provides a test circuit on the internal logic chip of an anti-fuse FPGA, and its structure is as Figure 1As shown, it includes a TDI port and a TDO port, a two-stage timing logic unit (i.e., timing logic unit 1 and timing logic unit 2), an n - 2-stage combinational logic unit (i.e., combinational logic unit 1, combinational logic unit 2,..., combinational logic unit n - 2), and 3n anti-fuse units, where n = 48, that is, a two-stage timing logic unit, a 46-stage combinational logic unit, and 144 anti-fuse units. The TDI port is connected to the input terminal D of the first-stage timing logic unit (i.e., timing logic unit 1), and the output terminal OUT of the first-stage timing logic unit is connected to the input terminal D1 of the next-stage combinational logic unit (i.e., combinational logic unit 1); after the 46 combinational logic units are connected in series, the output terminal OUT of the last-stage combinational logic unit (i.e., combinational logic unit 46) is connected to the input terminal D of the second-stage timing logic unit (i.e., timing logic unit 2); the output terminal OUT of the second-stage timing logic unit is connected to the TDO port; and there are 3 anti-fuse units of different types after any logic unit (i.e., any timing logic unit and any combinational logic unit), forming an on-chip test circuit for the internal logic of the anti-fuse FPGA.

[0035] The test enable signal OE is connected to the enable terminals OE of the 2 timing logic units and the 46 combinational logic units to control whether the on-chip test circuit for the internal logic of the anti-fuse FPGA works. When the test enable signal OE is high, the enable signal OE is valid, and the on-chip test circuit for the internal logic of the anti-fuse FPGA starts to work; when the test enable signal OE is low, the enable signal OE is invalid, and the on-chip test circuit for the internal logic of the fuse FPGA stops working; the reset signal RST is connected to the 2 timing logic units to control the reset of the timing logic units. When the reset signal RST is high and the rising edge of the clock signal CP arrives, the timing logic units work normally and the circuit works normally; when the reset signal RST is low and the rising edge of the clock signal CP arrives, the output terminal OUT of the timing logic units is reset, and the on-chip test circuit for the internal logic of the anti-fuse FPGA outputs a high level.

[0036] The circuit structure of the timing logic unit is as Figure 2As shown, it includes NAND gates NAND1 and NAND2, NOR gates NOR1 and NOR2, transmission gates T1 and T2, and inverters INV1 to INV3. The signal of the TDI port comes from the transmission signal of the chip I / O port, and the enable signal OE is configured by the internal state machine and instruction decoder of the circuit. The inputs of the NAND gate NAND1 are respectively connected to the TDI port of the on-chip test circuit of the internal logic and the enable signal OE, and the output is connected to node A1; the inputs of the NOR gate NOR1 are respectively connected to the reset signal RST of the on-chip test circuit of the internal logic and node A1, and the output is connected to node A3; the inputs of the NOR gate NOR2 are respectively connected to node A3 and node A4, and the output is connected to node A5; the input of the inverter INV2 is connected to node A5, and the output is connected to node A2; the clock signal CP is the control signal of the inverter INV2. When the clock signal CP is high, the inverter INV2 works normally; when the clock signal CP is low, the inverter INV2 does not work; the input of the transmission gate T1 is node A2, and the output is node A1; when the clock signal CP is low, the transmission gate T1 works; when the clock signal CP is high, the transmission gate T1 does not work. The inputs of the NAND gate NAND2 are respectively connected to node A2 and the reset signal RST of the on-chip test circuit of the internal logic, and the output is connected to node A4; nodes A5, A2, and A4 form a feedback loop; the input of the transmission gate T2 is connected to node A5, and the output is connected to node A6; when the clock signal CP is high, the transmission gate T2 works; when the clock signal CP is low, the transmission gate T2 does not work; the input end of the inverter INV3 is connected to the output end OUT of the sequential logic unit, and the clock signal CP is the control signal of the inverter INV3. When the clock signal CP is low, the inverter INV3 works normally; when the clock signal CP is high, the inverter INV3 does not work, and the output end of the inverter INV3 is connected to node A6; the input of the inverter INV1 is connected to node A6, and the output is connected to the output end OUT;

[0037] The circuit structure of the combinational logic unit is as Figure 3 shown, and it includes a NAND gate NAND3, multiplexers MUX1 and MUX2, and inverters INV4 and INV5. The inputs of the NAND gate NAND3 are respectively connected to the output signal of the previous-level logic unit and the enable signal OE of the on-chip test circuit of the internal logic, and the output end is connected to node A7. When the enable signal OE is high, the combinational logic unit starts to work. The inputs of the multiplexer MUX1 are respectively connected to the power supply VS and the ground GS, and the output is connected to node A8. The power supply VS and the ground GS are two fixed and connected selection signals of the multiplexer MUX1 (in fact, the combinational logic unit of the anti-fuse FPGA has 8 configurable input signals, Figure 2(only the simplified structure is shown), which is used to invert and output the D1 signal. The inputs of the selector MUX2 are respectively connected to node A8 and ground GS, and the output is connected to node A9. The power supply VS and ground GS are two fixed selection signals of the selector MUX2, which are used to output the signal of node A8 without loss and in the same phase. The input of the inverter INV4 is connected to node A9, and the output is connected to node A10; the input of the inverter INV5 is connected to node A10, and the output is connected to the output terminal OUT.

[0038] Please continue to refer to Figure 1 , three different types of antifuse cells will be programmed after any logic unit, and the physical positions of these 3 antifuse cells are non - continuous in the circuit layout, maximizing the requirements of the analog antifuse cell programming algorithm. By applying different intensities of programming stress (programming voltage, programming current, programming time, etc.) to program the antifuse cells, different resistance values of the programmed antifuse cells can be achieved, and then the influence of the antifuse cells with different resistance values on the circuit speed performance can be tested.

[0039] The internal logic on - chip test circuit chip internal layout is shown as Figure 4 shown. The antifuse FPGA internal logic on - chip test circuit composed of the 2 sequential logic units and 46 combinational logic units runs longitudinally through the entire chip in the layout, aiming to meet the requirement of the longest longitudinal transmission distance of the chip, maximizing the simulated wiring transmission delay, and visually verifying the speed performance of the internal logic units that are difficult to directly test at the chip level and the influence of the resistance difference of the antifuse units after programming on the circuit speed.

[0040] The antifuse FPGA internal logic on - chip test circuit provided by the present invention can start the internal logic on - chip test circuit according to the configuration method during the chip design stage, while setting the enable signal OE to high level and the reset signal RST to high level, and simulate - programming 144 antifuse units to verify the chip.

[0041] Design the overall speed performance of the internal sequential logic units and combinational logic units during the design stage. During the chip test stage, according to the developed test code and special programmer, truly program the 144 fuses of the chip internal logic on - chip test circuit, and monitor the speed performance of the programmed internal logic on - chip test circuit. Thus, the internal logic units can be evaluated during the chip design stage; during the chip test stage, evaluate the influence of the speed performance of the internal logic units of the circuit and the resistance value of the antifuse units after programming on the circuit speed.

[0042] In summary, the on-chip test circuit for internal logic of the anti-fuse FPGA provided by the present invention can evaluate the internal logic units during the chip design stage, and evaluate the influence of the resistance value of the internal logic unit circuit and the anti-fuse unit on the circuit speed after programming during the chip test stage. It can ensure the speed performance and stability of the relevant internal logic of the product, monitor whether the circuit meets the chip design specifications, and greatly improve the probability of successful design at one time.

[0043] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the field of the present invention according to the above disclosure are within the scope of protection of the claims.

Claims

1. An anti-fuse FPGA internal logic on-chip test circuit, characterized in that It includes a TDI port, a TDO port, a two-stage timing logic unit, an n - 2-stage combinational logic unit, and 3n antifuse units, where the two-stage timing logic unit is a first-stage timing logic unit and a second-stage timing logic unit; The TDI port is connected to the input end of the first-stage timing logic unit, the output end of the first-stage timing logic unit is connected to the input end of the first-stage combinational logic unit. After the n - 2-stage combinational logic units are connected in series, the output end of the last-stage combinational logic unit is connected to the input end of the second-stage timing logic unit; the output end of the second-stage timing logic unit is connected to the TDO port; There are 3 different types of antifuse units after any logic unit; The timing logic unit includes NAND gates NAND1 and NAND2, NOR gates NOR1 and NOR2, transmission gates T1 and T2, and inverters INV1~INV3; among them, The input ends of the NAND gate NAND1 are respectively connected to the TDI port and the enable signal OE, and the output is connected to node A1; the input ends of the NOR gate NOR1 are respectively connected to the reset signal RST of the on-chip test circuit of the internal logic and node A1, and the output is connected to node A3; The input ends of the NOR gate NOR2 are respectively connected to node A3 and node A4, and the output is connected to node A5; the input end of the inverter INV2 is connected to node A5, and the output is connected to node A2; the input end of the transmission gate T1 is node A2, and the output end is connected to node A1; the input ends of the NAND gate NAND2 are connected to node A2 and the reset signal RST of the on-chip test circuit of the internal logic, and the output end is connected to node A4; The input end of the transmission gate T2 is connected to node A5, and the output end is connected to node A6; the input end of the inverter INV1 is connected to node A6, and the output end is connected to the output end OUT; the input end of the inverter INV3 is connected to the output end OUT of the timing logic unit, and the output end is connected to node A6.

2. The anti-fuse FPGA internal logic on-chip test circuit according to claim 1, characterized in that, The inverter INV2, the inverter INV3, the transmission gate T1, and the transmission gate T2 are all controlled by the clock signal CP; When the clock signal CP is high, the inverter INV2 and the transmission gate T2 work normally; when the clock signal CP is low, the inverter INV2 and the transmission gate T2 do not work; When the clock signal CP is low, the inverter INV3 and the transmission gate T1 work normally; when the clock signal CP is high, the inverter INV3 and the transmission gate T1 do not work.

3. The anti-fuse FPGA internal logic on-chip test circuit according to claim 2, wherein The combinational logic unit includes a NAND gate NAND3, selectors MUX1 and MUX2, and inverters INV4 and INV5; among them, The input ends of the NAND gate NAND3 are respectively connected to the output signal of the upper-level logic unit and the enable signal OE of the on-chip test circuit of the internal logic, and the output end is connected to node A7; The input ends of the selector MUX1 are connected to the power supply VS, the ground GS, and the enable signal OE. When the enable signal OE is high, the combinational logic unit starts to work, and the selector MUX1 inverts and outputs the data of node A7; the output end of the selector MUX1 is connected to node A8; The input terminals of the selector MUX2 are connected to node A8, power supply VS, and ground GS, and the output is connected to node A9; the selector MUX2 outputs the data of node A8 in phase; The input terminal of the inverter INV4 is connected to node A9, and the output terminal is connected to node A10; The input terminal of the inverter INV5 is connected to node A10, and the output terminal is connected to output terminal OUT1.

4. The anti-fuse FPGA internal logic chip-on test circuit according to claim 3, characterized in that The TDI port is the data input port of the on-chip test circuit of the antifuse FPGA internal logic; the TDO port is the data output port of the on-chip test circuit of the antifuse FPGA internal logic; The enable signal OE controls the operation of the on-chip test circuit of the antifuse FPGA internal logic. When the enable signal OE is high, the on-chip test circuit of the antifuse FPGA internal logic is effectively enabled and the circuit starts to work; when the enable signal OE is low, the on-chip test circuit of the antifuse FPGA internal logic is disabled and the circuit does not work; The reset signal RST controls the reset of the timing logic unit. When the reset signal RST is high, at the rising edge of the clock signal CP, the timing logic unit works normally; when the reset signal RST is low, at the rising edge of the clock signal CP, the output terminal OUT of the timing logic unit is reset, and the on-chip test circuit of the antifuse FPGA internal logic outputs a high level; The clock signal CP is the clock signal of the on-chip test circuit of the antifuse FPGA internal logic. When the enable signal OE is high, the reset signal RST is high, and at the falling edge of the clock signal CP, the timing logic unit acquires data; at the rising edge of the clock signal CP, the timing logic unit outputs data.

5. The anti-fuse FPGA internal logic chip-on test circuit according to claim 1, characterized in that The physical positions of the 3 different types of antifuse units are non - continuous in the circuit layout, and the layout satisfies the wiring transmission delay of the entire circuit.

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