Fast response LDO circuit with multiple protection functions

Abstract

The application relates to an LDO circuit for an AC-DC power supply controller module in a power electronic system, comprising a band-gap reference circuit, a dynamic bias error amplifier, a dynamic bias control circuit, a bias circuit, a multiple protection circuit and a power tube, a feedback resistor R1 and a feedback resistor R2. In addition to a fixed bias current I B , the bias current of the dynamic bias error amplifier also has an additional dynamic bias current I AB . The dynamic bias control circuit detects the load current change and generates a bias control signal V ctrl to control the dynamic bias current I AB for changing the bias current of the dynamic bias error amplifier and changing the transient response speed. On the basis of the prior art, the application first adopts the dynamic bias technology to increase the bias current under heavy load and improve the response speed of the LDO circuit; in addition, the multiple protection circuit is adopted to increase the reliability of the LDO circuit.

Description

Technical Field

[0001] This invention relates to an LDO circuit for an AC-DC power controller module in a power electronic system, belonging to the field of integrated circuit technology. Background Technology

[0002] The development of the semiconductor industry has enabled the rapid growth of many emerging application areas, such as communications, smart home appliances, the Internet of Things (IoT), and portable electronic devices. These markets are also experiencing a surge in demand for power supply chips. Power supply chips are mainly divided into linear regulators and switching power converters. Most electronic products cannot be directly powered by AC power and require AC-DC conversion. However, current AC-DC converters often struggle to provide stable outputs, necessitating a voltage converter. Common voltage converters include low-dropout linear regulators (LDOs) and inductor-based DC-DC converters. Compared to DC-DC converters, LDOs offer advantages such as simpler structure, lower power consumption, lower high-frequency noise, and smaller size for easier integration. However, because LDOs can only step down the input voltage, while DC-DC converters can boost, buck, or invert the input voltage, the input / output voltage range of LDOs is somewhat limited compared to DC-DC converters. Furthermore, the voltage drop of the power transistor in a DC-DC converter is typically 10mV to 100mV, while that in an LDO is typically between 200mV and 600mV. This results in the lower conversion efficiency of the LDO compared to the DC-DC converter. Analog circuits are inherently more sensitive to power supply noise than digital circuits. Therefore, circuit modules with analog functions cannot tolerate switching noise and require low-noise, low-power, and low-cost LDOs for power. Consequently, LDOs, with their unique advantages, are widely used in applications requiring high noise sensitivity and voltage accuracy.

[0003] like Figure 1 As shown, a basic LDO has three pins, namely the input voltage V. IN (VDD), Output Voltage V OUT The LDO's submodules mainly include a reference circuit, an error amplifier, a power transistor (MP), and a feedback loop compensation circuit. The reference circuit provides a reference voltage V for the error amplifier and auxiliary circuits. REF and reference current I REFThe reference circuit comprises two modules: a current reference circuit and a voltage reference circuit. The current reference circuit generates a reference current unaffected by the supply voltage. The voltage reference circuit obtains a temperature-independent reference voltage by weighted summing the emitter-base voltage of a PNP transistor with a negative temperature coefficient and a thermal voltage with a positive temperature coefficient. An error amplifier amplifies the difference between the bandgap reference voltage and the LDO feedback voltage and inputs it to the gate of the power transistor to control the output voltage. The accuracy, transient response, and load current of the LDO's output voltage are directly affected by the error amplifier. When the load changes, the power transistor MP stabilizes the output voltage by changing its on-resistance. The feedback loop compensation circuit, including a resistor string and a compensation network, provides output voltage control and feedback network stability.

[0004] Traditional LDOs without external large capacitors suffer from system stability and transient response issues. First, without the left-half-plane zero formed by the external large capacitor and its equivalent series resistance, frequency compensation becomes more complex, necessitating the exploration of frequency compensation schemes for LDOs without external capacitors. Second, the system's transient response also changes. Without the external large capacitor, when the load current suddenly changes, the system struggles to provide or store additional current, forced to wait for the loop itself to respond to the load. This results in a larger undershoot voltage and a longer recovery time at the LDO's output. As the requirements for LDO chip load transient response performance increase, the LDO must recover within a very short time to meet the demands of high-frequency loads when the load changes suddenly. Because LDO circuits provide large currents, they must possess very high safety features. Abnormal internal temperature, current, and output voltage can cause irreversible damage to the chip, thus requiring various protection mechanisms. Summary of the Invention

[0005] Based on existing technology, this invention provides a transient-enhanced fast-response LDO circuit with multiple protection functions.

[0006] The overall structure of the fast-response LDO circuit with multiple protection functions provided by the present invention includes: a bandgap reference circuit, a dynamic bias error amplifier, a dynamic bias control circuit, a bias circuit, a multiple protection circuit, a power transistor Mn, a feedback resistor R1, and a feedback resistor R2.

[0007] The bandgap reference circuit generates a reference voltage V. REF The reference voltage Vr1 and the reference current Irb, where the reference voltage Vr1 is... REFThe reference voltage Vr1 is connected to the positive terminal of the dynamic bias error amplifier, the reference voltage Vr1 is connected to the dynamic bias control circuit and the multiple protection circuit, and the reference current Irb is connected to the bias circuit; the bias circuit is based on the reference current Irb generated by the bandgap reference circuit and the bias control signal Vr1 output by the dynamic bias control circuit. ctrl Generate bias current I B and bias current I AB The circuit is connected to a dynamic bias error amplifier; the negative terminal of the dynamic bias error amplifier is connected to the lower end of the feedback resistor R1, and the output terminal of the dynamic bias error amplifier is connected to the gate of the power transistor Mn and the control signal input terminal of the dynamic bias control circuit; the drain of the power transistor Mn is connected to the power supply voltage VDD, and the source of the power transistor Mn is connected to the upper end of the feedback resistor R1, serving as the output port Vout of the overall LDO circuit; the lower end of the feedback resistor R1 is connected to the upper end of the feedback resistor R2, serving as the generation node of the feedback voltage Vfb; the lower end of the feedback resistor R2 is connected to the ground voltage VSS; the dynamic bias error amplifier is based on the reference voltage V REF Bias current I B Bias current I AB And the feedback voltage Vfb, generate the error amplification signal V EA The dynamic bias control circuit controls the bias based on the error amplification signal V. EA The bias control signal V is generated with the reference voltage Vr1. ctrl It is connected to the bias circuit; the multiple protection circuit detects the chip status and compares it with the reference voltage Vr1, and outputs the chip status monitoring signal Error.

[0008] The bias current of the dynamic bias error amplifier, in addition to a fixed bias current I, is... B In addition, there is an extra dynamic bias current I AB The dynamic bias control circuit will detect changes in load current and generate a bias control signal V. ctrl To control the dynamic bias current I AB This is used to change the bias current of the dynamic bias error amplifier, thereby altering its transient response speed.

[0009] Specifically, the dynamic bias control circuit includes: a load detection circuit consisting of a current sensing transistor Ms and a resistor Rs, and a fast-response voltage comparator Comp. The gate of the current sensing transistor Ms is connected to the error amplification signal V. EA The drain of the current sensing transistor Ms is connected to the power supply voltage VDD, and the source of the current sensing transistor Ms is connected to the upper end of the resistor Rs and the positive terminal of the fast response voltage comparator Comp. The output signal V Rs The lower end of resistor Rs is connected to ground voltage VSS; the negative terminal of fast response voltage comparator Comp is connected to reference voltage Vr1, and fast response voltage comparator Comp outputs bias control signal V. ctrlWhen the load current suddenly increases, the output voltage V of the overall LDO circuit... out The current will suddenly drop, and the load detection circuit consisting of the current sensing tube Ms and the resistor Rs will detect this abnormal fluctuation. This fluctuation signal V Rs The bias control signal V is obtained by comparing the fast-response voltage comparator Comp with the reference voltage Vr1. ctrl .

[0010] Specifically, the bias circuit includes: a set of switch-controlled bias current source arrays, wherein there are K dynamic current sources M1 to MK, where K is any positive integer, and the drain of each dynamic current source M1 to MK is connected to the bias current I through a switch. AB The output port of each switch is connected to the output of the buffer and controlled by the control signal S. The input of the buffer is connected to the bias control signal V. ctrl The buffer outputs a control signal S; the bias circuit also includes an input current source M0 and a fixed bias current source Mb. The gate and drain of the input current source M0 are connected to a reference current Irb. The gate of the input current source M0 generates a gate bias voltage Vb, which is simultaneously connected to the gates of K dynamic current sources M1 to MK and the gate of the fixed bias current source Mb; the drain of the fixed bias current source Mb serves as the fixed bias current Irb. B The output port; the source of the input current source M0, the sources of the K dynamic current sources M1 to MK, and the source of the fixed bias current source Mb are all grounded.

[0011] Specifically, the bandgap reference circuit includes: PMOS transistors Mr1 and Mr2, resistors Rr1, Rr2, Rr3, Rr4, and Rr5, diodes D1 and D2, operational amplifier A1, a bias startup circuit, and a bias current output circuit. Among these, PMOS transistors Mr1 and Mr2, resistors Rr1, Rr2, and Rr3, diodes D1 and D2, and operational amplifier A1 constitute a bandgap voltage generation core circuit. The gates of PMOS transistors Mr1 and Mr2 are respectively connected to the bias voltage output terminal of the bias startup circuit. The source of PMOS transistor Mr1 is connected to the power supply VDD, the drain of PMOS transistor Mr1 is connected to the source of PMOS transistor Mr2, and the drain of PMOS transistor Mr2 is connected to resistor R. The upper ends of resistors R1 and Rr2 are connected to output a bandgap voltage. The lower end of resistor Rr1 is connected to the positive terminal of operational amplifier A1 and the anode of diode D1, while the lower end of resistor Rr2 is connected to the negative terminal of operational amplifier A1 and the anode of diode D2. The output terminal of operational amplifier A1 is connected to the gate of PMOS transistor Mr1. ​​The bandgap voltage output from the source of PMOS transistor Mr2 is connected to the upper end of resistor Rr5, and the lower end of resistor Rr5 is grounded through resistor Rr4, outputting a reference voltage Vr1. The two bias voltage output terminals of the bias startup circuit are also connected to the input terminals of the bias current output circuit. The input bias voltage of the bandgap voltage generation core circuit is the gate voltage Vb1 of PMOS transistor Mr1 and the gate voltage Vb2 of PMOS transistor Mr2. The output bandgap voltage of the bandgap voltage generation core circuit is the reference voltage Vr1. REF Reference voltage V REF The reference voltage Vr1 is generated by voltage division through resistors Rr4 and Rr5. The bias startup circuit has a power-on startup function. During the power-on process, it first provides initial bias voltages Vb1 and Vb2 to control the gates of PMOS transistors Mr1 and Mr2, respectively. After power-on, the bias current output circuit generates a reference current Irb based on the bias voltages Vb1 and Vb2 and outputs it to the bias circuit.

[0012] Specifically, the bias startup circuit includes: PMOS transistors M71, M72, M73, M74, M75, M76, M77, M78, M79, M710, M711, M712, M713, M714, and M715; the gate of PMOS transistor M71 is connected to the drain of PMOS transistor M71, the drain of NMOS transistor M72, the drain of NMOS transistor M73, and NMOS transistor M74. The gates of MOSFET M74 and PMOS transistor M75 are connected. NMOS transistors M74, M75, M76, M77, M78, and M79 form a three-stage cascaded inverter chain. The drain of PMOS transistor M75 is connected to the drain of NMOS transistor M74, the gate of PMOS transistor M76, and the gate of NMOS transistor M77. The drain of PMOS transistor M76 is connected to the drain of NMOS transistor M77, the gate of PMOS transistor M78, and the gate of NMOS transistor M79. The drain of PMOS transistor M78 is connected to the drain of NMOS transistor M79, serving as the inverter. The output of the inverter chain is connected to the gates of NMOS transistors M72, M73, M711, M712, M713, and M714. The input of the inverter chain is the gate of PMOS transistor M71. The drain of NMOS transistor M711 is connected to the drain and gate of PMOS transistors M710 and serves as the output of the bias voltage Vb1. The source of NMOS transistor M711 is connected to the drain of NMOS transistor M712. The drain of NMOS transistor M714 is connected to the drain of PMOS transistor M715. The gate of PMOS transistor M715 is connected to the output terminal of bias voltage Vb2, and the source of NMOS transistor M714 is connected to the drain of NMOS transistor M713. The sources of PMOS transistors M71, M75, M76, M78, M710, and M715 are all connected to the power supply voltage VDD. The sources of NMOS transistors M72, M73, M74, M77, M79, M712, and M713 are all connected to the ground voltage VSS.

[0013] Specifically, the multi-protection circuit includes: a temperature detection circuit, a current detection circuit, a first voltage detection circuit, and a second voltage detection circuit; the input terminal of the temperature detection circuit is connected to a first clamping circuit, which generates a bias voltage VbT based on the state of the temperature lockout signal OTLock and outputs it to the temperature detection circuit, which outputs a temperature detection signal VinT; the input terminal of the current detection circuit is connected to a second clamping circuit, which generates a bias voltage VbC based on the state of the overcurrent lockout signal OCLock and outputs it to the current detection circuit, which outputs a current detection output signal VinC; the input terminal of the first voltage detection circuit is connected to a third clamping circuit, which generates a bias voltage VbL based on the state of the undervoltage lockout signal UVLock and outputs it to the first voltage detection circuit, which outputs an undervoltage detection output signal VinL; the input terminal of the second voltage detection circuit is connected to a fourth clamping circuit, which generates a bias voltage VbH based on the state of the overvoltage lockout signal OVLock and outputs it to the second voltage detection circuit, which outputs an overvoltage detection output signal VinH.

[0014] The temperature detection output signal VinT, current detection output signal VinC, undervoltage detection output signal VinL, and overvoltage detection output signal VinH are simultaneously connected to the detection input switch selection circuit. Selected by the switch selection control signal Selp, the switch selection circuit outputs a detection signal Vind, which is connected to a high-precision comparator. The high-precision comparator compares the detection signal Vind with an internal reference signal and outputs a comparison output signal VoT, which is connected to a shaping buffer circuit. The shaping buffer circuit processes the comparison output signal VoT to obtain a protection signal OP and a protection lockout signal OPL, which are then connected to the detection output switch selection circuit. The detection output switch selection circuit has four sets of output terminals, each connected to the error handling logic: one set of over-temperature protection signal OTP and temperature lockout signal OTLock; one set of overcurrent protection signal OCP and overcurrent lockout signal OCLock; one set of undervoltage protection signal UVLO and undervoltage lockout signal UVLock; and one set of overvoltage protection signal OVP and overvoltage lockout signal OVLock. The detection output switch selection circuit, via the switch selection control signal Selp, selects one set of outputs to the error handling logic, which generates an error signal Error.

[0015] The detection input switch selection circuit and the detection output switch selection circuit adopt a 4-to-1 data selector. The switch selection control signal Selp has 4 switch states. In state one, the temperature detection output signal VinT is selected and connected to the detection signal Vind. The protection signal OP and the protection lockout signal OPL are selected and connected to the output terminals of the over-temperature protection signal OTP and the temperature lockout signal OTLock, respectively.

[0016] In state two, the current detection output signal VinC is strobed and connected to the detection signal Vind, and the protection signal OP and the protection lockout signal OPL are strobed and connected to the output terminals of the overcurrent protection signal OCP and the overcurrent lockout signal OCLock, respectively.

[0017] In state three, the undervoltage detection output signal VinL is strobed and connected to the detection signal Vind, and the protection signal OP and the protection lockout signal OPL are strobed and connected to the output terminals of the undervoltage protection signal UVLO and the undervoltage lockout signal UVLock, respectively.

[0018] In state four, the overvoltage detection output signal VinH is strobed and connected to the detection signal Vind, and the protection signal OP and the protection lockout signal OPL are strobed and connected to the output terminals of the overvoltage protection signal OVP and the overvoltage lockout signal OVLock, respectively.

[0019] The switch selection control signal Selp is generated by the OSC oscillator circuit and the timer circuit. The OSC oscillator circuit first generates a high-frequency clock, which is connected to the timer circuit. The timer circuit 98 generates the switch selection control signal Selp, which is then connected to the input switch selection circuit and the output switch selection circuit.

[0020] Specifically, the high-precision comparator includes: PMOS transistors M121, M122, M123, M124, M125, M126, M127, M128, M129, M1210, M1211, M1212, M1213, M1214, and M1215, resistor R121, and capacitor C121; wherein, the gate of PMOS transistor M121 is connected to a bias voltage, and PMOS transistor M121... 1. Drain connection to NMOS transistors M122, M122, M123, M128, and M129; Drain connection to NMOS transistors M123 to PMOS transistors M124, M124, and M125; Drain connection to PMOS transistors M125 to PMOS transistors M126 and M127; Gate connection to the high-precision comparator; Gate connection to PMOS transistor M127, the comparator voltage input, connected to Vind; Drain connection to PMOS transistor M126. Connect the drain of NMOS transistor M129 to the gate of NMOS transistor M1210; connect the drain of PMOS transistor M127 to the drain of NMOS transistor M128 and the gate of NMOS transistor M1214; connect the drain of PMOS transistor M1211 to the drain of NMOS transistor M1210 and the gate of PMOS transistor M1212; connect the drain of PMOS transistor M1212 to the gate of PMOS transistor M1211, the drain of NMOS transistor M1214, the gate of PMOS transistor M1213, and the gate of NMOS transistor M1215; connect the drain of PMOS transistor M1213 to the drain of NMOS transistor M1215, the upper end of resistor R121, and capacitor C121. The upper end serves as the signal Vo output terminal; the sources of NMOS transistors M122, M123, M128, M129, M1210, M1214, and M1215, the lower end of resistor R121, and the lower end of capacitor C121 are all connected to ground voltage VSS; the sources of PMOS transistors M121, M124, M125, M1211, M1212, and M1213 are all connected to power supply voltage VDD.

[0021] The advantages of this invention are: The fast-response LDO circuit with multiple protection functions provided by this invention, based on the prior art, firstly adopts dynamic bias technology to increase the bias current under heavy load, thereby improving the response speed of the LDO circuit; secondly, it adopts multiple protection circuits to increase the reliability of the LDO circuit. Attached Figure Description

[0022] Figure 1 This is a block diagram of a typical LDO circuit in the prior art.

[0023] Figure 2 This is a block diagram of the overall structure of the LDO circuit of the present invention.

[0024] Figure 3 This is one embodiment of the dynamic bias control circuit of the present invention.

[0025] Figure 4 This is one embodiment of the bias circuit of the present invention.

[0026] Figure 5 This is one embodiment of the dynamic bias error amplifier circuit of the present invention.

[0027] Figure 6 This is one embodiment of the bandgap reference circuit of the present invention.

[0028] Figure 7 for Figure 6 Schematic diagram of the mid-biased startup circuit.

[0029] Figure 8 for Figure 7 Power-on startup simulation waveform of the bias startup circuit.

[0030] Figure 9 This is a structural block diagram of one embodiment of the multiple protection circuit of the present invention.

[0031] Figure 10 for Figure 9 An embodiment of a mid-clamping circuit.

[0032] Figure 11 for Figure 9 An embodiment of a medium-to-high precision comparator.

[0033] Figure 12 for Figure 9 An embodiment of a shaping buffer circuit.

[0034] Figure 13 for Figure 9 A circuit example of error handling logic. Detailed Implementation

[0035] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0036] like Figure 2As shown, the fast-response LDO circuit with multiple protection functions described in this invention includes: a bandgap reference circuit 1, a dynamic bias error amplifier 2, a power transistor Mn, a feedback resistor R1, a feedback resistor R2, a dynamic bias control circuit 3, a bias circuit 4, and a multiple protection circuit 5.

[0037] The bandgap reference circuit 1 generates a reference voltage V. REF Reference voltage Vr1 and reference current Irb; Reference voltage V REF The reference voltage Vr1 is connected to the positive terminal of the dynamic bias error amplifier 2, the reference voltage Irb is connected to the dynamic bias control circuit 3 and the multiple protection circuit 5, and the reference current Irb is connected to the bias circuit 4. The bias circuit 4 operates based on the reference current Irb generated by the bandgap reference circuit 1 and the bias control signal Vr1 output by the dynamic bias control circuit 3. ctrl Generate bias current I B and bias current I AB ; connected to dynamic bias error amplifier 2. The dynamic bias error amplifier 2 is based on a reference voltage V. REF Bias current I B Bias current I AB And the feedback voltage Vfb, generate the error amplification signal V EA It is connected to the gate of the power transistor Mn and the control signal input terminal of the dynamic bias control circuit 3; the dynamic bias control circuit 3 controls the signal based on the error amplification signal V. EA The reference voltage Vr1 generates a bias control signal Vctrl, which is connected to bias circuit 4. The drain of power transistor Mn is connected to the power supply voltage VDD, and the source of power transistor Mn is connected to the upper end of feedback resistor R1, serving as the output port Vout of the LDO. The lower end of feedback resistor R1 is connected to the upper end of feedback resistor R2, serving as the generation node for feedback voltage Vfb, and connected to the negative terminal of dynamic bias error amplifier 2. The lower end of feedback resistor R2 is connected to ground voltage VSS. The multi-protection circuit 5 detects the chip status and compares it with the reference voltage Vr1 to obtain the chip status monitoring signal Error.

[0038] Figure 2 In the circuit shown, the resistor string formed by feedback resistors R1 and R2 detects the LDO output voltage and feeds it back to the input of the dynamic bias error amplifier 2, which is related to the input reference voltage V. REF Perform error comparison and lock the adjusting tube M. n The gate voltage forms the stable output voltage V of the LDO. out Unlike ordinary LDO circuits, the error amplifier E of this invention... A Employing a dynamic bias structure, the error amplifier has a fixed bias current I. B In addition, there is an extra dynamic bias current I ABThe dynamic bias control circuit 3 will detect changes in load current and generate a dynamic bias current I. AB The LDO is used to change the bias current of the error amplifier, thereby altering its transient response speed. When the load current suddenly increases, the LDO's output voltage V... out The voltage will suddenly drop, adjusting transistor M. n The gate voltage will also fluctuate abnormally. The dynamic bias control circuit 3 will detect this abnormal fluctuation and control the dynamic bias generation circuit to generate a dynamic bias current I. AB The total bias current of the error amplifier increases, thereby widening the bandwidth, V out The response time is reduced, and the transient response is enhanced.

[0039] Figure 3 This is an embodiment of the dynamic bias control circuit 3 of the present invention, wherein the dashed box represents the bias current source array 41 in the bias circuit 4. The dynamic bias control circuit 3 includes a load detection circuit composed of a current sensing transistor Ms and a resistor Rs, and a fast-response voltage comparator Comp. The gate of the current sensing transistor Ms is connected to the error amplification signal V. EA The drain of the current sensing transistor Ms is connected to the power supply voltage VDD, and the source of the current sensing transistor Ms is connected to the upper end of the resistor Rs and the positive terminal of the fast response voltage comparator Comp. The output signal V Rs The lower end of resistor Rs is connected to ground voltage VSS; the negative terminal of fast response voltage comparator Comp is connected to reference voltage Vr1, and fast response voltage comparator Comp outputs bias control signal V. ctrl When the load current suddenly increases, the LDO's output voltage V... out A sudden voltage drop will be detected by the load detection circuit (common-source single-stage amplifier circuit) consisting of the current sensing transistor Ms and the resistor Rs. This abnormal fluctuation signal V Rs The bias control signal V is obtained by comparing the fast-response voltage comparator Comp with the reference voltage Vr1. ctrl Bias control signal V ctrl The switching signal S of the switch array inside the bias current source array 41 will control the dynamic bias current I. AB .

[0040] Figure 4In one embodiment of the bias circuit 4 of the present invention, the circuit includes a buffer 411, an input current source M0, a set of switch-controlled bias current source array 41 (K dynamic current sources M1 to MK, K control switches), and a fixed bias current source Mb. The gate and drain of the input current source M0 are connected to a reference current Irb, generating a gate bias voltage Vb, and are simultaneously connected to the gates of the K dynamic current sources M1 to MK and the fixed bias current source Mb. A bias control signal Vctrl is connected to the input terminal of the buffer 411, and the output terminal of the buffer 411 is the control signal S of the K control switches. The control terminal of each switch is connected to the output terminal of the buffer 411 and is controlled by the control signal S. The drain of each dynamic current source M1 to MK is connected to the bias current Irb through a switch. AB The output port; the drain of the fixed bias current source Mb is used as the fixed bias I. B The output port; where K is any positive integer. The source of the input current source M0, the sources of the K dynamic current sources M1 to MK, and the source of the fixed bias current source Mb are all grounded.

[0041] Figure 5 The dynamic bias error amplifier 2(E) of this invention A Example circuit (circuit). PMOS transistors M51, M52, M53, M56, M57, NMOS transistors M54, M55, M58, and M59 form a two-stage push-pull output operational amplifier to provide a wide-swing output to the maximum extent. PMOS transistors M510 and M511 form a wide-swing output stage circuit. Output feedback signal V. FB The feedback is connected to the op-amp input to form negative feedback and clamps to the input reference voltage V. REF In the diagram, the dynamic bias current I generated by bias circuit 4... AB and base bias current I B All terminals are connected to the current input of PMOS transistor M50 to control the magnitude of the bias voltage Vbp. The current input terminal of PMOS transistor M50 is its drain, connected to the gates of PMOS transistors M50, M51, and M510. The drain of PMOS transistor M51 is connected to the sources of PMOS transistors M52 and M53. The gate of PMOS transistor M52 is connected to the feedback signal Vbp. FB The gate of PMOS transistor M53 is connected to the reference voltage V. REFThe drain of PMOS transistor M52 is connected to the drain and gate of NMOS transistors M54 and M58; the drain of PMOS transistor M53 is connected to the drain and gate of NMOS transistors M55 and M59; the drain of PMOS transistor M56 is connected to the gate of PMOS transistor M56, the gate of PMOS transistor M57, and the drain of NMOS transistor M58; the drain of PMOS transistor M57 is connected to the drain of NMOS transistor M59 and the gate of NMOS transistor M511; and the drains of PMOS transistor M510 and NMOS transistor M511 are connected together as the error amplification signal V. EA Output terminals. The sources of PMOS transistors M50, M51, and M510 are connected to VDD, while the sources of NMOS transistors M54, M55, M58, M59, and M511 are grounded.

[0042] Figure 6 This is an embodiment of the bandgap reference circuit 1 of the present invention. The bandgap reference circuit 1 includes: a bias startup circuit 601, PMOS transistors Mr1 and Mr2, resistors Rr1, Rr2, Rr3, Rr4, and Rr5, diodes D1 and D2, operational amplifier A1, and a bias current output circuit 602. Specifically, PMOS transistors Mr1 and Mr2, resistors Rr1, Rr2, and Rr3, diodes D1 and D2, and operational amplifier A1 constitute a bandgap voltage generation core circuit. The input bias voltage of the bandgap voltage generation core circuit is the gate voltage Vb1 of PMOS transistor Mr1 and the gate voltage Vb2 of PMOS transistor Mr2. The output bandgap voltage Vb1 of the bandgap voltage generation core circuit is Vb2. REF That is, the reference voltage V REF The reference voltage Vr1 is generated by voltage division through resistors Rr4 and Rr5.

[0043] The aforementioned bias startup circuit 601 has a power-on startup function. During power-on, it first provides an initial input bias voltage Vb1 and Vb2, which control the gates of PMOS transistors Mr1 and Mr2 respectively, thereby starting the bandgap voltage generation core circuit. After power-on, the operational amplifier A1 inside the bandgap voltage generation core circuit will control the Vb1 voltage. At this time, the bias voltages Vb1 and Vb2 will remain unchanged and are temperature-insensitive reference voltages. The bias current output circuit 602 generates a reference current Irb based on the bias voltages Vb1 and Vb2.

[0044] Figure 7This is a schematic diagram of the bias startup circuit 601. The bias startup circuit includes: PMOS transistors M71, M75, M76, M78, M710, M715, NMOS transistors M72, M73, M74, M77, M79, M711, M712, M713, and M714.

[0045] The gate and drain of PMOS transistor M71 are connected, and then connected to the drains of NMOS transistors M72, M73, M74, and M75. PMOS transistors M75, M76, M78, M74, M77, and M79 form a three-stage cascaded inverter chain. The input of this inverter chain is point A, the connection point between the gate and drain of PMOS transistor M71, and the output is the drains of PMOS transistors M78 and M79. The output of the inverter chain is also connected to NMOS transistor M75. The gates of transistors M2, M73, M711, M712, M713, and M714 are connected; the drain of NMOS transistor M711 is connected to the gate and drain of PMOS transistor M710 and serves as the output of the bias voltage Vb1; the source of NMOS transistor M711 is connected to the drain of NMOS transistor M712; the drain of NMOS transistor M714 is connected to the gate and drain of PMOS transistor M715 and serves as the output of the bias voltage Vb2; the source of NMOS transistor M714 is connected to the drain of NMOS transistor M713.

[0046] The sources of PMOS transistors M71, M75, M76, M78, M710, and M715 are all connected to the power supply voltage VDD; the sources of NMOS transistors M72, M73, M74, M77, M79, M711, M712, M713, and M714 are all connected to the ground voltage VSS.

[0047] Figure 8 This is a simulation waveform of the power-on startup of the bias startup circuit 601. During the power supply rise from 0-5V, the voltages at positions A, B, and C in the circuit are successively converted to fixed voltage states, thus achieving the power-on function.

[0048] Figure 9A block diagram of an embodiment of the multi-protection circuit 5 of the present invention is shown. The multi-protection circuit 5 includes: a first clamping circuit 911, a second clamping circuit 921, a third clamping circuit 931, a fourth clamping circuit 941, a temperature detection circuit 912, a current detection circuit 922, a first voltage detection circuit 932, a second voltage detection circuit 942, a detection input switch selection circuit 93, a high-precision comparator 94, a shaping buffer circuit 95, a detection output switch selection circuit 96, an OSC oscillator circuit 97, a timer circuit 98, and error handling logic 99.

[0049] The first clamping circuit 911 provides a bias voltage VbT based on the state of the temperature lockout signal OTLock, and outputs it to the temperature detection circuit 912. The temperature detection circuit 912 obtains the temperature detection output signal VinT based on the bias voltage VbT. The second clamping circuit 921 provides a bias voltage VbC based on the state of the overcurrent lockout signal OCLock, and outputs it to the current detection circuit 922. The current detection circuit 922 obtains the current detection output signal VinC based on the bias voltage VbC. The third clamping circuit 931 provides a bias voltage VbL based on the state of the undervoltage lockout signal UVLock, and outputs it to the current detection circuit 932. The current detection circuit 932 obtains the undervoltage detection output signal VinL based on the bias voltage VbC. The fourth clamping circuit 941 provides a bias voltage VbH based on the state of the overvoltage lockout signal OVLock, and outputs it to the current detection circuit 942. The current detection circuit 942 obtains the overvoltage detection output signal VinH based on the bias voltage VbH.

[0050] The temperature detection output signal VinT, the current detection output signal VinC, the undervoltage detection output signal VinL, and the overvoltage detection output signal VinH simultaneously enter the detection input switch selection circuit 93. After selection by the switch selection control signal Selp, a detection signal Vind (one of VinT, VinC, VinL, and VinH) is output. The switch selection control signal Selp has four switching states: in state one, the temperature detection output signal VinT is selected and connected to the signal Vind; in state two, the current detection output signal VinC is selected and connected to the signal Vind; in state three, the undervoltage detection output signal VinL is selected and connected to the signal Vind; and in state four, the overvoltage detection output signal VinH is selected and connected to the signal Vind. The high-precision comparator 94 compares the detection signal Vind with the internal reference signal to obtain the comparison output signal Vo; the shaping buffer circuit 95 processes the comparison output signal Vo to obtain the protection signal OP and the protection lockout signal OPL; the protection signal OP and the protection lockout signal OPL simultaneously enter the detection output switch selection circuit 96. The output terminals of the detection output switch selection circuit 96 have four sets, which are connected to the error handling logic 99 respectively. They are: one set of over-temperature protection signal OTP and temperature lockout signal OTLock, one set of over-current protection signal OCP and over-current lockout signal OCLock, one set of under-voltage protection signal UVLO and under-voltage lockout signal UVLock, and one set of over-voltage protection signal OVP and over-voltage lockout signal OVLock.

[0051] The output of the detection output switch selection circuit 96 is also selected by the switch selection control signal Selp. In state one, the protection signal OP and the protection lockout signal OPL are selected and connected to the over-temperature protection signal OTP and the temperature lockout signal OTLock, respectively. In state two, the protection signal OP and the protection lockout signal OPL are selected and connected to the overcurrent protection signal OCP and the overcurrent lockout signal OCLock, respectively. In state three, the protection signal OP and the protection lockout signal OPL are selected and connected to the undervoltage protection signal UVLO and the undervoltage lockout signal UVLock, respectively. In state four, the protection signal OP and the protection lockout signal OPL are selected and connected to the overvoltage protection signal OVP and the overvoltage lockout signal OVLock, respectively.

[0052] The input switch selection circuit 93 and the output switch selection circuit 96 can be implemented using a conventional 4-to-1 data selector. The switch selection control signal Selp is generated by the OSC oscillator circuit 97 and the timer circuit 98. The OSC oscillator circuit 97 first generates a high-frequency clock, which is then timed by the timer circuit 98 to generate the switch selection control signal Selp; the over-temperature protection signal OTP, the over-current protection signal OCP, the under-voltage protection signal UVLO, and the over-voltage protection signal OVP are also generated. At the same time, the error handling logic 99 performs the set logic operation to generate the error signal Error.

[0053] Figure 9 The circuit shown works as follows: When the temperature is normal, the temperature lockout signal OTLock is high. The high level of OTLock controls the first clamping circuit 911 to generate a higher bias voltage VbT. The temperature detection circuit 912 generates a temperature detection output signal VinT based on VbT. Under normal circumstances, the output signal Vo obtained by the high-precision comparator 94 should be high. The shaping buffer circuit 95 processes the comparison output signal Vo and finally outputs a high-level logic signal, OTLock. When the chip temperature is abnormal, the temperature detection output signal VinT generated by the temperature detection circuit 912 will change. The high-precision comparator 94 will change the comparison output signal VoT to a low level signal based on the obtained comparison signal. The temperature lock signal OTLock finally output by the shaping buffer circuit 95 will also change to a low level logic signal. The over-temperature protection signal OTP will become low level. The low level of the temperature lock signal OTLock will control the first clamping circuit 911 to generate a lower bias voltage VbT. The lower bias voltage VbT will further change the magnitude of the temperature detection output signal VinT, so that the Vo output by the high-precision comparator 94 will be further locked to a low level signal.

[0054] When the current is normal, the overcurrent lockout signal OCLock is high. The high level of OCLock controls the second clamping circuit 921 to generate a higher bias voltage VbC. The current detection circuit 922 generates a current detection output signal VinC based on VbC. Under normal circumstances, the output signal Vo of the high-precision comparator 94 should be high. The shaping buffer circuit 95 processes the comparison output signal Vo, and the final output OCLock is also a high-level logic signal. When the chip current is abnormal, the current detection output signal VinC generated by the current detection circuit 922 will change. The high-precision comparator 94 will change the obtained comparison output signal VoC to a low level signal. The current lockout signal OCLock obtained by the shaping buffer circuit 95 will also change to a low level logic signal. The overcurrent protection signal OCP will become low level. The low level of the overcurrent lockout signal OCLock will control the second clamping circuit 921 to generate a lower bias voltage VbC. The lower bias voltage VbC will further change the magnitude of the current detection output signal VinC, so that the Vo output by the second high-precision comparator 923 will be further locked to a low level signal.

[0055] When the voltage is normal, the undervoltage lockout signal UVLock is high. This high UVLock level controls the third clamping circuit 931 to generate a higher bias voltage VbL. The first voltage detection circuit 932 generates an undervoltage detection output signal VinL based on VbL. Under normal circumstances, the output signal Vo obtained by the high-precision comparator 94 should be high. The shaping buffer circuit 95 processes the comparison output signal Vo, and the final output UVLock is also a high-level logic signal. When the chip voltage is abnormally low, the undervoltage detection output signal VinL generated by the first voltage detection circuit 932 will change. The high-precision comparator 94 will change the obtained comparison output signal Vo to a low level signal. The undervoltage lockout signal UVLock finally output by the shaping buffer circuit 95 will also change to a low level logic signal. The undervoltage protection signal UVLO will become low level. The low level of the undervoltage lockout signal UVLock will control the third clamping circuit 931 to generate a lower bias voltage VbL. The lower bias voltage VbL will further change the magnitude of the undervoltage detection output signal VinL, so that the Vo output by the high-precision comparator 94 will be further locked to a low level signal.

[0056] The overvoltage protection process operates similarly to the undervoltage protection process described above. When the voltage is normal, the overvoltage lockout signal OVLock is high; when the voltage is too high, the overvoltage lockout signal OVLock also changes to a low logic signal, and the overvoltage protection signal OVP becomes low.

[0057] Figure 10 This is one embodiment of the clamping circuit used in the present invention. Figure 10 The signal identifier in the embodiment uses the signal from the temperature detection section. The first clamping circuit 911, the second clamping circuit 921, the third clamping circuit 931, and the fourth clamping circuit 941 in the embodiment all use [the signal]. Figure 10 The same clamping circuit is used.

[0058] This circuit consists of PMOS transistors M111, M112, M113, and M114, and resistors R111, R112, R113, and R114. The source of PMOS transistor M111, the upper end of resistor R111, and the drain of NMOS transistor M114 are all connected to the power supply voltage VDD. The gate of PMOS transistor M111 is connected to the gate of NMOS transistor M112 and also serves as the control signal input terminal of the clamping circuit, connected to the temperature lockout signal OTLock. The drain of PMOS transistor M111 is connected to the drain of NMOS transistor M112 and simultaneously connected to the gate of NMOS transistor M113. The drain of transistor 3 is connected to both the upper end of resistor R113 and the lower end of resistor R112; the upper end of resistor R112 is connected to the lower end of resistor R111 and is connected to the gate of NMOS transistor M114; the source of NMOS transistor M114 is connected to the upper end of resistor R114 and serves as the bias voltage output node of the clamping circuit; the source of NMOS transistor M112, the lower end of resistor R113, the lower end of resistor R114, and the source of NMOS transistor M113 are all connected to ground voltage VSS.

[0059] In this clamping circuit, the power supply voltage VCC is detected in real time by voltage divider resistors R111, R112, and R113. The voltage value obtained by voltage division passes through a source follower consisting of NMOS transistor M114 and resistor R114 to obtain the bias voltage VbT, which then enters the subsequent temperature detection circuit 1012. The resistance value of R113 is controlled by M113, and the on / off state of M113 is controlled by the OTLock signal. When the OTLock signal is high, the gate of M113 is low, M113 is in the off state, R113 is a large resistor, and the voltage value VbT obtained by voltage division is a relatively high bias voltage. When the OTLock signal is low, the gate of M113 is high, M113 is in the on state, R113 is shorted by M113 to a very small resistance, and the voltage value VbT obtained by voltage division is a relatively low bias voltage.

[0060] Figure 11 This is an embodiment of a high-precision comparator 94. The circuit includes: PMOS transistors M121, M122, M123, M124, M125, M126, M127, M128, M129, M1210, M1211, M1212, M1213, M1214, and M1215, resistor R121, and capacitor C121.

[0061] In this circuit, the gate of PMOS transistor M121 is connected to the bias voltage Vb121, and the drain of PMOS transistor M121 is connected to the drain, gate, gate, M123, M128, and gate of NMOS transistors M129. The drain of NMOS transistor M123 is connected to the drain, gate, and gate of PMOS transistors M124 and M125. The drain of PMOS transistor M125 is connected to the source of PMOS transistors M126 and M127. The gate of PMOS transistor M126 is connected to the reference voltage of the high-precision comparator 94. The gate of PMOS transistor M127 is the comparison voltage input terminal, connected to the detection input switch selection circuit 93. The output is Vind; the drain of PMOS transistor M126 is connected to the drain of NMOS transistor M129 and the gate of NMOS transistor M1210; the drain of PMOS transistor M127 is connected to the drain of NMOS transistor M128 and the gate of NMOS transistor M1214; the drain of PMOS transistor M1211 is connected to the drain of NMOS transistor M1210 and the gate of PMOS transistor M1212; the drain of PMOS transistor M1212 is connected to the gate of PMOS transistor M1211, the drain of NMOS transistor M1214, the gate of PMOS transistor M1213 and the gate of NMOS transistor M1215; the drain of PMOS transistor M1213 is connected to the drain of NMOS transistor M1215, the upper end of resistor R121 and capacitor C121, and serves as the signal Vo output terminal.

[0062] The sources of NMOS transistors M122, M123, M128, M129, M1210, M1214, and M1215, the lower end of resistor R121, and the lower end of capacitor C121 are all connected to ground voltage VSS; the sources of PMOS transistors M121, M124, M125, M1211, M1212, and M1213 are all connected to power supply voltage VDD.

[0063] Figure 12An embodiment of the shaping buffer circuit 95 includes PMOS transistors M131, M133, M135, M136, M139, M1311, NMOS transistors M132, M134, M137, M138, M1310, and M1312, resistors R131 and R132, and capacitor C131. The circuit consists of PMOS transistors M131, M133, M132, and M134, resistors R131 and R132, and capacitor C131 forming a buffer with RC filtering. PMOS transistors M135, M136, M139, M137, M138, and M1310 form a Schmitt trigger. PMOS transistors M1311 and M1312 form an output inverter. The input of the buffer with RC filtering is connected to the comparison output voltage Vo of the high-precision comparator 104. The output of the buffer with RC filtering is connected to the input of the Schmitt trigger. The output of the Schmitt trigger is connected to the input of the output inverter and the OP signal output. The output of the output inverter outputs the temperature lockout signal OPL.

[0064] Figure 13 This is an embodiment of the error handling logic circuit 99 of the present invention, which is composed of combinational logic gates. The function of the error handling logic circuit 99 is to synthesize the chip status monitoring signals to determine whether the circuit is normal, and to shut down the data output when the chip is abnormal. The control process implemented by this circuit is as follows: when the circuit experiences overcurrent (OCLock high level), overtemperature (OTLock high level), power supply voltage overvoltage (OVLock high level), or power supply voltage undervoltage (UVLock high level), the error logic circuit outputs a low-level Error signal to indicate that the circuit has malfunctioned; when the overcurrent and overtemperature alarms are cleared and the power supply returns to normal operating voltage, the error logic circuit 99 immediately outputs a high-level signal to indicate that the circuit is working normally.

[0065] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A fast-response LDO circuit with multiple protection functions, characterized in that: include: The bandgap reference circuit (1), dynamic bias error amplifier (2), dynamic bias control circuit (3), bias circuit (4), multiple protection circuit (5), power transistor Mn, feedback resistor R1, and feedback resistor R2 are included. The bandgap reference circuit (1) generates a reference voltage V. REF The reference voltage Vr1 and the reference current Irb, where the reference voltage Vr1 is... REF The reference voltage Vr1 is connected to the positive terminal of the dynamic bias error amplifier (2), the reference voltage Vr1 is connected to the dynamic bias control circuit (3) and the multiple protection circuit (5), and the reference current Irb is connected to the bias circuit (4); the bias circuit (4) is based on the reference current Irb generated by the bandgap reference circuit (1) and the bias control signal Vr1 output by the dynamic bias control circuit (3). ctrl Generate bias current I B and bias current I AB The negative terminal of the dynamic bias error amplifier (2) is connected to the lower end of the feedback resistor R1, and the output terminal of the dynamic bias error amplifier (2) is connected to the gate of the power transistor Mn and the control signal input terminal of the dynamic bias control circuit (3). The drain of the power transistor Mn is connected to the power supply voltage VDD, and the source of the power transistor Mn is connected to the upper end of the feedback resistor R1 and serves as the output port Vout of the overall LDO circuit. The lower end of the feedback resistor R1 is connected to the upper end of the feedback resistor R2 and serves as the generation node of the feedback voltage Vfb. The lower end of the feedback resistor R2 is connected to the ground voltage VSS. The dynamic bias error amplifier (2) is based on the reference voltage V REF Bias current I B Bias current I AB And the feedback voltage Vfb, generate the error amplification signal V EA ; Dynamic bias control circuit (3) based on error amplification signal V EA The bias control signal V is generated with the reference voltage Vr1. ctrl , connected to the bias circuit (4); the multiple protection circuit (5) detects the chip status and compares it with the reference voltage Vr1, and outputs the chip status monitoring signal Error.

2. The fast-response LDO circuit with multiple protection functions according to claim 1, characterized in that, The bias current of the dynamic bias error amplifier (2) is in addition to a fixed bias current I. B In addition, there is an extra dynamic bias current I AB The dynamic bias control circuit (3) will detect changes in load current and generate a bias control signal V. ctrl To control the dynamic bias current I AB This is used to change the bias current of the dynamic bias error amplifier (2) and thus change its transient response speed.

3. The fast-response LDO circuit with multiple protection functions according to claim 1, characterized in that, The dynamic bias control circuit (3) includes: a load detection circuit composed of a current sensing transistor Ms and a resistor Rs, and a fast response voltage comparator Comp. The gate of the current sensing transistor Ms is connected to the error amplification signal V. EA The drain of the current sensing transistor Ms is connected to the power supply voltage VDD, and the source of the current sensing transistor Ms is connected to the upper end of the resistor Rs and the positive terminal of the fast response voltage comparator Comp. The output signal V Rs The lower end of resistor Rs is connected to ground voltage VSS; the negative terminal of fast response voltage comparator Comp is connected to reference voltage Vr1, and fast response voltage comparator Comp outputs bias control signal V. ctrl When the load current suddenly increases, the output voltage V of the overall LDO circuit... out The current will suddenly drop, and the load detection circuit consisting of the current sensing tube Ms and the resistor Rs will detect this abnormal fluctuation. This fluctuation signal V Rs The bias control signal V is obtained by comparing the fast-response voltage comparator Comp with the reference voltage Vr1. ctrl .

4. The fast-response LDO circuit with multiple protection functions according to claim 1, characterized in that, The bias circuit (4) includes a set of switch-controlled bias current source arrays (41), which have K dynamic current sources M1 to MK, where K is any positive integer. The drain of each dynamic current source M1 to MK is connected to the bias current I through a switch. AB The output port of each switch is connected to the output of the buffer (411) and controlled by the control signal S. The input of the buffer (411) is connected to the bias control signal V. ctrl The buffer (411) outputs a control signal S; the bias circuit (4) further includes an input current source M0 and a fixed bias current source Mb. The gate and drain of the input current source M0 are connected to the reference current Irb. The gate of the input current source M0 generates a gate bias voltage Vb, which is simultaneously connected to the gates of K dynamic current sources M1 to MK and the gate of the fixed bias current source Mb. The drain of the fixed bias current source Mb serves as the fixed bias current Irb. B The output port; the source of the input current source M0, the sources of the K dynamic current sources M1 to MK, and the source of the fixed bias current source Mb are all grounded.

5. The fast-response LDO circuit with multiple protection functions according to claim 1, characterized in that, The bandgap reference circuit (1) includes: PMOS transistors Mr1 and Mr2, resistors Rr1, Rr2, Rr3, Rr4, and Rr5, diodes D1 and D2, operational amplifier A1, a bias start-up circuit (601), and a bias current output circuit (602); wherein, PMOS transistors Mr1 and Mr2, resistors Rr1, Rr2, and Rr3, diodes D1 and D2, and operational amplifier A1 constitute a bandgap voltage generation core circuit, the gates of PMOS transistors Mr1 and Mr2 are respectively connected to the bias voltage output terminal of the bias start-up circuit (601), the source of PMOS transistor Mr1 is connected to the power supply VDD, the drain of PMOS transistor Mr1 is connected to the source of PMOS transistor Mr2, and the drain of PMOS transistor Mr2 is connected to the power supply VDD. The upper ends of resistors Rr1 and Rr2 are connected to output a bandgap voltage. The lower end of resistor Rr1 is connected to the positive terminal of operational amplifier A1 and the anode of diode D1, and the lower end of resistor Rr2 is connected to the negative terminal of operational amplifier A1 and the anode of diode D2. The output terminal of operational amplifier A1 is connected to the gate of PMOS transistor Mr1. ​​The bandgap voltage output from the source of PMOS transistor Mr2 is connected to the upper end of resistor Rr5. The lower end of resistor Rr5 is grounded through resistor Rr4 and outputs a reference voltage Vr1. The two bias voltage output terminals of the bias startup circuit (601) are also connected to the input terminals of the bias current output circuit (602). The input bias voltage of the bandgap voltage generating core circuit is the gate voltage Vb1 of PMOS transistor Mr1 and the gate voltage Vb2 of PMOS transistor Mr2. The output bandgap voltage of the bandgap voltage generating core circuit is the reference voltage Vr1. REF Reference voltage V REF The reference voltage Vr1 is generated by voltage division through resistors Rr4 and Rr5; the bias start-up circuit (601) has a power-on start-up function. During the power-on process, it first provides initial bias voltages Vb1 and Vb2 to control the gates of PMOS transistors Mr1 and Mr2, respectively; after power-on, the bias current output circuit (602) generates a reference current Irb according to the bias voltages Vb1 and Vb2 and outputs it to the bias circuit (4).

6. The fast-response LDO circuit with multiple protection functions according to claim 5, characterized in that, The bias start-up circuit (601) includes: PMOS transistor M71, NMOS transistor M72, NMOS transistor M73, NMOS transistor M74, PMOS transistor M75, PMOS transistor M76, NMOS transistor M77, PMOS transistor M78, NMOS transistor M79, PMOS transistor M710, NMOS transistor M711, NMOS transistor M712, NMOS transistor M713, NMOS transistor M714, and PMOS transistor M715; the gate of PMOS transistor M71 is connected to the drain of PMOS transistor M71, the drain of NMOS transistor M72, the drain of NMOS transistor M73, and NMOS transistor M74. The gates of MOSFET M74 and PMOS transistor M75 are connected. NMOS transistors M74, M75, M76, M77, M78, and M79 form a three-stage cascaded inverter chain. The drain of PMOS transistor M75 is connected to the drain of NMOS transistor M74, the gate of PMOS transistor M76, and the gate of NMOS transistor M77. The drain of PMOS transistor M76 is connected to the drain of NMOS transistor M77, the gate of PMOS transistor M78, and the gate of NMOS transistor M79. The drain of PMOS transistor M78 is connected to the drain of NMOS transistor M79, serving as the inverter. The output of the inverter chain is connected to the gates of NMOS transistors M72, M73, M711, M712, M713, and M714. The input of the inverter chain is the gate of PMOS transistor M71. The drain of NMOS transistor M711 is connected to the drain and gate of PMOS transistors M710 and serves as the output of the bias voltage Vb1. The source of NMOS transistor M711 is connected to the drain of NMOS transistor M712. The drain of NMOS transistor M714 is connected to the drain of PMOS transistor M715. The gate of PMOS transistor M715 is connected to the output terminal of bias voltage Vb2, and the source of NMOS transistor M714 is connected to the drain of NMOS transistor M713. The sources of PMOS transistors M71, M75, M76, M78, M710, and M715 are all connected to the power supply voltage VDD. The sources of NMOS transistors M72, M73, M74, M77, M79, M712, and M713 are all connected to the ground voltage VSS.

7. The fast-response LDO circuit with multiple protection functions according to claim 1, characterized in that, The multi-protection circuit (5) includes: a temperature detection circuit (912), a current detection circuit (922), a first voltage detection circuit (932), and a second voltage detection circuit (942); the input terminal of the temperature detection circuit (912) is connected to a first clamping circuit (911), which generates a bias voltage VbT according to the state of the temperature lockout signal OTLock and outputs it to the temperature detection circuit (912), which outputs a temperature detection signal VinT; the input terminal of the current detection circuit (922) is connected to a second clamping circuit (921), which generates a bias voltage VbC according to the state of the overcurrent lockout signal OCLock and outputs it to the current detection circuit (922). The current detection circuit (922) outputs a current detection output signal VinC; the input terminal of the first voltage detection circuit (932) is connected to the third clamping circuit (931), the third clamping circuit (931) generates a bias voltage VbL according to the state of the undervoltage lockout signal UVLock, and outputs it to the first voltage detection circuit (932), the first voltage detection circuit (932) outputs an undervoltage detection output signal VinL; the input terminal of the second voltage detection circuit (942) is connected to the fourth clamping circuit (941), the fourth clamping circuit (941) generates a bias voltage VbH according to the state of the overvoltage lockout signal OVLock, and outputs it to the second voltage detection circuit (942), the second voltage detection circuit (942) outputs an overvoltage detection output signal VinH; The temperature detection output signal VinT, current detection output signal VinC, undervoltage detection output signal VinL, and overvoltage detection output signal VinH are simultaneously connected to the detection input switch selection circuit (93). Selected by the switch selection control signal Selp, the switch selection circuit (93) outputs a detection signal Vind, which is connected to a high-precision comparator (94). The high-precision comparator (94) compares the detection signal Vind with an internal reference signal and outputs a comparison output signal VoT, which is connected to a shaping buffer circuit (95). The shaping buffer circuit (95) processes the comparison output signal VoT to obtain a protection signal OP and a protection lockout signal OPL, which are then connected to... The detection output switch selection circuit (96) is connected to the detection output switch selection circuit (96). The detection output switch selection circuit (96) has four sets of output terminals, which are respectively connected to the error handling logic (99). One set of over-temperature protection signal OTP and temperature lockout signal OTLock, one set of over-current protection signal OCP and over-current lockout signal OCLock, one set of under-voltage protection signal UVLO and under-voltage lockout signal UVLock, and one set of over-voltage protection signal OVP and over-voltage lockout signal OVLock. The detection output switch selection circuit (96) selects one set of outputs to the error handling logic (99) via the switch selection control signal Selp. The error handling logic (99) is used to generate the error signal Error. The detection input switch selection circuit (93) and the detection output switch selection circuit (96) adopt a 4-to-1 data selector. The switch selection control signal Selp has 4 switch states. In state one, the temperature detection output signal VinT is selected and connected to the detection signal Vind. The protection signal OP and the protection lock signal OPL are selected and connected to the output terminals of the over-temperature protection signal OTP and the temperature lock signal OTLock, respectively. In state two, the current detection output signal VinC is strobed and connected to the detection signal Vind, and the protection signal OP and the protection lockout signal OPL are strobed and connected to the output terminals of the overcurrent protection signal OCP and the overcurrent lockout signal OCLock, respectively. In state three, the undervoltage detection output signal VinL is strobed and connected to the detection signal Vind, and the protection signal OP and the protection lockout signal OPL are strobed and connected to the output terminals of the undervoltage protection signal UVLO and the undervoltage lockout signal UVLock, respectively. In state four, the overvoltage detection output signal VinH is strobed and connected to the detection signal Vind, and the protection signal OP and the protection lockout signal OPL are strobed and connected to the output terminals of the overvoltage protection signal OVP and the overvoltage lockout signal OVLock, respectively. The switch selection control signal Selp is generated by the OSC oscillator circuit (97) and the timer circuit (98). The OSC oscillator circuit (97) first generates a high-frequency clock, which is connected to the timer circuit (98). The timer circuit generates the switch selection control signal Selp at regular intervals, which is connected to the input switch selection circuit (93) and the output switch selection circuit (96).

8. The fast-response LDO circuit with multiple protection functions according to claim 7, characterized in that, The high-precision comparator (94) includes: PMOS transistors M121, M122, M123, M124, M125, M126, M127, M128, M129, M1210, M1211, M1212, M1213, M1214, and M1215, resistor R121, and capacitor C121; wherein, the gate of PMOS transistor M121 is connected to a bias voltage, and PMOS transistor M121... The drain of NMOS transistor M122 is connected to the drain and gate of NMOS transistor M122, the gate of NMOS transistor M123, the gate of NMOS transistor M128, and the gate of NMOS transistor M129; the drain of NMOS transistor M123 is connected to the drain and gate of PMOS transistor M124, the gate of PMOS transistor M124, and the gate of PMOS transistor M125; the drain of PMOS transistor M125 is connected to the source of PMOS transistor M126 and the source of PMOS transistor M127; the gate of PMOS transistor M126 is connected to the reference voltage of the high-precision comparator (94); the gate of PMOS transistor M127 is the comparison voltage input terminal and is connected to Vind; PMOS transistor M126 The drain of PMOS transistor M127 is connected to the drain of NMOS transistor M129 and the gate of NMOS transistor M1210; the drain of PMOS transistor M127 is connected to the drain of NMOS transistor M128 and the gate of NMOS transistor M1214; the drain of PMOS transistor M1211 is connected to the drain of NMOS transistor M1210 and the gate of PMOS transistor M1212; the drain of PMOS transistor M1212 is connected to the gate of PMOS transistor M1211, the drain of NMOS transistor M1214, the gate of PMOS transistor M1213, and the gate of NMOS transistor M1215; the drain of PMOS transistor M1213 is connected to the drain of NMOS transistor M1215, the upper end of resistor R121, and capacitor C12.

1. The upper end serves as the signal Vo output terminal; the sources of NMOS transistors M122, M123, M128, M129, M1210, M1214, and M1215, the lower end of resistor R121, and the lower end of capacitor C121 are all connected to ground voltage VSS; the sources of PMOS transistors M121, M124, M125, M1211, M1212, and M1213 are all connected to power supply voltage VDD.

Images