Multilevel interconnect structures and methods for fabricating the same

Abstract

A multilayer interconnect structure having a scatterometry test layer and a method of manufacturing the same are disclosed. The multilayer interconnect structure includes a patterned reflective layer, a bulk reflective layer, and a patterned test layer. The patterned reflective layer is disposed on a substrate and includes a first reflective pattern and a second reflective pattern separated from each other. The bulk reflective layer is disposed on the patterned reflective layer. The patterned test layer is disposed on the bulk reflective layer.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for manufacturing the same, and more particularly to a multilevel interconnect structure having a scatterometry test layer and a method for manufacturing the same. Background Technology

[0002] In current semiconductor manufacturing processes, optical critical dimension (OCD) measurements are typically performed on the device under test (DUT) within a test area. Generally, OCD measurements involve projecting light onto the test area and measuring based on the reflected light. However, when light enters the film layer beneath the DUT, the reflected light may carry noise from the underlying layer, affecting measurement accuracy.

[0003] To prevent reflected light from carrying noise from underlying layers, a bulk reflective layer is typically placed beneath the device under test (DUT) to prevent light from entering the underlying film. However, as device sizes continue to miniaturize and thin, the thickness of this bulk reflective layer decreases, leading to light leakage and affecting measurement accuracy. Furthermore, when the bulk reflective layer is too thin, dishing can occur during subsequent grinding processes, impacting the reflection effect. Summary of the Invention

[0004] The present invention provides a multi-layer interconnect structure, including a patterned reflective layer of a first reflective pattern and a second reflective pattern separated from each other, disposed below a block-shaped reflective layer.

[0005] The present invention provides a method for manufacturing a multilayer interconnect structure, including a patterned reflective layer of a first reflective pattern and a second reflective pattern separated from each other, formed below a blocky reflective layer.

[0006] The multilayer interconnect structure of the present invention includes a scattering test layer. The multilayer interconnect structure includes a patterned reflective layer, a blocky reflective layer, and a patterned test layer. The patterned reflective layer is disposed on a substrate and includes a first reflective pattern and a second reflective pattern spaced apart from each other. The blocky reflective layer is disposed on the patterned reflective layer. The patterned test layer is disposed on the blocky reflective layer.

[0007] In one embodiment of the multilayer interconnect structure of the present invention, the first reflective pattern includes a plurality of parallel strip patterns, the second reflective pattern includes a plurality of conductive via patterns, and the conductive via patterns are located between two adjacent strip patterns.

[0008] In one embodiment of the multilayer interconnect structure of the present invention, multiple rows of through-hole patterns are provided between two adjacent strip patterns.

[0009] In one embodiment of the multilayer interconnect structure of the present invention, the first reflective pattern includes a block pattern with multiple openings, the second reflective pattern includes multiple through-hole patterns, and the multiple through-hole patterns are located in the multiple openings.

[0010] In one embodiment of the multilayer interconnect structure of the present invention, the first reflective pattern includes a plurality of first through-hole patterns, the second reflective pattern includes a plurality of second through-hole patterns, and the apertures of the plurality of first through-hole patterns and the apertures of the plurality of second through-hole patterns are different from each other.

[0011] In one embodiment of the multilayer interconnect structure of the present invention, the patterned reflective layer further includes a third reflective pattern, the first reflective pattern includes a plurality of first via patterns, the second reflective pattern includes a plurality of second via patterns, the third reflective pattern includes a plurality of third via patterns, and the apertures of the plurality of first via patterns, the plurality of second via patterns, and the plurality of third via patterns are different from each other.

[0012] In one embodiment of the multilayer interconnect structure of the present invention, the ratio of the projected area of ​​the patterned reflective layer on the substrate to the projected area of ​​the blocky reflective layer on the substrate is between 0.75 and 0.90.

[0013] In one embodiment of the multilayer interconnect structure of the present invention, the material of the patterned reflective layer includes metal.

[0014] In one embodiment of the multilayer interconnect structure of the present invention, the material of the blocky reflective layer includes metal.

[0015] In one embodiment of the multilayer interconnect structure of the present invention, the blocky reflective layer is located directly below the patterned test layer, and the patterned reflective layer is located directly below the blocky reflective layer.

[0016] In one embodiment of the multilayer interconnect structure of the present invention, a dielectric layer disposed between the blocky reflective layer and the patterned test layer is further included.

[0017] In one embodiment of the multilayer interconnect structure of the present invention, a dielectric layer disposed between the first reflective pattern and the second reflective pattern is further included.

[0018] The method for manufacturing a multilayer interconnect structure with a scattering test layer according to the present invention includes the following steps: forming a patterned reflective layer on a substrate, wherein the patterned reflective layer includes a first reflective pattern and a second reflective pattern spaced apart from each other; forming a blocky reflective layer on the patterned reflective layer; and forming a patterned test layer on the blocky reflective layer.

[0019] In one embodiment of the manufacturing method of the multilayer interconnect structure of the present invention, the first reflective pattern includes a plurality of parallel strip patterns, the second reflective pattern includes a plurality of through-hole patterns, and the through-hole patterns are located between two adjacent strip patterns.

[0020] In one embodiment of the manufacturing method of the multilayer interconnect structure of the present invention, multiple rows of through hole patterns are provided between two adjacent strip patterns.

[0021] In one embodiment of the manufacturing method of the multilayer interconnect structure of the present invention, the first reflective pattern includes a block pattern having a plurality of openings, the second reflective pattern includes a plurality of through-hole patterns, and the plurality of through-hole patterns are located in the plurality of openings.

[0022] In one embodiment of the manufacturing method of the multilayer interconnect structure of the present invention, the first reflective pattern includes a plurality of first through-hole patterns, the second reflective pattern includes a plurality of second through-hole patterns, and the apertures of the plurality of first through-hole patterns and the apertures of the plurality of second through-hole patterns are different from each other.

[0023] In one embodiment of the manufacturing method of the multilayer interconnect structure of the present invention, the patterned reflective layer further includes a third reflective pattern, the first reflective pattern includes a plurality of first via patterns, the second reflective pattern includes a plurality of second via patterns, the third reflective pattern includes a plurality of third via patterns, and the apertures of the plurality of first via patterns, the plurality of second via patterns, and the plurality of third via patterns are different from each other.

[0024] In one embodiment of the manufacturing method of the multilayer interconnect structure of the present invention, the ratio of the projected area of ​​the patterned reflective layer on the substrate to the projected area of ​​the blocky reflective layer on the substrate is between 0.75 and 0.90.

[0025] In one embodiment of the manufacturing method of the multilayer interconnect structure of the present invention, the blocky reflective layer is located directly below the patterned test layer, and the patterned reflective layer is located directly below the blocky reflective layer.

[0026] In one embodiment of the manufacturing method of the multilayer interconnect structure of the present invention, after forming the block reflective layer and before forming the patterned test layer, a dielectric layer is further formed on the block reflective layer.

[0027] In one embodiment of the manufacturing method of the multilayer interconnect structure of the present invention, a dielectric layer is further formed between the first reflective pattern and the second reflective pattern.

[0028] Based on the above, in the multilayer interconnect structure with a scattering test layer of the present invention, the patterned reflective layer and the block reflective layer are located below the patterned test layer (as a scattering test layer) to serve as a reflective structure. Therefore, during optical critical size measurement, when light enters below the patterned test layer, the light can be directly reflected without carrying noise from the lower layer, thus ensuring measurement accuracy.

[0029] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0030] Figures 1A to 1C This is a cross-sectional schematic diagram illustrating the manufacturing process of the multi-layer interconnect structure according to the first embodiment of the present invention.

[0031] Figure 2A This is a top view schematic diagram of a patterned reflective layer with a multi-layer interconnect structure as illustrated in the first embodiment of the present invention.

[0032] Figure 2B This is a top view schematic diagram of the blocky reflective layer with a multi-layer interconnect structure shown in the first embodiment of the present invention.

[0033] Figure 2C This is a top view schematic diagram of a patterned test layer with a multi-layer interconnect structure as illustrated in the first embodiment of the present invention.

[0034] Figure 3 This is a top view schematic diagram of a patterned reflective layer with a multi-layer interconnect structure as illustrated in the second embodiment of the present invention.

[0035] Figure 4 This is a top view schematic diagram of a patterned reflective layer with a multi-layer interconnect structure as illustrated in the third embodiment of the present invention.

[0036] Figure 5 This is a top view schematic diagram of the patterned reflective layer with a multilayer interconnect structure as illustrated in the fourth embodiment of the present invention;

[0037] Figure 6 This is a top view schematic diagram of a patterned reflective layer with a multi-layer interconnect structure as illustrated in the fifth embodiment of the present invention. Detailed Implementation

[0038] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, the same elements will be designated with the same symbols in the following description.

[0039] The terms "contains," "includes," and "has" used in this article are all open-ended, meaning "includes but not limited to."

[0040] Furthermore, the directional terms such as "up" and "down" mentioned in the text are only used to refer to the direction of the diagram and are not intended to limit the present invention.

[0041] When using terms such as "first" and "second" to describe elements, it is only for distinguishing these elements from one another and does not limit the order or importance of these elements. Therefore, in some cases, a first element may also be called a second element, and a second element may also be called a first element, without departing from the scope of the present invention.

[0042] In this document, the term "range from one value to another" is a concise way of representing a range to avoid listing all the values ​​in the range one by one in the specification. Therefore, the description of a particular range of values ​​covers any value within the range, as well as the smaller range of values ​​defined by any value within the range.

[0043] Figures 1A to 1C This is a cross-sectional schematic diagram illustrating the manufacturing process of a multi-layer interconnect structure according to the first embodiment of the present invention.

[0044] In this embodiment, the test element for optical critical dimension measurement and the reflective element for improving measurement accuracy are both disposed in the test area of ​​the substrate. Furthermore, the fabrication of the test element and the reflective element can be integrated with the fabrication of the circuit structure in the component area of ​​the substrate, but the invention is not limited thereto. Therefore, in this embodiment, the test element, the reflective element, and the circuit structure in the component area can be collectively referred to as a multilayer interconnect structure. The formation of the test element and the reflective element in the test area will be described below, and those skilled in the art should simultaneously understand the formation of the circuit structure in the component area.

[0045] First, refer to Figure 1AA substrate 100 is provided. In this embodiment, the substrate 100 includes a silicon substrate, various semiconductor elements and circuit structures formed on the silicon substrate, and a dielectric layer covering the silicon substrate. For clarity and ease of explanation, the various semiconductor elements, circuit structures, and dielectric layer described above are not illustrated. A dielectric layer 101 is then formed on the substrate 100. In the element region, the dielectric layer 101 may be referred to as an inter-alyer dielectric layer. Next, a patterned reflective layer 102 is formed on the substrate 100. The material of the patterned reflective layer 102 is, for example, a metal. The method for forming the patterned reflective layer 102 is, for example, to first form an opening in the dielectric layer 101 and then fill the opening with a metal material layer. In this embodiment, the step of forming the patterned reflective layer 102 may be integrated with the step of forming vias in the element region, but the invention is not limited thereto.

[0046] In this embodiment, the patterned reflective layer 102 includes a first reflective pattern 102a and a second reflective pattern 102b that are separated from each other by the dielectric layer 101. Figure 2A This is a top view schematic diagram of a patterned reflective layer with a multi-layer interconnect structure according to this embodiment. Figure 2A As shown, in this embodiment, the first reflective pattern 102a includes a plurality of parallel strip patterns 102a-1, and the second reflective pattern 102b includes a plurality of via patterns 102b-1. These via patterns 102b-1 are located between two adjacent strip patterns 102a-1. The via patterns 102b-1 and the strip patterns 102a-1 are separated from each other by the dielectric layer 101. In this embodiment, the via patterns 102b-1 located between two adjacent strip patterns 102a-1 are arranged in a row, but the invention is not limited to this. In other embodiments, these via patterns 102b-1 may also be arranged irregularly between two adjacent strip patterns 102a-1. Furthermore, in this embodiment, these via patterns 102b-1 have the same aperture, but the invention is not limited to this. In other embodiments, these via patterns 102b-1 may also have different apertures.

[0047] Next, refer to Figure 1B A bulk reflective layer 104 is formed on the dielectric layer 101. The material of the bulk reflective layer 104 is, for example, a metal. Figure 2B This is a top view schematic diagram of a blocky reflective layer with a multi-layer interconnect structure according to this embodiment. Figure 2BAs shown, the bulk reflective layer 104 has a large-area bulk structure located on the dielectric layer 101. The bulk reflective layer 104 can be formed, for example, by first forming a metal material layer on the dielectric layer 101, and then performing a patterning process on the metal material layer. The material of the bulk reflective layer 104 may be the same as or different from the material of the patterned reflective layer 102; this invention is not limited thereto. In this embodiment, the formation step of the patterned reflective layer 102 may be integrated with the formation step of the circuit layer in the component region, but this invention is not limited thereto. In this embodiment, the bulk reflective layer 104 is in contact with the patterned reflective layer 102, but this invention is not limited thereto. In other embodiments, depending on actual needs, the bulk reflective layer 104 may be separated from the patterned reflective layer 102 by a dielectric layer.

[0048] Then, refer to Figure 1C A dielectric layer 103 is formed on the bulk reflective layer 104. In this embodiment, the dielectric layer 103 is the same as the dielectric layer 101. In the component region, the dielectric layer 103 and the dielectric layer 101 can be considered as a single interlayer dielectric layer. Then, a patterned test layer 106 is formed on the bulk reflective layer 104 as a scattering test layer. The material of the patterned test layer 106 is, for example, a metal. Figure 2C This is a top view schematic diagram of a patterned test layer with a multi-layer interconnect structure as illustrated in this embodiment. Figure 2C As shown, in this embodiment, the patterned test layer 106 includes a plurality of parallel strip patterns, but the invention is not limited thereto. In other embodiments, the patterned test layer 106 may have other forms of patterns depending on actual needs. The patterned test layer 106 is formed, for example, by first forming trenches in the dielectric layer 103 and then filling the trenches with a metal material layer. In this embodiment, the formation step of the patterned test layer 106 may be integrated with the formation step of the circuit layer in the component region, but the invention is not limited thereto. In this way, the multilayer interconnect structure 10 of this embodiment is formed.

[0049] In the multilayer interconnect structure 10, the blocky reflective layer 104 is located directly below the patterned test layer 106, and the patterned reflective layer 102 is located directly below the blocky reflective layer 104. In this way, when performing optical critical dimension measurements, light can be projected onto the patterned test layer 106, and measurements can be performed based on the reflected light. Furthermore, since the blocky reflective layer 104 and the patterned reflective layer 102 are located below the patterned test layer 106, when light enters below the patterned test layer 106, the light is directly reflected and does not carry noise from the lower layers, ensuring measurement accuracy.

[0050] Furthermore, since the patterned reflective layer 102 and the block reflective layer 104, which together serve as a reflective structure, are disposed below the block reflective layer 104, the problem of light leakage caused by insufficient thickness of the reflective structure can be effectively avoided.

[0051] On the other hand, in this embodiment, the patterned reflective layer 102 includes reflective patterns of different sizes that are separated from each other, and the ratio of the projected area of ​​the patterned reflective layer 102 on the substrate 100 to the projected area of ​​the blocky reflective layer 104 on the substrate 100 is between 0.75 and 0.90. Therefore, the blocky reflective layer 104 can be effectively prevented from becoming disc-shaped in the subsequent grinding process to ensure the reflective effect.

[0052] In this embodiment, as Figure 2A As shown, the first reflective pattern 102a includes a plurality of parallel strip patterns 102a-1, and the second reflective pattern 102b includes a plurality of via patterns 102b-1, with the via patterns 102b-1 located between two adjacent strip patterns arranged in a row. However, the present invention is not limited thereto. In other embodiments, the patterned reflective layer 102 may include other types of reflective patterns, which will be described below.

[0053] Figure 3 This is a top view schematic diagram of a patterned reflective layer with a multilayer interconnect structure according to a second embodiment of the present invention. Figure 3 As shown, the difference between the patterned reflective layer 102 of this embodiment and the patterned reflective layer 102 of the first embodiment is that, in this embodiment, two rows of through-hole patterns 102b-1 are provided between two adjacent strip patterns 102a-1. Furthermore, similar to the first embodiment, in this embodiment, the ratio of the projected area of ​​the patterned reflective layer 102 on the substrate 100 to the projected area of ​​the block reflective layer 104 on the substrate 100 is between 0.75 and 0.90. Depending on actual needs, more rows of through-hole patterns 102b-1 can be provided between two adjacent strip patterns 102a-1.

[0054] Figure 4 This is a top view schematic diagram of a patterned reflective layer with a multilayer interconnect structure according to a third embodiment of the present invention. Figure 4As shown, the difference between the patterned reflective layer 102 in this embodiment and the patterned reflective layer 102 in the first embodiment is that, in this embodiment, the first reflective pattern 102a includes a block pattern 102a-2 with multiple openings 105, and the second reflective pattern 102b includes multiple through-hole patterns 102b-2, with one through-hole pattern 102b-2 located in one opening 105. Furthermore, similar to the first embodiment, in this embodiment, the ratio of the projected area of ​​the patterned reflective layer 102 on the substrate 100 to the projected area of ​​the block reflective layer 104 on the substrate 100 is between 0.75 and 0.90. Depending on actual needs, in other embodiments, multiple through-hole patterns 102b-2 may be provided in one opening 105, or the first reflective pattern 102a may include multiple block patterns 102a-2. Furthermore, the present invention does not limit the number or arrangement of the openings 105.

[0055] Figure 5 This is a top view schematic diagram of a patterned reflective layer with a multilayer interconnect structure according to a fourth embodiment of the present invention. Figure 5 As shown, the difference between the patterned reflective layer 102 in this embodiment and the patterned reflective layer 102 in the first embodiment is that, in this embodiment, the first reflective pattern 102a includes a plurality of first through-hole patterns 102a-3, and the second reflective pattern 102b includes a plurality of second through-hole patterns 102b-3, and the apertures of the first through-hole patterns 102a-3 and the second through-hole patterns 102b-3 are different from each other. Furthermore, similar to the first embodiment, in this embodiment, the ratio of the projected area of ​​the patterned reflective layer 102 on the substrate 100 to the projected area of ​​the blocky reflective layer 104 on the substrate 100 is between 0.75 and 0.90.

[0056] In this embodiment, the first via pattern 102a-3 is arranged in an array, and the second via pattern 102b-3 is also arranged in an array. The first via pattern 102a-3 with a smaller aperture is located between adjacent second via patterns 102b-3 with larger apertures, but the invention is not limited thereto. In other embodiments, the first via pattern 102a-3 and the second via pattern 102b-3 can be arranged in any manner depending on actual needs.

[0057] Figure 6 This is a top view schematic diagram of a patterned reflective layer with a multilayer interconnect structure according to the fifth embodiment of the present invention. Figure 6As shown, the difference between the patterned reflective layer 102 in this embodiment and the patterned reflective layer 102 in the fifth embodiment is that, in this embodiment, the patterned reflective layer 102 includes a first through-hole pattern 102a-3 and a second through-hole pattern 102b-3, as well as a third reflective pattern 102c, and the third reflective pattern 102c includes a plurality of third through-hole patterns 102c-1. The apertures of the first through-hole pattern 102a-3, the second through-hole pattern 102b-3, and the third through-hole pattern 102c-1 are different from each other. Furthermore, similar to the first embodiment, in this embodiment, the ratio of the projected area of ​​the patterned reflective layer 102 on the substrate 100 to the projected area of ​​the blocky reflective layer 104 on the substrate 100 is between 0.75 and 0.90.

[0058] In this embodiment, the first via pattern 102a-3, the second via pattern 102b-3, and the third via pattern 102c-1 are arranged in an array. The first via pattern 102a-3 with a smaller aperture is located between adjacent second via patterns 102b-3 with larger apertures, while the third via pattern 102c-1 with the smallest aperture surrounds the first via pattern 102a-3 and the second via pattern 102b-3. However, the present invention is not limited to this. In other embodiments, the first via pattern 102a-3, the second via pattern 102b-3, and the third via pattern 102c-1 can be arranged in any manner according to actual needs.

[0059] Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A multilayer interconnect structure having a scattering test layer, the multilayer interconnect structure comprising: A patterned reflective layer is disposed on a substrate and includes a first reflective pattern and a second reflective pattern that are separated from each other; A block-shaped reflective layer is disposed on the patterned reflective layer; as well as A patterned test layer is disposed on the blocky reflective layer. The ratio of the projected area of ​​the patterned reflective layer on the substrate to the projected area of ​​the blocky reflective layer on the substrate is between 0.75 and 0.

90.

2. The multilayer interconnect structure as claimed in claim 1, wherein the first reflective pattern comprises a plurality of parallel strip patterns, the second reflective pattern comprises a plurality of via patterns, and the via patterns are located between two adjacent strip patterns.

3. The multilayer interconnect structure as described in claim 2, wherein multiple rows of through-hole patterns are provided between two adjacent strip patterns.

4. The multilayer interconnect structure as claimed in claim 1, wherein the first reflective pattern comprises a block pattern having a plurality of openings, the second reflective pattern comprises a plurality of via patterns, and the plurality of via patterns are located in the plurality of openings.

5. The multilayer interconnect structure as claimed in claim 1, wherein the first reflective pattern includes a plurality of first via patterns, the second reflective pattern includes a plurality of second via patterns, and the apertures of the plurality of first via patterns and the apertures of the plurality of second via patterns are different from each other.

6. The multilayer interconnect structure as claimed in claim 1, wherein the patterned reflective layer further includes a third reflective pattern, the first reflective pattern includes a plurality of first via patterns, the second reflective pattern includes a plurality of second via patterns, the third reflective pattern includes a plurality of third via patterns, and the apertures of the plurality of first via patterns, the plurality of second via patterns, and the plurality of third via patterns are different from each other.

7. The multilayer interconnect structure as claimed in claim 1, wherein the material of the patterned reflective layer includes metal.

8. The multilayer interconnect structure as claimed in claim 1, wherein the material of the blocky reflective layer includes metal.

9. The multilayer interconnect structure as claimed in claim 1, wherein the blocky reflective layer is located directly below the patterned test layer, and the patterned reflective layer is located directly below the blocky reflective layer.

10. The multilayer interconnect structure as described in claim 1 further includes a dielectric layer disposed between the bulk reflective layer and the patterned test layer.

11. The multilayer interconnect structure as described in claim 1 further includes a dielectric layer disposed between the first reflective pattern and the second reflective pattern.

12. A method for manufacturing a multilayer interconnect structure, the multilayer interconnect structure having a scattering test layer, the method for manufacturing the multilayer interconnect structure comprising: A patterned reflective layer is formed on a substrate, wherein the patterned reflective layer includes a first reflective pattern and a second reflective pattern spaced apart from each other; A blocky reflective layer is formed on the patterned reflective layer; as well as A patterned test layer is formed on the blocky reflective layer. The ratio of the projected area of ​​the patterned reflective layer on the substrate to the projected area of ​​the blocky reflective layer on the substrate is between 0.75 and 0.

90.

13. The method for manufacturing a multilayer interconnect structure as claimed in claim 12, wherein the first reflective pattern comprises a plurality of parallel strip patterns, the second reflective pattern comprises a plurality of via patterns, and the via patterns are located between two adjacent strip patterns.

14. The method for manufacturing a multilayer interconnect structure as described in claim 13, wherein multiple rows of through-hole patterns are provided between two adjacent strip patterns.

15. The method for manufacturing a multilayer interconnect structure as claimed in claim 12, wherein the first reflective pattern comprises a block pattern having a plurality of openings, the second reflective pattern comprises a plurality of via patterns, and the plurality of via patterns are located in the plurality of openings.

16. The method for manufacturing a multilayer interconnect structure as claimed in claim 12, wherein the first reflective pattern includes a plurality of first via patterns, the second reflective pattern includes a plurality of second via patterns, and the apertures of the plurality of first via patterns and the apertures of the plurality of second via patterns are different from each other.

17. The method for manufacturing a multilayer interconnect structure as claimed in claim 12, wherein the patterned reflective layer further includes a third reflective pattern, the first reflective pattern includes a plurality of first via patterns, the second reflective pattern includes a plurality of second via patterns, the third reflective pattern includes a plurality of third via patterns, and the apertures of the plurality of first via patterns, the plurality of second via patterns, and the plurality of third via patterns are different from each other.

18. The method for manufacturing a multilayer interconnect structure as claimed in claim 12, wherein the blocky reflective layer is located directly below the patterned test layer, and the patterned reflective layer is located directly below the blocky reflective layer.

19. The method of manufacturing a multilayer interconnect structure as claimed in claim 12, wherein after forming the bulk reflective layer and before forming the patterned test layer, a dielectric layer is further formed on the bulk reflective layer.

20. The method for manufacturing a multilayer interconnect structure as claimed in claim 12, further comprising forming a dielectric layer between the first reflective pattern and the second reflective pattern.

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